powerpc/mpc85xx: Add TMU device tree support for T1023/T1024
authorHongtao Jia <hongtao.jia@freescale.com>
Tue, 24 Nov 2015 06:52:47 +0000 (14:52 +0800)
committerScott Wood <scottwood@freescale.com>
Thu, 24 Dec 2015 04:21:11 +0000 (22:21 -0600)
Also add nodes and properties for thermal management support. Meanwhile
preprocessor support is needed using thermal of framework.

Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
arch/powerpc/boot/dts/fsl/t1023rdb.dts
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
arch/powerpc/boot/dts/fsl/t1024qds.dts
arch/powerpc/boot/dts/fsl/t1024rdb.dts
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi

index 2b2fff4..6bd842b 100644 (file)
        };
 };
 
-/include/ "t1023si-post.dtsi"
+#include "t1023si-post.dtsi"
index 518ddaa..99e421d 100644 (file)
@@ -32,6 +32,8 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <dt-bindings/thermal/thermal.h>
+
 &ifc {
        #address-cells = <2>;
        #size-cells = <1>;
                reg = <0xea000 0x4000>;
        };
 
+       tmu: tmu@f0000 {
+               compatible = "fsl,qoriq-tmu";
+               reg = <0xf0000 0x1000>;
+               interrupts = <18 2 0 0>;
+               fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
+               fsl,tmu-calibration = <0x00000000 0x0000000f
+                                      0x00000001 0x00000017
+                                      0x00000002 0x0000001e
+                                      0x00000003 0x00000026
+                                      0x00000004 0x0000002e
+                                      0x00000005 0x00000035
+                                      0x00000006 0x0000003d
+                                      0x00000007 0x00000044
+                                      0x00000008 0x0000004c
+                                      0x00000009 0x00000053
+                                      0x0000000a 0x0000005b
+                                      0x0000000b 0x00000064
+
+                                      0x00010000 0x00000011
+                                      0x00010001 0x0000001c
+                                      0x00010002 0x00000024
+                                      0x00010003 0x0000002b
+                                      0x00010004 0x00000034
+                                      0x00010005 0x00000039
+                                      0x00010006 0x00000042
+                                      0x00010007 0x0000004c
+                                      0x00010008 0x00000051
+                                      0x00010009 0x0000005a
+                                      0x0001000a 0x00000063
+
+                                      0x00020000 0x00000013
+                                      0x00020001 0x00000019
+                                      0x00020002 0x00000024
+                                      0x00020003 0x0000002c
+                                      0x00020004 0x00000035
+                                      0x00020005 0x0000003d
+                                      0x00020006 0x00000046
+                                      0x00020007 0x00000050
+                                      0x00020008 0x00000059
+
+                                      0x00030000 0x00000002
+                                      0x00030001 0x0000000d
+                                      0x00030002 0x00000019
+                                      0x00030003 0x00000024>;
+               #thermal-sensor-cells = <0>;
+       };
+
+       thermal-zones {
+               cpu_thermal: cpu-thermal {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+
+                       thermal-sensors = <&tmu>;
+
+                       trips {
+                               cpu_alert: cpu-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+                               cpu_crit: cpu-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&cpu0 THERMAL_NO_LIMIT
+                                                       THERMAL_NO_LIMIT>;
+                               };
+                               map1 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&cpu1 THERMAL_NO_LIMIT
+                                                       THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+       };
+
        scfg: global-utilities@fc000 {
                compatible = "fsl,t1023-scfg";
                reg = <0xfc000 0x1000>;
index 43cd5b5..6a3581b 100644 (file)
        };
 };
 
-/include/ "t1024si-post.dtsi"
+#include "t1024si-post.dtsi"
index 429d8c7..0ccc7d0 100644 (file)
        };
 };
 
-/include/ "t1024si-post.dtsi"
+#include "t1024si-post.dtsi"
index 95e3af8..bb48034 100644 (file)
@@ -32,7 +32,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/include/ "t1023si-post.dtsi"
+#include "t1023si-post.dtsi"
 
 / {
        aliases {
index 3e1528a..9d08a36 100644 (file)
@@ -76,6 +76,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
+                       #cooling-cells = <2>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -85,6 +86,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
+                       #cooling-cells = <2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
                        };