Merge branch 'linus' into x86/cpu, to pick up fixes

Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --combined drivers/cpufreq/intel_pstate.c
index e1b7a5e,1fa1a32..28690b2
--- 1/drivers/cpufreq/intel_pstate.c
--- 2/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@@ -35,7 -35,6 +35,7 @@@
  #include <asm/msr.h>
  #include <asm/cpu_device_id.h>
  #include <asm/cpufeature.h>
 +#include <asm/intel-family.h>
  
  #define ATOM_RATIOS           0x66a
  #define ATOM_VIDS             0x66b
@@@ -373,26 -372,9 +373,9 @@@ static bool intel_pstate_get_ppc_enable
        return acpi_ppc;
  }
  
- /*
-  * The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and
-  * in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and
-  * max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state
-  * ratio, out of it only high 8 bits are used. For example 0x1700 is setting
-  * target ratio 0x17. The _PSS control value stores in a format which can be
-  * directly written to PERF_CTL MSR. But in intel_pstate driver this shift
-  * occurs during write to PERF_CTL (E.g. for cores core_set_pstate()).
-  * This function converts the _PSS control value to intel pstate driver format
-  * for comparison and assignment.
-  */
- static int convert_to_native_pstate_format(struct cpudata *cpu, int index)
- {
-       return cpu->acpi_perf_data.states[index].control >> 8;
- }
- 
  static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
  {
        struct cpudata *cpu;
-       int turbo_pss_ctl;
        int ret;
        int i;
  
@@@ -442,11 -424,10 +425,10 @@@
         * max frequency, which will cause a reduced performance as
         * this driver uses real max turbo frequency as the max
         * frequency. So correct this frequency in _PSS table to
-        * correct max turbo frequency based on the turbo ratio.
+        * correct max turbo frequency based on the turbo state.
         * Also need to convert to MHz as _PSS freq is in MHz.
         */
-       turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0);
-       if (turbo_pss_ctl > cpu->pstate.max_pstate)
+       if (!limits->turbo_disabled)
                cpu->acpi_perf_data.states[0].core_frequency =
                                        policy->cpuinfo.max_freq / 1000;
        cpu->valid_pss_table = true;
@@@ -1353,29 -1334,29 +1335,29 @@@ static void intel_pstate_update_util(st
                        (unsigned long)&policy }
  
  static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
 -      ICPU(0x2a, core_params),
 -      ICPU(0x2d, core_params),
 -      ICPU(0x37, silvermont_params),
 -      ICPU(0x3a, core_params),
 -      ICPU(0x3c, core_params),
 -      ICPU(0x3d, core_params),
 -      ICPU(0x3e, core_params),
 -      ICPU(0x3f, core_params),
 -      ICPU(0x45, core_params),
 -      ICPU(0x46, core_params),
 -      ICPU(0x47, core_params),
 -      ICPU(0x4c, airmont_params),
 -      ICPU(0x4e, core_params),
 -      ICPU(0x4f, core_params),
 -      ICPU(0x5e, core_params),
 -      ICPU(0x56, core_params),
 -      ICPU(0x57, knl_params),
 +      ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
 +      ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
 +      ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
 +      ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
 +      ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
 +      ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
 +      ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
 +      ICPU(INTEL_FAM6_HASWELL_X,              core_params),
 +      ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
 +      ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
 +      ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
 +      ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
 +      ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
 +      ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
 +      ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
 +      ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
 +      ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
        {}
  };
  MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
  
  static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
 -      ICPU(0x56, core_params),
 +      ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
        {}
  };
  
@@@ -1419,6 -1400,9 +1401,9 @@@ static void intel_pstate_set_update_uti
  {
        struct cpudata *cpu = all_cpu_data[cpu_num];
  
+       if (cpu->update_util_set)
+               return;
+ 
        /* Prevent intel_pstate_update_util() from using stale data. */
        cpu->sample.time = 0;
        cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
@@@ -1459,8 -1443,6 +1444,6 @@@ static int intel_pstate_set_policy(stru
        if (!policy->cpuinfo.max_freq)
                return -ENODEV;
  
-       intel_pstate_clear_update_util_hook(policy->cpu);
- 
        pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
                 policy->cpuinfo.max_freq, policy->max);