drm/radeon/kms: demystify evergreen blit code

some bits in 3D registers used by blit functions look like
magic and this is hard to follow; change them to a little bit
more meaningful pre-defined constants

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index f073dc9..5befd51 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -60,7 +60,9 @@ set_render_target(struct radeon_device *rdev, int format,
        if (h < 8)
                h = 8;
 
-       cb_color_info = ((format << 2) | (1 << 24) | (2 << 8));
+       cb_color_info = CB_FORMAT(format) |
+               CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
+               CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
        pitch = (w / 8) - 1;
        slice = ((w * h) / 64) - 1;
 
@@ -137,12 +139,16 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
        u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 
        /* high addr, stride */
-       sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
+       sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
+               SQ_VTXC_STRIDE(16);
 #ifdef __BIG_ENDIAN
-       sq_vtx_constant_word2 |= (2 << 30);
+       sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 #endif
        /* xyzw swizzles */
-       sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12);
+       sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
+               SQ_VTCX_SEL_Y(SQ_SEL_Y) |
+               SQ_VTCX_SEL_Z(SQ_SEL_Z) |
+               SQ_VTCX_SEL_W(SQ_SEL_W);
 
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
        radeon_ring_write(rdev, 0x580);
@@ -153,7 +159,7 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
        radeon_ring_write(rdev, 0);
        radeon_ring_write(rdev, 0);
        radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
+       radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
 
        if ((rdev->family == CHIP_CEDAR) ||
            (rdev->family == CHIP_PALM) ||
@@ -180,14 +186,19 @@ set_tex_resource(struct radeon_device *rdev,
        if (h < 1)
                h = 1;
 
-       sq_tex_resource_word0 = (1 << 0); /* 2D */
+       sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
        sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
                                  ((w - 1) << 18));
-       sq_tex_resource_word1 = ((h - 1) << 0) | (2 << 28);
+       sq_tex_resource_word1 = ((h - 1) << 0) |
+                               TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
        /* xyzw swizzles */
-       sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25);
+       sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
+                               TEX_DST_SEL_Y(SQ_SEL_Y) |
+                               TEX_DST_SEL_Z(SQ_SEL_Z) |
+                               TEX_DST_SEL_W(SQ_SEL_W);
 
-       sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30);
+       sq_tex_resource_word7 = format |
+               S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
 
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
        radeon_ring_write(rdev, 0);

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 7363d9d..b937c49 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -941,11 +941,15 @@
 #define        CB_COLOR0_SLICE                                 0x28c68
 #define        CB_COLOR0_VIEW                                  0x28c6c
 #define        CB_COLOR0_INFO                                  0x28c70
+#      define CB_FORMAT(x)                             ((x) << 2)
 #       define CB_ARRAY_MODE(x)                         ((x) << 8)
 #       define ARRAY_LINEAR_GENERAL                     0
 #       define ARRAY_LINEAR_ALIGNED                     1
 #       define ARRAY_1D_TILED_THIN1                     2
 #       define ARRAY_2D_TILED_THIN1                     4
+#      define CB_SOURCE_FORMAT(x)                      ((x) << 24)
+#      define CB_SF_EXPORT_FULL                        0
+#      define CB_SF_EXPORT_NORM                        1
 #define        CB_COLOR0_ATTRIB                                0x28c74
 #define        CB_COLOR0_DIM                                   0x28c78
 /* only CB0-7 blocks have these regs */
@@ -1107,15 +1111,53 @@
 #define        CB_COLOR7_CLEAR_WORD3                           0x28e3c
 
 #define SQ_TEX_RESOURCE_WORD0_0                         0x30000
+#      define TEX_DIM(x)                               ((x) << 0)
+#      define SQ_TEX_DIM_1D                            0
+#      define SQ_TEX_DIM_2D                            1
+#      define SQ_TEX_DIM_3D                            2
+#      define SQ_TEX_DIM_CUBEMAP                       3
+#      define SQ_TEX_DIM_1D_ARRAY                      4
+#      define SQ_TEX_DIM_2D_ARRAY                      5
+#      define SQ_TEX_DIM_2D_MSAA                       6
+#      define SQ_TEX_DIM_2D_ARRAY_MSAA                 7
 #define SQ_TEX_RESOURCE_WORD1_0                         0x30004
 #       define TEX_ARRAY_MODE(x)                        ((x) << 28)
 #define SQ_TEX_RESOURCE_WORD2_0                         0x30008
 #define SQ_TEX_RESOURCE_WORD3_0                         0x3000C
 #define SQ_TEX_RESOURCE_WORD4_0                         0x30010
+#      define TEX_DST_SEL_X(x)                         ((x) << 16)
+#      define TEX_DST_SEL_Y(x)                         ((x) << 19)
+#      define TEX_DST_SEL_Z(x)                         ((x) << 22)
+#      define TEX_DST_SEL_W(x)                         ((x) << 25)
+#      define SQ_SEL_X                                 0
+#      define SQ_SEL_Y                                 1
+#      define SQ_SEL_Z                                 2
+#      define SQ_SEL_W                                 3
+#      define SQ_SEL_0                                 4
+#      define SQ_SEL_1                                 5
 #define SQ_TEX_RESOURCE_WORD5_0                         0x30014
 #define SQ_TEX_RESOURCE_WORD6_0                         0x30018
 #define SQ_TEX_RESOURCE_WORD7_0                         0x3001c
 
+#define SQ_VTX_CONSTANT_WORD0_0                                0x30000
+#define SQ_VTX_CONSTANT_WORD1_0                                0x30004
+#define SQ_VTX_CONSTANT_WORD2_0                                0x30008
+#      define SQ_VTXC_BASE_ADDR_HI(x)                  ((x) << 0)
+#      define SQ_VTXC_STRIDE(x)                        ((x) << 8)
+#      define SQ_VTXC_ENDIAN_SWAP(x)                   ((x) << 30)
+#      define SQ_ENDIAN_NONE                           0
+#      define SQ_ENDIAN_8IN16                          1
+#      define SQ_ENDIAN_8IN32                          2
+#define SQ_VTX_CONSTANT_WORD3_0                                0x3000C
+#      define SQ_VTCX_SEL_X(x)                         ((x) << 3)
+#      define SQ_VTCX_SEL_Y(x)                         ((x) << 6)
+#      define SQ_VTCX_SEL_Z(x)                         ((x) << 9)
+#      define SQ_VTCX_SEL_W(x)                         ((x) << 12)
+#define SQ_VTX_CONSTANT_WORD4_0                                0x30010
+#define SQ_VTX_CONSTANT_WORD5_0                         0x30014
+#define SQ_VTX_CONSTANT_WORD6_0                         0x30018
+#define SQ_VTX_CONSTANT_WORD7_0                         0x3001c
+
 /* cayman 3D regs */
 #define CAYMAN_VGT_OFFCHIP_LDS_BASE                    0x89B0
 #define CAYMAN_DB_EQAA                                 0x28804