arm64: dts: mt8173: add MT8173 display PWM driver support node

Add display PWM node in mt8173-evb.dts and mt8173.dtsi.

Signed-off-by: YH Huang <yh.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 811cb76..1b3fabd 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -92,6 +92,13 @@
 };
 
 &pio {
+       disp_pwm0_pins: disp_pwm0_pins {
+               pins1 {
+                       pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
+                       output-low;
+               };
+       };
+
        mmc0_pins_default: mmc0default {
                pins_cmd_dat {
                        pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
@@ -190,6 +197,12 @@
        };
 };
 
+&pwm0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&disp_pwm0_pins>;
+       status = "okay";
+};
+
 &pwrap {
        pmic: mt6397 {
                compatible = "mediatek,mt6397";

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d301ce5..ed0047a 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -525,6 +525,28 @@
                        #clock-cells = <1>;
                };
 
+               pwm0: pwm@1401e000 {
+                       compatible = "mediatek,mt8173-disp-pwm",
+                                    "mediatek,mt6595-disp-pwm";
+                       reg = <0 0x1401e000 0 0x1000>;
+                       #pwm-cells = <2>;
+                       clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+                                <&mmsys CLK_MM_DISP_PWM0MM>;
+                       clock-names = "main", "mm";
+                       status = "disabled";
+               };
+
+               pwm1: pwm@1401f000 {
+                       compatible = "mediatek,mt8173-disp-pwm",
+                                    "mediatek,mt6595-disp-pwm";
+                       reg = <0 0x1401f000 0 0x1000>;
+                       #pwm-cells = <2>;
+                       clocks = <&mmsys CLK_MM_DISP_PWM126M>,
+                                <&mmsys CLK_MM_DISP_PWM1MM>;
+                       clock-names = "main", "mm";
+                       status = "disabled";
+               };
+
                imgsys: clock-controller@15000000 {
                        compatible = "mediatek,mt8173-imgsys", "syscon";
                        reg = <0 0x15000000 0 0x1000>;