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ARC: [axs10x] cap ethernet phy to 100 Mbit/sec
author
Alexey Brodkin
<abrodkin@synopsys.com>
Mon, 7 Dec 2015 11:21:37 +0000
(14:21 +0300)
committer
Vineet Gupta
<vgupta@synopsys.com>
Mon, 7 Dec 2015 14:10:03 +0000
(19:40 +0530)
Current ARC SDP boards cannot reliably handle 1Gbit
Ethernet connections due to limitations in hardware.
To make sure networking is stable on the board we're
limiting phy to 100 Mbit.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/boot/dts/axs10x_mb.dtsi
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diff --git
a/arch/arc/boot/dts/axs10x_mb.dtsi
b/arch/arc/boot/dts/axs10x_mb.dtsi
index
f3db321
..
44a578c
100644
(file)
--- a/
arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/
arch/arc/boot/dts/axs10x_mb.dtsi
@@
-46,6
+46,7
@@
snps,pbl = < 32 >;
clocks = <&apbclk>;
clock-names = "stmmaceth";
+ max-speed = <100>;
};
ehci@0x40000 {