CHROMIUM: usb: dwc3: Add delay of 10ms to allow phy clk to stabilise

Adds the delay of 10ms once the gpio line for phy clk is pulled high,
to allow the clock to stabilise.

BUG=chrome-os-partner:13972
TEST=1>booted kernel with USB 3.0 device connected on 3.0 port,
device detected and enumerated.
2>run 'powerd_suspend' while usb 3.0 device is connected on 3.0 port,
system resumes successfully, device detected and enumerated.

Change-Id: I9cc5ad96427b16ce0c7d6fb12b5ff802f27c5f2c
Signed-off-by: Jaehoon Kim <jh228.kim@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/33299
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 4f37d98..8ec051c 100644 (file)
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -24,6 +24,7 @@
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
+#include <linux/delay.h>
 
 #include <plat/usb-phy.h>
 
@@ -250,9 +251,17 @@ static int dwc3_exynos_runtime_resume(struct device *dev)
 
        dev_dbg(dev, "entering runtime resume\n");
 
-       if (gpio_is_valid(exynos->phyclk_gpio))
+       if (gpio_is_valid(exynos->phyclk_gpio)) {
                gpio_set_value(exynos->phyclk_gpio, 1);
 
+               /*
+                * PI6C557-03 clock generator needs 3ms typically to stabilise,
+                * but the datasheet doesn't list max.  We'll sleep for 10ms
+                * and cross our fingers that it's enough.
+                */
+               msleep(10);
+       }
+
        if (!pdata) {
                dev_dbg(&pdev->dev, "missing platform data\n");
        } else {
@@ -304,8 +313,11 @@ static int dwc3_exynos_resume(struct device *dev)
         * later if the system decides we want to be runtime
         * suspended again.
         */
-       if (gpio_is_valid(exynos->phyclk_gpio))
+       if (gpio_is_valid(exynos->phyclk_gpio)) {
                gpio_set_value(exynos->phyclk_gpio, 1);
+               /* PI6C557 clock generator needs 3ms to stabilise */
+               mdelay(3);
+       }
 
        clk_enable(exynos->clk);