ARM: shmobile: r8a7794: Add DU0 clock
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Mon, 16 Nov 2015 08:57:11 +0000 (17:57 +0900)
committerSimon Horman <horms+renesas@verge.net.au>
Tue, 17 Nov 2015 18:29:55 +0000 (10:29 -0800)
The DU0 clock is an MSTP clock, child of the CPG ZX clock.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7794.dtsi
include/dt-bindings/clock/r8a7794-clock.h

index 018ff56..b70e406 100644 (file)
                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
                        clocks = <&mp_clk>, <&mp_clk>,
                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
-                                <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
+                                <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                <&zx_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
                                R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
                                R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
                                R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
                                R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
-                               R8A7794_CLK_SCIF0
+                               R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
                        >;
                        clock-output-names =
                                "ehci", "hsusb",
                                "hscif2", "scif5", "scif4", "hscif1", "hscif0",
-                               "scif3", "scif2", "scif1", "scif0";
+                               "scif3", "scif2", "scif1", "scif0", "du0";
                };
                mstp8_clks: mstp8_clks@e6150990 {
                        compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
index 09da38a..a7a7e03 100644 (file)
@@ -79,6 +79,7 @@
 #define R8A7794_CLK_SCIF2              19
 #define R8A7794_CLK_SCIF1              20
 #define R8A7794_CLK_SCIF0              21
+#define R8A7794_CLK_DU0                        24
 
 /* MSTP8 */
 #define R8A7794_CLK_VIN1               10