Merge tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm...

Pull intel drm fixes from Jani Nikula:
 "Almost all of it is regression fixes all around, with cc: stable, and
  then there's Ander's fix for one of the warnings you reported.  We're
  still working on the rest"

[ Dave is on vacation, and Jani is heading out on vacation too ]

* tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel()
  drm/i915: fix backlight after resume on 855gm
  agp/intel: Fix typo in needs_ilk_vtd_wa()
  drm/i915/ppgtt: Break loop in gen8_ppgtt_clear_range failure path
  drm/i915: Fix IPS related flicker

diff --combined drivers/gpu/drm/i915/i915_reg.h
index f5edb35,47bb110..2030f60
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -3491,6 -3491,7 +3491,7 @@@ enum skl_disp_power_wells 
  #define   BLM_POLARITY_PNV                    (1 << 0) /* pnv only */
  
  #define BLC_HIST_CTL  (dev_priv->info.display_mmio_offset + 0x61260)
+ #define  BLM_HISTOGRAM_ENABLE                 (1 << 31)
  
  /* New registers for PCH-split platforms. Safe where new bits show up, the
   * register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@@ -6941,9 -6942,6 +6942,9 @@@
  #define   AUDIO_CP_READY(trans)               ((1 << 1) << ((trans) * 4))
  #define   AUDIO_ELD_VALID(trans)      ((1 << 0) << ((trans) * 4))
  
 +#define HSW_AUD_CHICKENBIT                    0x65f10
 +#define   SKL_AUD_CODEC_WAKE_SIGNAL           (1 << 15)
 +
  /* HSW Power Wells */
  #define HSW_PWR_WELL_BIOS                     0x45400 /* CTL1 */
  #define HSW_PWR_WELL_DRIVER                   0x45404 /* CTL2 */

diff --combined drivers/gpu/drm/i915/intel_dp.c
index 76afc62,16c86ce..6e8faa2
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -893,8 -893,10 +893,8 @@@ intel_dp_aux_ch(struct intel_dp *intel_
                                continue;
                        }
                        if (status & DP_AUX_CH_CTL_DONE)
 -                              break;
 +                              goto done;
                }
 -              if (status & DP_AUX_CH_CTL_DONE)
 -                      break;
        }
  
        if ((status & DP_AUX_CH_CTL_DONE) == 0) {
@@@ -903,7 -905,6 +903,7 @@@
                goto out;
        }
  
 +done:
        /* Check for timeout or receive error.
         * Timeouts occur when the sink is not connected
         */
@@@ -1140,6 -1141,9 +1140,9 @@@ skl_edp_set_pll_config(struct intel_crt
  static void
  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
  {
+       memset(&pipe_config->dpll_hw_state, 0,
+              sizeof(pipe_config->dpll_hw_state));
+ 
        switch (link_bw) {
        case DP_LINK_BW_1_62:
                pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;