Merge tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm...

Pull intel drm fixes from Jani Nikula:
 "Almost all of it is regression fixes all around, with cc: stable, and
  then there's Ander's fix for one of the warnings you reported.  We're
  still working on the rest"

[ Dave is on vacation, and Jani is heading out on vacation too ]

* tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel()
  drm/i915: fix backlight after resume on 855gm
  agp/intel: Fix typo in needs_ilk_vtd_wa()
  drm/i915/ppgtt: Break loop in gen8_ppgtt_clear_range failure path
  drm/i915: Fix IPS related flicker

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0b4188b..c6dea3f 100644 (file)
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -581,7 +581,7 @@ static inline int needs_ilk_vtd_wa(void)
        /* Query intel_iommu to see if we need the workaround. Presumably that
         * was loaded first.
         */
-       if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
+       if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||
             gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
             intel_iommu_gfx_mapped)
                return 1;

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 619dad1..9daa288 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -516,17 +516,17 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
                struct page *page_table;
 
                if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
-                       continue;
+                       break;
 
                pd = ppgtt->pdp.page_directory[pdpe];
 
                if (WARN_ON(!pd->page_table[pde]))
-                       continue;
+                       break;
 
                pt = pd->page_table[pde];
 
                if (WARN_ON(!pt->page))
-                       continue;
+                       break;
 
                page_table = pt->page;
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5edb35..2030f60 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3491,6 +3491,7 @@ enum skl_disp_power_wells {
 #define   BLM_POLARITY_PNV                     (1 << 0) /* pnv only */
 
 #define BLC_HIST_CTL   (dev_priv->info.display_mmio_offset + 0x61260)
+#define  BLM_HISTOGRAM_ENABLE                  (1 << 31)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
  * register layout machtes with gen4 BLC_PWM_CTL[12]. */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dcb1d25..1b61f98 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13303,6 +13303,16 @@ intel_check_primary_plane(struct drm_plane *plane,
                                intel_crtc->atomic.wait_vblank = true;
                }
 
+               /*
+                * FIXME: Actually if we will still have any other plane enabled
+                * on the pipe we could let IPS enabled still, but for
+                * now lets consider that when we make primary invisible
+                * by setting DSPCNTR to 0 on update_primary_plane function
+                * IPS needs to be disable.
+                */
+               if (!state->visible || !fb)
+                       intel_crtc->atomic.disable_ips = true;
+
                intel_crtc->atomic.fb_bits |=
                        INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
 
@@ -13400,6 +13410,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc)
        if (intel_crtc->atomic.disable_fbc)
                intel_fbc_disable(dev);
 
+       if (intel_crtc->atomic.disable_ips)
+               hsw_disable_ips(intel_crtc);
+
        if (intel_crtc->atomic.pre_disable_primary)
                intel_pre_disable_primary(crtc);
 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76afc62..6e8faa2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1140,6 +1140,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 static void
 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
 {
+       memset(&pipe_config->dpll_hw_state, 0,
+              sizeof(pipe_config->dpll_hw_state));
+
        switch (link_bw) {
        case DP_LINK_BW_1_62:
                pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2afb31a..1059283 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -485,6 +485,7 @@ struct intel_crtc_atomic_commit {
        /* Sleepable operations to perform before commit */
        bool wait_for_flips;
        bool disable_fbc;
+       bool disable_ips;
        bool pre_disable_primary;
        bool update_wm;
        unsigned disabled_planes;

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 7d83527..55aad23 100644 (file)
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
 
        /* XXX: combine this into above write? */
        intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+       /*
+        * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
+        * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
+        * that has backlight.
+        */
+       if (IS_GEN2(dev))
+               I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
 }
 
 static void i965_enable_backlight(struct intel_connector *connector)