clk: tegra: Fix some static checker problems

The latest Tegra clk pull had some problems. Fix them.

drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 109a79b..c2ff859 100644 (file)
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -587,7 +587,7 @@ static void dfll_load_i2c_lut(struct tegra_dfll *td)
                else
                        lut_index = i;
 
-                 val = regulator_list_hardware_vsel(td->vdd_reg,
+               val = regulator_list_hardware_vsel(td->vdd_reg,
                                                     td->i2c_lut[lut_index]);
                __raw_writel(val, td->lut_base + i * 4);
        }
@@ -1432,6 +1432,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td)
        int selector;
        unsigned long rate;
        struct dev_pm_opp *opp;
+       int lut;
 
        rcu_read_lock();
 
@@ -1444,9 +1445,10 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td)
        v_max = dev_pm_opp_get_voltage(opp);
 
        v = td->soc->min_millivolts * 1000;
-       td->i2c_lut[0] = find_vdd_map_entry_exact(td, v);
-       if (td->i2c_lut[0] < 0)
+       lut = find_vdd_map_entry_exact(td, v);
+       if (lut < 0)
                goto out;
+       td->i2c_lut[0] = lut;
 
        for (j = 1, rate = 0; ; rate++) {
                opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index a9e2b30..824d758 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1447,7 +1447,7 @@ static void tegra124_car_barrier(void)
  *
  * Assert the reset line of the DFLL's DVCO.  No return value.
  */
-void tegra124_clock_assert_dfll_dvco_reset(void)
+static void tegra124_clock_assert_dfll_dvco_reset(void)
 {
        u32 v;
 
@@ -1463,7 +1463,7 @@ void tegra124_clock_assert_dfll_dvco_reset(void)
  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
  * operate.  No return value.
  */
-void tegra124_clock_deassert_dfll_dvco_reset(void)
+static void tegra124_clock_deassert_dfll_dvco_reset(void)
 {
        u32 v;
 
@@ -1473,7 +1473,7 @@ void tegra124_clock_deassert_dfll_dvco_reset(void)
        tegra124_car_barrier();
 }
 
-int tegra124_reset_assert(unsigned long id)
+static int tegra124_reset_assert(unsigned long id)
 {
        if (id == TEGRA124_RST_DFLL_DVCO)
                tegra124_clock_assert_dfll_dvco_reset();
@@ -1483,7 +1483,7 @@ int tegra124_reset_assert(unsigned long id)
        return 0;
 }
 
-int tegra124_reset_deassert(unsigned long id)
+static int tegra124_reset_deassert(unsigned long id)
 {
        if (id == TEGRA124_RST_DFLL_DVCO)
                tegra124_clock_deassert_dfll_dvco_reset();