default y
select HAVE_AOUT
select HAVE_DMA_API_DEBUG
- select HAVE_IDE
+ select HAVE_IDE if PCI || ISA || PCMCIA
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
select GENERIC_IRQ_SHOW
+ select CPU_PM if (SUSPEND || CPU_IDLE)
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
The base address of exception vectors.
config ARM_PATCH_PHYS_VIRT
- bool "Patch physical to virtual translations at runtime"
+ bool "Patch physical to virtual translations at runtime" if EMBEDDED
+ default y
depends on !XIP_KERNEL && MMU
depends on !ARCH_REALVIEW || !SPARSEMEM
help
kernel in system memory.
This can only be used with non-XIP MMU kernels where the base
- of physical memory is at a 16MB boundary, or theoretically 64K
- for the MSM machine class.
+ of physical memory is at a 16MB boundary.
-config ARM_PATCH_PHYS_VIRT_16BIT
- def_bool y
- depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
+ Only disable this option if you know that you do not require
+ this feature (eg, building a kernel for a single machine) and
+ you need to shrink the kernel to the minimal size.
+
+config NEED_MACH_MEMORY_H
+ bool
+ help
+ Select this when mach/memory.h is required to provide special
+ definitions for this platform. The need for mach/memory.h should
+ be avoided when possible.
+
+config PHYS_OFFSET
+ hex "Physical address of main memory"
+ depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
help
- This option extends the physical to virtual translation patching
- to allow physical memory down to a theoretical minimum of 64K
- boundaries.
+ Please provide the physical address corresponding to the
+ location of main memory in your system.
+
+config GENERIC_BUG
+ def_bool y
+ depends on BUG
source "init/Kconfig"
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
select PLAT_VERSATILE_FPGA_IRQ
+ select NEED_MACH_MEMORY_H
help
Support for ARM's Integrator platform.
select PLAT_VERSATILE_CLCD
select ARM_TIMER_SP804
select GPIO_PL061 if GPIOLIB
+ select NEED_MACH_MEMORY_H
help
This enables support for ARM Ltd RealView boards.
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select CLKDEV_LOOKUP
- select ARM_PATCH_PHYS_VIRT if MMU
help
This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 and AT91CAP9 processors.
help
Support for Broadcom's BCMRing platform.
+config ARCH_HIGHBANK
+ bool "Calxeda Highbank-based"
+ select ARCH_WANT_OPTIONAL_GPIOLIB
+ select ARM_AMBA
+ select ARM_GIC
+ select ARM_TIMER_SP804
+ select CLKDEV_LOOKUP
+ select CPU_V7
+ select GENERIC_CLOCKEVENTS
+ select HAVE_ARM_SCU
+ select USE_OF
+ help
+ Support for the Calxeda Highbank SoC based boards.
+
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x-based"
select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
Support for Cirrus Logic 711x/721x based boards.
config ARCH_PRIMA2
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
select CPU_V7
- select GENERIC_TIME
select NO_IOPORT
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
select ISA
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
This is an evaluation board for the StrongARM processor available
from Digital. It has limited hardware on-board, including an
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
This enables support for the Cirrus EP93xx series of CPUs.
select CPU_SA110
select FOOTBRIDGE
select GENERIC_CLOCKEVENTS
+ select HAVE_IDE
+ select NEED_MACH_MEMORY_H
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
select PCI
select ARCH_SUPPORTS_MSI
select VMSPLIT_1G
+ select NEED_MACH_MEMORY_H
help
Support for Intel's IOP13XX (XScale) family of processors.
select CPU_XSC3
select PCI
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
Support for Intel's IXP23xx (XScale) family of processors.
select CPU_XSCALE
select PCI
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
Support for Intel's IXP2400/2800 (XScale) family of processors.
select ARM_AMBA
select USB_ARCH_HAS_OHCI
select CLKDEV_LOOKUP
- select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
Support for the NXP LPC32XX family of processors
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
+ select GENERIC_ALLOCATOR
help
Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
select CPU_ARM922T
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
System-on-Chip devices.
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
-config ARCH_NUC93X
- bool "Nuvoton NUC93X CPU"
- select CPU_ARM926T
- select CLKDEV_LOOKUP
- help
- Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
- low-power and high performance MPEG-4/JPEG multimedia controller chip.
-
config ARCH_TEGRA
bool "NVIDIA Tegra"
select CLKDEV_LOOKUP
select CLKSRC_MMIO
- select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
select HAVE_CLK
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
+config ARCH_PICOXCELL
+ bool "Picochip picoXcell"
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_PATCH_PHYS_VIRT
+ select ARM_VIC
+ select CPU_V6K
+ select DW_APB_TIMER
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_GPIO
+ select HAVE_SCHED_CLOCK
+ select HAVE_TCM
+ select NO_IOPORT
+ select USE_OF
+ help
+ This enables support for systems based on the Picochip picoXcell
+ family of Femtocell devices. The picoxcell support requires device tree
+ for all boards.
+
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
select SPARSE_IRQ
select AUTO_ZRELADDR
select MULTI_IRQ_HANDLER
+ select ARM_CPU_SUSPEND if PM
+ select HAVE_IDE
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
select SPARSE_IRQ
select MULTI_IRQ_HANDLER
select PM_GENERIC_DOMAINS if PM
+ select NEED_MACH_MEMORY_H
help
Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
select NO_IOPORT
select ARCH_SPARSEMEM_ENABLE
select ARCH_USES_GETTIMEOFFSET
+ select HAVE_IDE
+ select NEED_MACH_MEMORY_H
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
CD-ROM interface, serial and parallel port, and the floppy drive.
select HAVE_SCHED_CLOCK
select TICK_ONESHOT
select ARCH_REQUIRE_GPIOLIB
+ select HAVE_IDE
+ select NEED_MACH_MEMORY_H
help
Support for StrongARM 11x0 based boards.
select CPU_V6
select ARM_VIC
select HAVE_CLK
+ select HAVE_TCM
select CLKDEV_LOOKUP
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
select ARCH_REQUIRE_GPIOLIB
select SAMSUNG_CLKSRC
select SAMSUNG_IRQ_VIC_TIMER
- select SAMSUNG_IRQ_UART
select S3C_GPIO_TRACK
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
+ select NEED_MACH_MEMORY_H
help
Samsung S5PV210/S5PC110 series based systems
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
+ select NEED_MACH_MEMORY_H
help
Samsung EXYNOS4 series based systems
select ZONE_DMA
select PCI
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_MEMORY_H
help
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
select HAVE_SCHED_CLOCK
select HAVE_TCM
select ARM_AMBA
+ select ARM_PATCH_PHYS_VIRT
select ARM_VIC
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ select NEED_MACH_MEMORY_H
help
Support for ST-Ericsson U300 series mobile platforms.
config ARCH_ZYNQ
bool "Xilinx Zynq ARM Cortex A9 Platform"
select CPU_V7
- select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
select ARM_GIC
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/plat-nomadik/Kconfig"
-source "arch/arm/mach-nuc93x/Kconfig"
-
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
- ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
+ depends on MMU
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
help
processor machines. On a single processor machine, the kernel will
run faster if you say N here.
- See also <file:Documentation/i386/IO-APIC.txt>,
+ See also <file:Documentation/x86/i386/IO-APIC.txt>,
<file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
<http://tldp.org/HOWTO/SMP-HOWTO.html>.
If you don't know what to do here, say Y.
+config ARM_CPU_TOPOLOGY
+ bool "Support cpu topology definition"
+ depends on SMP && CPU_V7
+ default y
+ help
+ Support ARM cpu topology definition. The MPIDR register defines
+ affinity between processors which is then used to describe the cpu
+ topology of an ARM System.
+
+config SCHED_MC
+ bool "Multi-core scheduler support"
+ depends on ARM_CPU_TOPOLOGY
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+ bool "SMT scheduler support"
+ depends on ARM_CPU_TOPOLOGY
+ help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
config HAVE_ARM_SCU
bool
help
depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
select AEABI
select ARM_ASM_UNIFIED
+ select ARM_UNWIND
help
By enabling this option, the kernel will be compiled in
Thumb-2 mode. A compiler/assembler that understand the unified
endchoice
+config ARM_APPENDED_DTB
+ bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
+ depends on OF && !ZBOOT_ROM && EXPERIMENTAL
+ help
+ With this option, the boot code will look for a device tree binary
+ (DTB) appended to zImage
+ (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
+
+ This is meant as a backward compatibility convenience for those
+ systems with a bootloader that can't be upgraded to accommodate
+ the documented boot protocol using a device tree.
+
+ Beware that there is very little in terms of protection against
+ this option being confused by leftover garbage in memory that might
+ look like a DTB header after a reboot if no actual DTB is appended
+ to zImage. Do not leave this option active in a production kernel
+ if you don't intend to always append a DTB. Proper passing of the
+ location into r2 of a bootloader provided DTB is always preferable
+ to this option.
+
+config ARM_ATAG_DTB_COMPAT
+ bool "Supplement the appended DTB with traditional ATAG information"
+ depends on ARM_APPENDED_DTB
+ help
+ Some old bootloaders can't be updated to a DTB capable one, yet
+ they provide ATAGs with memory configuration, the ramdisk address,
+ the kernel cmdline string, etc. Such information is dynamically
+ provided by the bootloader and can't always be stored in a static
+ DTB. To allow a device tree enabled kernel to be used with such
+ bootloaders, this option allows zImage to extract the information
+ from the ATAG list and store it at run time into the appended DTB.
+
config CMDLINE
string "Default kernel command string"
default ""
bool
depends on CPU_FREQ && ARCH_PXA && PXA25x
default y
+ select CPU_FREQ_TABLE
select CPU_FREQ_DEFAULT_GOV_USERSPACE
config CPU_FREQ_S3C
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
+config ARM_CPU_SUSPEND
+ def_bool PM_SLEEP
+
endmenu
source "net/Kconfig"
#include <linux/pwm_backlight.h>
#include <video/platform_lcd.h>
+ #include <media/m5mols.h>
+ #include <media/s5p_fimc.h>
+ #include <media/v4l2-mediabus.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/iic.h>
#include <plat/mfc.h>
#include <plat/pd.h>
+ #include <plat/fimc-core.h>
+ #include <plat/camport.h>
+ #include <plat/mipi_csis.h>
#include <mach/map.h>
enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
FIXED_REG_ID_MAX8903,
+ FIXED_REG_ID_CAM_A28V,
+ FIXED_REG_ID_CAM_12V,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
},
};
- static struct device *nuri_cm_devices[] = {
- &s3c_device_i2c5.dev,
- &s3c_device_adc.dev,
- NULL, /* Reserved for UART */
- NULL,
- };
-
static void __init nuri_power_init(void)
{
int gpio;
s5p_ehci_set_platdata(pdata);
}
+ /* CAMERA */
+ static struct regulator_consumer_supply cam_vdda_supply[] = {
+ REGULATOR_SUPPLY("a_sensor", "0-001f"),
+ };
+
+ static struct regulator_init_data cam_vdda_reg_init_data = {
+ .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+ .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
+ .consumer_supplies = cam_vdda_supply,
+ };
+
+ static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
+ .supply_name = "CAM_IO_EN",
+ .microvolts = 2800000,
+ .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */
+ .enable_high = 1,
+ .init_data = &cam_vdda_reg_init_data,
+ };
+
+ static struct platform_device cam_vdda_fixed_rdev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
+ .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
+ };
+
+ static struct regulator_consumer_supply camera_8m_12v_supply =
+ REGULATOR_SUPPLY("dig_12", "0-001f");
+
+ static struct regulator_init_data cam_8m_12v_reg_init_data = {
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &camera_8m_12v_supply,
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS
+ },
+ };
+
+ static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
+ .supply_name = "8M_1.2V",
+ .microvolts = 1200000,
+ .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+ .enable_high = 1,
+ .init_data = &cam_8m_12v_reg_init_data,
+ };
+
+ static struct platform_device cam_8m_12v_fixed_rdev = {
+ .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
+ .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
+ };
+
+ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+ .clk_rate = 166000000UL,
+ .lanes = 2,
+ .alignment = 32,
+ .hs_settle = 12,
+ .phy_enable = s5p_csis_phy_enable,
+ };
+
+ #define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
+ #define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5)
+
+ static struct m5mols_platform_data m5mols_platdata = {
+ .gpio_reset = GPIO_CAM_MEGA_RST,
+ };
+
+ static struct i2c_board_info m5mols_board_info = {
+ I2C_BOARD_INFO("M5MOLS", 0x1F),
+ .platform_data = &m5mols_platdata,
+ };
+
+ static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
+ {
+ .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+ V4L2_MBUS_VSYNC_ACTIVE_LOW,
+ .bus_type = FIMC_MIPI_CSI2,
+ .board_info = &m5mols_board_info,
+ .clk_frequency = 24000000UL,
+ .csi_data_align = 32,
+ },
+ };
+
+ static struct s5p_platform_fimc fimc_md_platdata = {
+ .isp_info = nuri_camera_sensors,
+ .num_clients = ARRAY_SIZE(nuri_camera_sensors),
+ };
+
+ static struct gpio nuri_camera_gpios[] = {
+ { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
+ { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
+ };
+
+ static void nuri_camera_init(void)
+ {
+ s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+ &s5p_device_mipi_csis0);
+ s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
+ &s5p_device_fimc_md);
+
+ if (gpio_request_array(nuri_camera_gpios,
+ ARRAY_SIZE(nuri_camera_gpios))) {
+ pr_err("%s: GPIO request failed\n", __func__);
+ return;
+ }
+
+ m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
+ if (!IS_ERR_VALUE(m5mols_board_info.irq))
+ s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
+ else
+ pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
+
+ /* Free GPIOs controlled directly by the sensor drivers. */
+ gpio_free(GPIO_CAM_MEGA_RST);
+
+ if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
+ pr_err("%s: Camera port A setup failed\n", __func__);
+ return;
+ }
+ /* Increase drive strength of the sensor clock output */
+ s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
+ }
+
+ static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
+ .frequency = 400000U,
+ .sda_delay = 200,
+ };
+
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&s3c_device_i2c5, /* PMIC should initialize first */
+ &s3c_device_i2c0,
&emmc_fixed_voltage,
+ &s5p_device_mipi_csis0,
+ &s5p_device_fimc0,
+ &s5p_device_fimc1,
+ &s5p_device_fimc2,
+ &s5p_device_fimc3,
&s5p_device_fimd0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_LCD0],
+ &exynos4_device_pd[PD_CAM],
+ &s5p_device_fimc_md,
/* NURI Devices */
&nuri_gpio_keys,
&nuri_backlight_device,
&max8903_fixed_reg_dev,
&nuri_max8903_device,
+ &cam_vdda_fixed_rdev,
+ &cam_8m_12v_fixed_rdev,
};
static void __init nuri_map_io(void)
nuri_tsp_init();
nuri_power_init();
+ s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
s3c_i2c3_set_platdata(&i2c3_data);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s5p_fimd0_set_platdata(&nuri_fb_pdata);
+ nuri_camera_init();
+
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+ s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+ s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
}
MACHINE_START(NURI, "NURI")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
- .boot_params = S5P_PA_SDRAM + 0x100,
+ .atag_offset = 0x100,
.init_irq = exynos4_init_irq,
.map_io = nuri_map_io,
.init_machine = nuri_machine_init,
projects / cascardo / linux.git / commitdiff