PCI: altera: Move retrain from fixup to altera_pcie_host_init()

Previously we used a PCI early fixup to initiate a link retrain on Altera
devices.  But Altera PCIe IP can be configured as either a Root Port or an
Endpoint, and they might have same vendor ID, so the fixup would be run for
both.

We only want to initiate a link retrain for Altera Root Port devices, not
for Endpoints, so move the link retrain functionality from the fixup to
altera_pcie_host_init().

[bhelgaas: changelog]
Signed-off-by: Ley Foon Tan <lftan@altera.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 34e6258..4ca50a2 100644 (file)
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -43,6 +43,7 @@
 #define RP_LTSSM_MASK                  0x1f
 #define LTSSM_L0                       0xf
 
+#define PCIE_CAP_OFFSET                        0x80
 /* TLP configuration type 0 and 1 */
 #define TLP_FMTTYPE_CFGRD0             0x04    /* Configuration Read Type 0 */
 #define TLP_FMTTYPE_CFGWR0             0x44    /* Configuration Write Type 0 */
@@ -100,66 +101,6 @@ static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
        return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 }
 
-static void altera_wait_link_retrain(struct pci_dev *dev)
-{
-       u16 reg16;
-       unsigned long start_jiffies;
-       struct altera_pcie *pcie = dev->bus->sysdata;
-
-       /* Wait for link training end. */
-       start_jiffies = jiffies;
-       for (;;) {
-               pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &reg16);
-               if (!(reg16 & PCI_EXP_LNKSTA_LT))
-                       break;
-
-               if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
-                       dev_err(&pcie->pdev->dev, "link retrain timeout\n");
-                       break;
-               }
-               udelay(100);
-       }
-
-       /* Wait for link is up */
-       start_jiffies = jiffies;
-       for (;;) {
-               if (altera_pcie_link_is_up(pcie))
-                       break;
-
-               if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
-                       dev_err(&pcie->pdev->dev, "link up timeout\n");
-                       break;
-               }
-               udelay(100);
-       }
-}
-
-static void altera_pcie_retrain(struct pci_dev *dev)
-{
-       u16 linkcap, linkstat;
-       struct altera_pcie *pcie = dev->bus->sysdata;
-
-       if (!altera_pcie_link_is_up(pcie))
-               return;
-
-       /*
-        * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
-        * current speed is 2.5 GB/s.
-        */
-       pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
-
-       if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
-               return;
-
-       pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
-       if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
-               pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
-                                        PCI_EXP_LNKCTL_RL);
-               altera_wait_link_retrain(dev);
-       }
-}
-DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
-
 /*
  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
@@ -434,6 +375,90 @@ static struct pci_ops altera_pcie_ops = {
        .write = altera_pcie_cfg_write,
 };
 
+static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
+                               unsigned int devfn, int offset, u16 *value)
+{
+       u32 data;
+       int ret;
+
+       ret = _altera_pcie_cfg_read(pcie, busno, devfn,
+                                   PCIE_CAP_OFFSET + offset, sizeof(*value),
+                                   &data);
+       *value = data;
+       return ret;
+}
+
+static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
+                                unsigned int devfn, int offset, u16 value)
+{
+       return _altera_pcie_cfg_write(pcie, busno, devfn,
+                                     PCIE_CAP_OFFSET + offset, sizeof(value),
+                                     value);
+}
+
+static void altera_wait_link_retrain(struct altera_pcie *pcie)
+{
+       u16 reg16;
+       unsigned long start_jiffies;
+
+       /* Wait for link training end. */
+       start_jiffies = jiffies;
+       for (;;) {
+               altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
+                                    PCI_EXP_LNKSTA, &reg16);
+               if (!(reg16 & PCI_EXP_LNKSTA_LT))
+                       break;
+
+               if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
+                       dev_err(&pcie->pdev->dev, "link retrain timeout\n");
+                       break;
+               }
+               udelay(100);
+       }
+
+       /* Wait for link is up */
+       start_jiffies = jiffies;
+       for (;;) {
+               if (altera_pcie_link_is_up(pcie))
+                       break;
+
+               if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
+                       dev_err(&pcie->pdev->dev, "link up timeout\n");
+                       break;
+               }
+               udelay(100);
+       }
+}
+
+static void altera_pcie_retrain(struct altera_pcie *pcie)
+{
+       u16 linkcap, linkstat, linkctl;
+
+       if (!altera_pcie_link_is_up(pcie))
+               return;
+
+       /*
+        * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+        * current speed is 2.5 GB/s.
+        */
+       altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
+                            &linkcap);
+       if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
+               return;
+
+       altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
+                            &linkstat);
+       if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
+               altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
+                                    PCI_EXP_LNKCTL, &linkctl);
+               linkctl |= PCI_EXP_LNKCTL_RL;
+               altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
+                                     PCI_EXP_LNKCTL, linkctl);
+
+               altera_wait_link_retrain(pcie);
+       }
+}
+
 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
                                irq_hw_number_t hwirq)
 {
@@ -555,6 +580,11 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
        return 0;
 }
 
+static void altera_pcie_host_init(struct altera_pcie *pcie)
+{
+       altera_pcie_retrain(pcie);
+}
+
 static int altera_pcie_probe(struct platform_device *pdev)
 {
        struct altera_pcie *pcie;
@@ -592,6 +622,7 @@ static int altera_pcie_probe(struct platform_device *pdev)
        cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
        /* enable all interrupts */
        cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
+       altera_pcie_host_init(pcie);
 
        bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
                                pcie, &pcie->resources);