* Broadcom iProc PCIe controller with the platform bus interface
Required properties:
-- compatible: Must be "brcm,iproc-pcie"
+- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
+ for PAXC. PAXB-based root complex is used for external endpoint devices.
+ PAXC-based root complex is connected to emulated endpoint devices
+ internal to the ASIC
- reg: base address and length of the PCIe controller I/O register space
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map, standard PCI properties to define the
- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
increase the outbound window size
+MSI support (optional):
+
+For older platforms without MSI integrated in the GIC, iProc PCIe core provides
+an event queue based MSI support. The iProc MSI uses host memories to store
+MSI posted writes in the event queues
+
+- msi-parent: Link to the device node of the MSI controller. On newer iProc
+platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
+platforms without MSI support in its interrupt controller, one may use the
+event queue based MSI support integrated within the iProc PCIe core.
+
+When the iProc event queue based MSI is used, one needs to define the
+following properties in the MSI device node:
+- compatible: Must be "brcm,iproc-msi"
+- msi-controller: claims itself as an MSI controller
+- interrupt-parent: Link to its parent interrupt device
+- interrupts: List of interrupt IDs from its parent interrupt device
+
+Optional properties:
+- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
+require the interrupt enable registers to be set explicitly to enable MSI
+
Example:
pcie0: pcie@18012000 {
compatible = "brcm,iproc-pcie";
brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x00000000>;
brcm,pcie-ob-window-size = <256>;
+
+ msi-parent = <&msi0>;
+
+ /* iProc event queue based MSI */
+ msi0: msi@18012000 {
+ compatible = "brcm,iproc-msi";
+ msi-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
+ <GIC_SPI 97 IRQ_TYPE_NONE>,
+ <GIC_SPI 98 IRQ_TYPE_NONE>,
+ <GIC_SPI 99 IRQ_TYPE_NONE>,
+ };
};
pcie1: pcie@18013000 {
-HiSilicon PCIe host bridge DT description
+HiSilicon Hip05 and Hip06 PCIe host bridge DT description
HiSilicon PCIe host controller is based on Designware PCI core.
It shares common functions with PCIe Designware core driver and inherits
Additional properties are described here:
-Required properties:
-- compatible: Should contain "hisilicon,hip05-pcie".
+Required properties
+- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
- reg: Should contain rc_dbi, config registers location and length.
- reg-names: Must include the following entries:
"rc_dbi": controller configuration registers;
- status: Either "ok" or "disabled".
- dma-coherent: Present if DMA operations are coherent.
-Example:
+Hip05 Example (note that Hip06 is the same except compatible):
pcie@0xb0080000 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
Required properties:
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
"renesas,pci-r8a7791" for the R8A7791 SoC;
- "renesas,pci-r8a7794" for the R8A7794 SoC.
+ "renesas,pci-r8a7794" for the R8A7794 SoC;
+ "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
+
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
- reg: A list of physical regions to access the device: the first is
the operational registers for the OHCI/EHCI controllers and the
second is for the bridge configuration and control registers.
- interrupt-map-mask: standard property that helps to define the interrupt
mapping.
+Optional properties:
+- dma-ranges: a single range for the inbound memory region. If not supplied,
+ defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
+ allowed combinations of address and size.
+
Example SoC configuration:
pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7790";
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0x0 0xee090000 0x0 0xc00>,
<0x0 0xee080000 0x0 0x1100>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
interrupt-map-mask = <0xff00 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
--- /dev/null
+* Qualcomm PCI express root complex
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Value should contain
+ - "qcom,pcie-ipq8064" for ipq8064
+ - "qcom,pcie-apq8064" for apq8064
+ - "qcom,pcie-apq8084" for apq8084
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Register ranges as listed in the reg-names property
+
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must include the following entries
+ - "parf" Qualcomm specific registers
+ - "dbi" Designware PCIe registers
+ - "elbi" External local bus interface registers
+ - "config" PCIe configuration space
+
+- device_type:
+ Usage: required
+ Value type: <string>
+ Definition: Should be "pci". As specified in designware-pcie.txt
+
+- #address-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should be 3. As specified in designware-pcie.txt
+
+- #size-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should be 2. As specified in designware-pcie.txt
+
+- ranges:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: As specified in designware-pcie.txt
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: MSI interrupt
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "msi"
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should be 1. As specified in designware-pcie.txt
+
+- interrupt-map-mask:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: As specified in designware-pcie.txt
+
+- interrupt-map:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: As specified in designware-pcie.txt
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: List of phandle and clock specifier pairs as listed
+ in clock-names property
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "iface" Configuration AHB clock
+
+- clock-names:
+ Usage: required for ipq/apq8064
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "core" Clocks the pcie hw block
+ - "phy" Clocks the pcie PHY block
+- clock-names:
+ Usage: required for apq8084
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "aux" Auxiliary (AUX) clock
+ - "bus_master" Master AXI clock
+ - "bus_slave" Slave AXI clock
+- resets:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: List of phandle and reset specifier pairs as listed
+ in reset-names property
+
+- reset-names:
+ Usage: required for ipq/apq8064
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "axi" AXI reset
+ - "ahb" AHB reset
+ - "por" POR reset
+ - "pci" PCI reset
+ - "phy" PHY reset
+
+- reset-names:
+ Usage: required for apq8084
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "core" Core reset
+
+- power-domains:
+ Usage: required for apq8084
+ Value type: <prop-encoded-array>
+ Definition: A phandle and power domain specifier pair to the
+ power domain which is responsible for collapsing
+ and restoring power to the peripheral
+
+- vdda-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: A phandle to the core analog power supply
+
+- vdda_phy-supply:
+ Usage: required for ipq/apq8064
+ Value type: <phandle>
+ Definition: A phandle to the analog power supply for PHY
+
+- vdda_refclk-supply:
+ Usage: required for ipq/apq8064
+ Value type: <phandle>
+ Definition: A phandle to the analog power supply for IC which generates
+ reference clock
+
+- phys:
+ Usage: required for apq8084
+ Value type: <phandle>
+ Definition: List of phandle(s) as listed in phy-names property
+
+- phy-names:
+ Usage: required for apq8084
+ Value type: <stringlist>
+ Definition: Should contain "pciephy"
+
+- <name>-gpios:
+ Usage: optional
+ Value type: <prop-encoded-array>
+ Definition: List of phandle and gpio specifier pairs. Should contain
+ - "perst-gpios" PCIe endpoint reset signal line
+ - "wake-gpios" PCIe endpoint wake signal line
+
+* Example for ipq/apq8064
+ pcie@1b500000 {
+ compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
+ reg = <0x1b500000 0x1000
+ 0x1b502000 0x80
+ 0x1b600000 0x100
+ 0x0ff00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
+ 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
+ interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc PCIE_A_CLK>,
+ <&gcc PCIE_H_CLK>,
+ <&gcc PCIE_PHY_CLK>;
+ clock-names = "core", "iface", "phy";
+ resets = <&gcc PCIE_ACLK_RESET>,
+ <&gcc PCIE_HCLK_RESET>,
+ <&gcc PCIE_POR_RESET>,
+ <&gcc PCIE_PCI_RESET>,
+ <&gcc PCIE_PHY_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy";
+ pinctrl-0 = <&pcie_pins_default>;
+ pinctrl-names = "default";
+ };
+
+* Example for apq8084
+ pcie0@fc520000 {
+ compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
+ reg = <0xfc520000 0x2000>,
+ <0xff000000 0x1000>,
+ <0xff001000 0x1000>,
+ <0xff002000 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
+ 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
+ interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>;
+ clock-names = "iface", "master_bus", "slave_bus", "aux";
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE0_GDSC>;
+ vdda-supply = <&pma8084_l3>;
+ phys = <&pciephy0>;
+ phy-names = "pciephy";
+ perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie0_pins_default>;
+ pinctrl-names = "default";
+ };
* Renesas RCar PCIe interface
Required properties:
-- compatible: should contain one of the following
- "renesas,pcie-r8a7779", "renesas,pcie-r8a7790", "renesas,pcie-r8a7791"
+compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
+ "renesas,pcie-r8a7790" for the R8A7790 SoC;
+ "renesas,pcie-r8a7791" for the R8A7791 SoC;
+ "renesas,pcie-r8a7795" for the R8A7795 SoC;
+ "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
- reg: base address and length of the pcie controller registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
SoC specific DT Entry:
pcie: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7791";
+ compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
F: drivers/pci/host/pci-host-generic.c
+PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
+M: Keith Busch <keith.busch@intel.com>
+L: linux-pci@vger.kernel.org
+S: Supported
+F: arch/x86/pci/vmd.c
+
PCIE DRIVER FOR ST SPEAR13XX
M: Pratyush Anand <pratyush.anand@gmail.com>
L: linux-pci@vger.kernel.org
PCIE DRIVER FOR HISILICON
M: Zhou Wang <wangzhou1@hisilicon.com>
+M: Gabriele Paoloni <gabriele.paoloni@huawei.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
F: drivers/pci/host/pcie-hisi.c
+PCIE DRIVER FOR QUALCOMM MSM
+M: Stanimir Varbanov <svarbanov@mm-sol.com>
+L: linux-pci@vger.kernel.org
+L: linux-arm-msm@vger.kernel.org
+S: Maintained
+F: drivers/pci/host/*qcom*
+
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org
bias-disable;
};
};
+
+ pcie_pins: pcie_pinmux {
+ mux {
+ pins = "gpio27";
+ function = "gpio";
+ };
+ conf {
+ pins = "gpio27";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
};
rpm@108000 {
lvs1 {
bias-pull-down;
};
+
+ lvs6 {
+ bias-pull-down;
+ };
};
};
status = "okay";
};
+ pci@1b500000 {
+ status = "ok";
+ vdda-supply = <&pm8921_s3>;
+ vdda_phy-supply = <&pm8921_lvs6>;
+ vdda_refclk-supply = <&ext_3p3v>;
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+ perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ };
+
qcom,ssbi@500000 {
pmic@0 {
gpio@150 {
compatible = "qcom,tcsr-apq8064", "syscon";
reg = <0x1a400000 0x100>;
};
+
+ pcie: pci@1b500000 {
+ compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
+ reg = <0x1b500000 0x1000
+ 0x1b502000 0x80
+ 0x1b600000 0x100
+ 0x0ff00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
+ 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
+ interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc PCIE_A_CLK>,
+ <&gcc PCIE_H_CLK>,
+ <&gcc PCIE_PHY_REF_CLK>;
+ clock-names = "core", "iface", "phy";
+ resets = <&gcc PCIE_ACLK_RESET>,
+ <&gcc PCIE_HCLK_RESET>,
+ <&gcc PCIE_POR_RESET>,
+ <&gcc PCIE_PCI_RESET>,
+ <&gcc PCIE_PHY_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy";
+ status = "disabled";
+ };
};
};
* support EEH. So we just care about PCI devices for
* simplicity here.
*/
- if (!dev || (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE))
+ if (!dev || (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE))
return NULL;
/*
pci_device_add(dev, bus);
- /* Setup MSI caps & disable MSI/MSI-X interrupts */
- pci_msi_setup_pci_dev(dev);
-
return dev;
}
EXPORT_SYMBOL(of_create_pci_dev);
def_bool y
depends on PCI
+config VMD
+ depends on PCI_MSI
+ tristate "Volume Management Device Driver"
+ default N
+ ---help---
+ Adds support for the Intel Volume Management Device (VMD). VMD is a
+ secondary PCI host bridge that allows PCI Express root ports,
+ and devices attached to them, to be removed from the default
+ PCI domain and placed within the VMD domain. This provides
+ more bus resources than are otherwise possible with a
+ single domain. If you know your system provides one of these and
+ has devices attached to it, say Y; if you are not sure, say N.
+
source "net/Kconfig"
source "drivers/Kconfig"
#endif
};
+#if defined(CONFIG_X86_DEV_DMA_OPS) && defined(CONFIG_PCI_DOMAINS)
+struct dma_domain {
+ struct list_head node;
+ struct dma_map_ops *dma_ops;
+ int domain_nr;
+};
+void add_dma_domain(struct dma_domain *domain);
+void del_dma_domain(struct dma_domain *domain);
+#endif
+
struct pdev_archdata {
};
unsigned long uv_offset;
char *uv_name;
};
+#endif
+#if IS_ENABLED(CONFIG_VMD)
+ struct {
+ struct msi_desc *desc;
+ };
#endif
};
};
#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
/*
- * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
- * on their northbrige except through the * %eax register. As such, you MUST
- * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
- * accessor functions.
- * In fact just use pci_config_*, nothing else please.
+ * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
+ * %eax. No other source or target registers may be used. The following
+ * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's
+ * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
+ * "MMIO Configuration Coding Requirements".
*/
static inline unsigned char mmio_config_readb(void __iomem *pos)
{
obj-$(CONFIG_AMD_NB) += amd_bus.o
obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o
+obj-$(CONFIG_VMD) += vmd.o
+
ifeq ($(CONFIG_PCI_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}
+#if defined(CONFIG_X86_DEV_DMA_OPS) && defined(CONFIG_PCI_DOMAINS)
+static LIST_HEAD(dma_domain_list);
+static DEFINE_SPINLOCK(dma_domain_list_lock);
+
+void add_dma_domain(struct dma_domain *domain)
+{
+ spin_lock(&dma_domain_list_lock);
+ list_add(&domain->node, &dma_domain_list);
+ spin_unlock(&dma_domain_list_lock);
+}
+EXPORT_SYMBOL_GPL(add_dma_domain);
+
+void del_dma_domain(struct dma_domain *domain)
+{
+ spin_lock(&dma_domain_list_lock);
+ list_del(&domain->node);
+ spin_unlock(&dma_domain_list_lock);
+}
+EXPORT_SYMBOL_GPL(del_dma_domain);
+
+static void set_dma_domain_ops(struct pci_dev *pdev)
+{
+ struct dma_domain *domain;
+
+ spin_lock(&dma_domain_list_lock);
+ list_for_each_entry(domain, &dma_domain_list, node) {
+ if (pci_domain_nr(pdev->bus) == domain->domain_nr) {
+ pdev->dev.archdata.dma_ops = domain->dma_ops;
+ break;
+ }
+ }
+ spin_unlock(&dma_domain_list_lock);
+}
+#else
+static void set_dma_domain_ops(struct pci_dev *pdev) {}
+#endif
+
int pcibios_add_device(struct pci_dev *dev)
{
struct setup_data *data;
pa_data = data->next;
iounmap(data);
}
+ set_dma_domain_ops(dev);
return 0;
}
unsigned long result = 0;
unsigned long flags;
unsigned long bx = (bus << 8) | devfn;
+ u16 number = 0, mask = 0;
WARN_ON(seg);
if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
switch (len) {
case 1:
- __asm__("lcall *(%%esi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=c" (*value),
- "=a" (result)
- : "1" (PCIBIOS_READ_CONFIG_BYTE),
- "b" (bx),
- "D" ((long)reg),
- "S" (&pci_indirect));
- /*
- * Zero-extend the result beyond 8 bits, do not trust the
- * BIOS having done it:
- */
- *value &= 0xff;
+ number = PCIBIOS_READ_CONFIG_BYTE;
+ mask = 0xff;
break;
case 2:
- __asm__("lcall *(%%esi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=c" (*value),
- "=a" (result)
- : "1" (PCIBIOS_READ_CONFIG_WORD),
- "b" (bx),
- "D" ((long)reg),
- "S" (&pci_indirect));
- /*
- * Zero-extend the result beyond 16 bits, do not trust the
- * BIOS having done it:
- */
- *value &= 0xffff;
+ number = PCIBIOS_READ_CONFIG_WORD;
+ mask = 0xffff;
break;
case 4:
- __asm__("lcall *(%%esi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=c" (*value),
- "=a" (result)
- : "1" (PCIBIOS_READ_CONFIG_DWORD),
- "b" (bx),
- "D" ((long)reg),
- "S" (&pci_indirect));
+ number = PCIBIOS_READ_CONFIG_DWORD;
break;
}
+ __asm__("lcall *(%%esi); cld\n\t"
+ "jc 1f\n\t"
+ "xor %%ah, %%ah\n"
+ "1:"
+ : "=c" (*value),
+ "=a" (result)
+ : "1" (number),
+ "b" (bx),
+ "D" ((long)reg),
+ "S" (&pci_indirect));
+ /*
+ * Zero-extend the result beyond 8 or 16 bits, do not trust the
+ * BIOS having done it:
+ */
+ if (mask)
+ *value &= mask;
+
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
return (int)((result & 0xff00) >> 8);
unsigned long result = 0;
unsigned long flags;
unsigned long bx = (bus << 8) | devfn;
+ u16 number = 0;
WARN_ON(seg);
if ((bus > 255) || (devfn > 255) || (reg > 255))
switch (len) {
case 1:
- __asm__("lcall *(%%esi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=a" (result)
- : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
- "c" (value),
- "b" (bx),
- "D" ((long)reg),
- "S" (&pci_indirect));
+ number = PCIBIOS_WRITE_CONFIG_BYTE;
break;
case 2:
- __asm__("lcall *(%%esi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=a" (result)
- : "0" (PCIBIOS_WRITE_CONFIG_WORD),
- "c" (value),
- "b" (bx),
- "D" ((long)reg),
- "S" (&pci_indirect));
+ number = PCIBIOS_WRITE_CONFIG_WORD;
break;
case 4:
- __asm__("lcall *(%%esi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=a" (result)
- : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
- "c" (value),
- "b" (bx),
- "D" ((long)reg),
- "S" (&pci_indirect));
+ number = PCIBIOS_WRITE_CONFIG_DWORD;
break;
}
+ __asm__("lcall *(%%esi); cld\n\t"
+ "jc 1f\n\t"
+ "xor %%ah, %%ah\n"
+ "1:"
+ : "=a" (result)
+ : "0" (number),
+ "c" (value),
+ "b" (bx),
+ "D" ((long)reg),
+ "S" (&pci_indirect));
+
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
return (int)((result & 0xff00) >> 8);
--- /dev/null
+/*
+ * Volume Management Device driver
+ * Copyright (c) 2015, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/pci.h>
+#include <linux/rculist.h>
+#include <linux/rcupdate.h>
+
+#include <asm/irqdomain.h>
+#include <asm/device.h>
+#include <asm/msi.h>
+#include <asm/msidef.h>
+
+#define VMD_CFGBAR 0
+#define VMD_MEMBAR1 2
+#define VMD_MEMBAR2 4
+
+/*
+ * Lock for manipulating VMD IRQ lists.
+ */
+static DEFINE_RAW_SPINLOCK(list_lock);
+
+/**
+ * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
+ * @node: list item for parent traversal.
+ * @rcu: RCU callback item for freeing.
+ * @irq: back pointer to parent.
+ * @virq: the virtual IRQ value provided to the requesting driver.
+ *
+ * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
+ * a VMD IRQ using this structure.
+ */
+struct vmd_irq {
+ struct list_head node;
+ struct rcu_head rcu;
+ struct vmd_irq_list *irq;
+ unsigned int virq;
+};
+
+/**
+ * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
+ * @irq_list: the list of irq's the VMD one demuxes to.
+ * @vmd_vector: the h/w IRQ assigned to the VMD.
+ * @index: index into the VMD MSI-X table; used for message routing.
+ * @count: number of child IRQs assigned to this vector; used to track
+ * sharing.
+ */
+struct vmd_irq_list {
+ struct list_head irq_list;
+ struct vmd_dev *vmd;
+ unsigned int vmd_vector;
+ unsigned int index;
+ unsigned int count;
+};
+
+struct vmd_dev {
+ struct pci_dev *dev;
+
+ spinlock_t cfg_lock;
+ char __iomem *cfgbar;
+
+ int msix_count;
+ struct msix_entry *msix_entries;
+ struct vmd_irq_list *irqs;
+
+ struct pci_sysdata sysdata;
+ struct resource resources[3];
+ struct irq_domain *irq_domain;
+ struct pci_bus *bus;
+
+#ifdef CONFIG_X86_DEV_DMA_OPS
+ struct dma_map_ops dma_ops;
+ struct dma_domain dma_domain;
+#endif
+};
+
+static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
+{
+ return container_of(bus->sysdata, struct vmd_dev, sysdata);
+}
+
+/*
+ * Drivers managing a device in a VMD domain allocate their own IRQs as before,
+ * but the MSI entry for the hardware it's driving will be programmed with a
+ * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
+ * domain into one of its own, and the VMD driver de-muxes these for the
+ * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
+ * and irq_chip to set this up.
+ */
+static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+ struct vmd_irq *vmdirq = data->chip_data;
+ struct vmd_irq_list *irq = vmdirq->irq;
+
+ msg->address_hi = MSI_ADDR_BASE_HI;
+ msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_DEST_ID(irq->index);
+ msg->data = 0;
+}
+
+/*
+ * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops.
+ */
+static void vmd_irq_enable(struct irq_data *data)
+{
+ struct vmd_irq *vmdirq = data->chip_data;
+
+ raw_spin_lock(&list_lock);
+ list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
+ raw_spin_unlock(&list_lock);
+
+ data->chip->irq_unmask(data);
+}
+
+static void vmd_irq_disable(struct irq_data *data)
+{
+ struct vmd_irq *vmdirq = data->chip_data;
+
+ data->chip->irq_mask(data);
+
+ raw_spin_lock(&list_lock);
+ list_del_rcu(&vmdirq->node);
+ raw_spin_unlock(&list_lock);
+}
+
+/*
+ * XXX: Stubbed until we develop acceptable way to not create conflicts with
+ * other devices sharing the same vector.
+ */
+static int vmd_irq_set_affinity(struct irq_data *data,
+ const struct cpumask *dest, bool force)
+{
+ return -EINVAL;
+}
+
+static struct irq_chip vmd_msi_controller = {
+ .name = "VMD-MSI",
+ .irq_enable = vmd_irq_enable,
+ .irq_disable = vmd_irq_disable,
+ .irq_compose_msi_msg = vmd_compose_msi_msg,
+ .irq_set_affinity = vmd_irq_set_affinity,
+};
+
+static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
+ msi_alloc_info_t *arg)
+{
+ return 0;
+}
+
+/*
+ * XXX: We can be even smarter selecting the best IRQ once we solve the
+ * affinity problem.
+ */
+static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd)
+{
+ int i, best = 0;
+
+ raw_spin_lock(&list_lock);
+ for (i = 1; i < vmd->msix_count; i++)
+ if (vmd->irqs[i].count < vmd->irqs[best].count)
+ best = i;
+ vmd->irqs[best].count++;
+ raw_spin_unlock(&list_lock);
+
+ return &vmd->irqs[best];
+}
+
+static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
+ unsigned int virq, irq_hw_number_t hwirq,
+ msi_alloc_info_t *arg)
+{
+ struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(arg->desc)->bus);
+ struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
+
+ if (!vmdirq)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&vmdirq->node);
+ vmdirq->irq = vmd_next_irq(vmd);
+ vmdirq->virq = virq;
+
+ irq_domain_set_info(domain, virq, vmdirq->irq->vmd_vector, info->chip,
+ vmdirq, handle_simple_irq, vmd, NULL);
+ return 0;
+}
+
+static void vmd_msi_free(struct irq_domain *domain,
+ struct msi_domain_info *info, unsigned int virq)
+{
+ struct vmd_irq *vmdirq = irq_get_chip_data(virq);
+
+ /* XXX: Potential optimization to rebalance */
+ raw_spin_lock(&list_lock);
+ vmdirq->irq->count--;
+ raw_spin_unlock(&list_lock);
+
+ kfree_rcu(vmdirq, rcu);
+}
+
+static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev,
+ int nvec, msi_alloc_info_t *arg)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
+
+ if (nvec > vmd->msix_count)
+ return vmd->msix_count;
+
+ memset(arg, 0, sizeof(*arg));
+ return 0;
+}
+
+static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
+{
+ arg->desc = desc;
+}
+
+static struct msi_domain_ops vmd_msi_domain_ops = {
+ .get_hwirq = vmd_get_hwirq,
+ .msi_init = vmd_msi_init,
+ .msi_free = vmd_msi_free,
+ .msi_prepare = vmd_msi_prepare,
+ .set_desc = vmd_set_desc,
+};
+
+static struct msi_domain_info vmd_msi_domain_info = {
+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX,
+ .ops = &vmd_msi_domain_ops,
+ .chip = &vmd_msi_controller,
+};
+
+#ifdef CONFIG_X86_DEV_DMA_OPS
+/*
+ * VMD replaces the requester ID with its own. DMA mappings for devices in a
+ * VMD domain need to be mapped for the VMD, not the device requiring
+ * the mapping.
+ */
+static struct device *to_vmd_dev(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
+
+ return &vmd->dev->dev;
+}
+
+static struct dma_map_ops *vmd_dma_ops(struct device *dev)
+{
+ return to_vmd_dev(dev)->archdata.dma_ops;
+}
+
+static void *vmd_alloc(struct device *dev, size_t size, dma_addr_t *addr,
+ gfp_t flag, struct dma_attrs *attrs)
+{
+ return vmd_dma_ops(dev)->alloc(to_vmd_dev(dev), size, addr, flag,
+ attrs);
+}
+
+static void vmd_free(struct device *dev, size_t size, void *vaddr,
+ dma_addr_t addr, struct dma_attrs *attrs)
+{
+ return vmd_dma_ops(dev)->free(to_vmd_dev(dev), size, vaddr, addr,
+ attrs);
+}
+
+static int vmd_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t addr, size_t size,
+ struct dma_attrs *attrs)
+{
+ return vmd_dma_ops(dev)->mmap(to_vmd_dev(dev), vma, cpu_addr, addr,
+ size, attrs);
+}
+
+static int vmd_get_sgtable(struct device *dev, struct sg_table *sgt,
+ void *cpu_addr, dma_addr_t addr, size_t size,
+ struct dma_attrs *attrs)
+{
+ return vmd_dma_ops(dev)->get_sgtable(to_vmd_dev(dev), sgt, cpu_addr,
+ addr, size, attrs);
+}
+
+static dma_addr_t vmd_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction dir,
+ struct dma_attrs *attrs)
+{
+ return vmd_dma_ops(dev)->map_page(to_vmd_dev(dev), page, offset, size,
+ dir, attrs);
+}
+
+static void vmd_unmap_page(struct device *dev, dma_addr_t addr, size_t size,
+ enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+ vmd_dma_ops(dev)->unmap_page(to_vmd_dev(dev), addr, size, dir, attrs);
+}
+
+static int vmd_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+ enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+ return vmd_dma_ops(dev)->map_sg(to_vmd_dev(dev), sg, nents, dir, attrs);
+}
+
+static void vmd_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+ enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+ vmd_dma_ops(dev)->unmap_sg(to_vmd_dev(dev), sg, nents, dir, attrs);
+}
+
+static void vmd_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
+ size_t size, enum dma_data_direction dir)
+{
+ vmd_dma_ops(dev)->sync_single_for_cpu(to_vmd_dev(dev), addr, size, dir);
+}
+
+static void vmd_sync_single_for_device(struct device *dev, dma_addr_t addr,
+ size_t size, enum dma_data_direction dir)
+{
+ vmd_dma_ops(dev)->sync_single_for_device(to_vmd_dev(dev), addr, size,
+ dir);
+}
+
+static void vmd_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction dir)
+{
+ vmd_dma_ops(dev)->sync_sg_for_cpu(to_vmd_dev(dev), sg, nents, dir);
+}
+
+static void vmd_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction dir)
+{
+ vmd_dma_ops(dev)->sync_sg_for_device(to_vmd_dev(dev), sg, nents, dir);
+}
+
+static int vmd_mapping_error(struct device *dev, dma_addr_t addr)
+{
+ return vmd_dma_ops(dev)->mapping_error(to_vmd_dev(dev), addr);
+}
+
+static int vmd_dma_supported(struct device *dev, u64 mask)
+{
+ return vmd_dma_ops(dev)->dma_supported(to_vmd_dev(dev), mask);
+}
+
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+static u64 vmd_get_required_mask(struct device *dev)
+{
+ return vmd_dma_ops(dev)->get_required_mask(to_vmd_dev(dev));
+}
+#endif
+
+static void vmd_teardown_dma_ops(struct vmd_dev *vmd)
+{
+ struct dma_domain *domain = &vmd->dma_domain;
+
+ if (vmd->dev->dev.archdata.dma_ops)
+ del_dma_domain(domain);
+}
+
+#define ASSIGN_VMD_DMA_OPS(source, dest, fn) \
+ do { \
+ if (source->fn) \
+ dest->fn = vmd_##fn; \
+ } while (0)
+
+static void vmd_setup_dma_ops(struct vmd_dev *vmd)
+{
+ const struct dma_map_ops *source = vmd->dev->dev.archdata.dma_ops;
+ struct dma_map_ops *dest = &vmd->dma_ops;
+ struct dma_domain *domain = &vmd->dma_domain;
+
+ domain->domain_nr = vmd->sysdata.domain;
+ domain->dma_ops = dest;
+
+ if (!source)
+ return;
+ ASSIGN_VMD_DMA_OPS(source, dest, alloc);
+ ASSIGN_VMD_DMA_OPS(source, dest, free);
+ ASSIGN_VMD_DMA_OPS(source, dest, mmap);
+ ASSIGN_VMD_DMA_OPS(source, dest, get_sgtable);
+ ASSIGN_VMD_DMA_OPS(source, dest, map_page);
+ ASSIGN_VMD_DMA_OPS(source, dest, unmap_page);
+ ASSIGN_VMD_DMA_OPS(source, dest, map_sg);
+ ASSIGN_VMD_DMA_OPS(source, dest, unmap_sg);
+ ASSIGN_VMD_DMA_OPS(source, dest, sync_single_for_cpu);
+ ASSIGN_VMD_DMA_OPS(source, dest, sync_single_for_device);
+ ASSIGN_VMD_DMA_OPS(source, dest, sync_sg_for_cpu);
+ ASSIGN_VMD_DMA_OPS(source, dest, sync_sg_for_device);
+ ASSIGN_VMD_DMA_OPS(source, dest, mapping_error);
+ ASSIGN_VMD_DMA_OPS(source, dest, dma_supported);
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+ ASSIGN_VMD_DMA_OPS(source, dest, get_required_mask);
+#endif
+ add_dma_domain(domain);
+}
+#undef ASSIGN_VMD_DMA_OPS
+#else
+static void vmd_teardown_dma_ops(struct vmd_dev *vmd) {}
+static void vmd_setup_dma_ops(struct vmd_dev *vmd) {}
+#endif
+
+static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
+ unsigned int devfn, int reg, int len)
+{
+ char __iomem *addr = vmd->cfgbar +
+ (bus->number << 20) + (devfn << 12) + reg;
+
+ if ((addr - vmd->cfgbar) + len >=
+ resource_size(&vmd->dev->resource[VMD_CFGBAR]))
+ return NULL;
+
+ return addr;
+}
+
+/*
+ * CPU may deadlock if config space is not serialized on some versions of this
+ * hardware, so all config space access is done under a spinlock.
+ */
+static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
+ int len, u32 *value)
+{
+ struct vmd_dev *vmd = vmd_from_bus(bus);
+ char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
+ unsigned long flags;
+ int ret = 0;
+
+ if (!addr)
+ return -EFAULT;
+
+ spin_lock_irqsave(&vmd->cfg_lock, flags);
+ switch (len) {
+ case 1:
+ *value = readb(addr);
+ break;
+ case 2:
+ *value = readw(addr);
+ break;
+ case 4:
+ *value = readl(addr);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ spin_unlock_irqrestore(&vmd->cfg_lock, flags);
+ return ret;
+}
+
+/*
+ * VMD h/w converts non-posted config writes to posted memory writes. The
+ * read-back in this function forces the completion so it returns only after
+ * the config space was written, as expected.
+ */
+static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
+ int len, u32 value)
+{
+ struct vmd_dev *vmd = vmd_from_bus(bus);
+ char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
+ unsigned long flags;
+ int ret = 0;
+
+ if (!addr)
+ return -EFAULT;
+
+ spin_lock_irqsave(&vmd->cfg_lock, flags);
+ switch (len) {
+ case 1:
+ writeb(value, addr);
+ readb(addr);
+ break;
+ case 2:
+ writew(value, addr);
+ readw(addr);
+ break;
+ case 4:
+ writel(value, addr);
+ readl(addr);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ spin_unlock_irqrestore(&vmd->cfg_lock, flags);
+ return ret;
+}
+
+static struct pci_ops vmd_ops = {
+ .read = vmd_pci_read,
+ .write = vmd_pci_write,
+};
+
+/*
+ * VMD domains start at 0x1000 to not clash with ACPI _SEG domains.
+ */
+static int vmd_find_free_domain(void)
+{
+ int domain = 0xffff;
+ struct pci_bus *bus = NULL;
+
+ while ((bus = pci_find_next_bus(bus)) != NULL)
+ domain = max_t(int, domain, pci_domain_nr(bus));
+ return domain + 1;
+}
+
+static int vmd_enable_domain(struct vmd_dev *vmd)
+{
+ struct pci_sysdata *sd = &vmd->sysdata;
+ struct resource *res;
+ u32 upper_bits;
+ unsigned long flags;
+ LIST_HEAD(resources);
+
+ res = &vmd->dev->resource[VMD_CFGBAR];
+ vmd->resources[0] = (struct resource) {
+ .name = "VMD CFGBAR",
+ .start = res->start,
+ .end = (resource_size(res) >> 20) - 1,
+ .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
+ };
+
+ res = &vmd->dev->resource[VMD_MEMBAR1];
+ upper_bits = upper_32_bits(res->end);
+ flags = res->flags & ~IORESOURCE_SIZEALIGN;
+ if (!upper_bits)
+ flags &= ~IORESOURCE_MEM_64;
+ vmd->resources[1] = (struct resource) {
+ .name = "VMD MEMBAR1",
+ .start = res->start,
+ .end = res->end,
+ .flags = flags,
+ };
+
+ res = &vmd->dev->resource[VMD_MEMBAR2];
+ upper_bits = upper_32_bits(res->end);
+ flags = res->flags & ~IORESOURCE_SIZEALIGN;
+ if (!upper_bits)
+ flags &= ~IORESOURCE_MEM_64;
+ vmd->resources[2] = (struct resource) {
+ .name = "VMD MEMBAR2",
+ .start = res->start + 0x2000,
+ .end = res->end,
+ .flags = flags,
+ };
+
+ sd->domain = vmd_find_free_domain();
+ if (sd->domain < 0)
+ return sd->domain;
+
+ sd->node = pcibus_to_node(vmd->dev->bus);
+
+ vmd->irq_domain = pci_msi_create_irq_domain(NULL, &vmd_msi_domain_info,
+ NULL);
+ if (!vmd->irq_domain)
+ return -ENODEV;
+
+ pci_add_resource(&resources, &vmd->resources[0]);
+ pci_add_resource(&resources, &vmd->resources[1]);
+ pci_add_resource(&resources, &vmd->resources[2]);
+ vmd->bus = pci_create_root_bus(&vmd->dev->dev, 0, &vmd_ops, sd,
+ &resources);
+ if (!vmd->bus) {
+ pci_free_resource_list(&resources);
+ irq_domain_remove(vmd->irq_domain);
+ return -ENODEV;
+ }
+
+ vmd_setup_dma_ops(vmd);
+ dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
+ pci_rescan_bus(vmd->bus);
+
+ WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
+ "domain"), "Can't create symlink to domain\n");
+ return 0;
+}
+
+static irqreturn_t vmd_irq(int irq, void *data)
+{
+ struct vmd_irq_list *irqs = data;
+ struct vmd_irq *vmdirq;
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
+ generic_handle_irq(vmdirq->virq);
+ rcu_read_unlock();
+
+ return IRQ_HANDLED;
+}
+
+static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+ struct vmd_dev *vmd;
+ int i, err;
+
+ if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
+ return -ENOMEM;
+
+ vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
+ if (!vmd)
+ return -ENOMEM;
+
+ vmd->dev = dev;
+ err = pcim_enable_device(dev);
+ if (err < 0)
+ return err;
+
+ vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
+ if (!vmd->cfgbar)
+ return -ENOMEM;
+
+ pci_set_master(dev);
+ if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
+ dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)))
+ return -ENODEV;
+
+ vmd->msix_count = pci_msix_vec_count(dev);
+ if (vmd->msix_count < 0)
+ return -ENODEV;
+
+ vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
+ GFP_KERNEL);
+ if (!vmd->irqs)
+ return -ENOMEM;
+
+ vmd->msix_entries = devm_kcalloc(&dev->dev, vmd->msix_count,
+ sizeof(*vmd->msix_entries),
+ GFP_KERNEL);
+ if (!vmd->msix_entries)
+ return -ENOMEM;
+ for (i = 0; i < vmd->msix_count; i++)
+ vmd->msix_entries[i].entry = i;
+
+ vmd->msix_count = pci_enable_msix_range(vmd->dev, vmd->msix_entries, 1,
+ vmd->msix_count);
+ if (vmd->msix_count < 0)
+ return vmd->msix_count;
+
+ for (i = 0; i < vmd->msix_count; i++) {
+ INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
+ vmd->irqs[i].vmd_vector = vmd->msix_entries[i].vector;
+ vmd->irqs[i].index = i;
+
+ err = devm_request_irq(&dev->dev, vmd->irqs[i].vmd_vector,
+ vmd_irq, 0, "vmd", &vmd->irqs[i]);
+ if (err)
+ return err;
+ }
+
+ spin_lock_init(&vmd->cfg_lock);
+ pci_set_drvdata(dev, vmd);
+ err = vmd_enable_domain(vmd);
+ if (err)
+ return err;
+
+ dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
+ vmd->sysdata.domain);
+ return 0;
+}
+
+static void vmd_remove(struct pci_dev *dev)
+{
+ struct vmd_dev *vmd = pci_get_drvdata(dev);
+
+ pci_set_drvdata(dev, NULL);
+ sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
+ pci_stop_root_bus(vmd->bus);
+ pci_remove_root_bus(vmd->bus);
+ vmd_teardown_dma_ops(vmd);
+ irq_domain_remove(vmd->irq_domain);
+}
+
+#ifdef CONFIG_PM
+static int vmd_suspend(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+
+ pci_save_state(pdev);
+ return 0;
+}
+
+static int vmd_resume(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+
+ pci_restore_state(pdev);
+ return 0;
+}
+#endif
+static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
+
+static const struct pci_device_id vmd_ids[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x201d),},
+ {0,}
+};
+MODULE_DEVICE_TABLE(pci, vmd_ids);
+
+static struct pci_driver vmd_drv = {
+ .name = "vmd",
+ .id_table = vmd_ids,
+ .probe = vmd_probe,
+ .remove = vmd_remove,
+ .driver = {
+ .pm = &vmd_dev_pm_ops,
+ },
+};
+module_pci_driver(vmd_drv);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION("0.6");
#define PCI_word_BAD (pos & 1)
#define PCI_dword_BAD (pos & 3)
-#define PCI_OP_READ(size,type,len) \
+#define PCI_OP_READ(size, type, len) \
int pci_bus_read_config_##size \
(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
{ \
return res; \
}
-#define PCI_OP_WRITE(size,type,len) \
+#define PCI_OP_WRITE(size, type, len) \
int pci_bus_write_config_##size \
(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
{ \
}
/* Returns 0 on success, negative values indicate error. */
-#define PCI_USER_READ_CONFIG(size,type) \
+#define PCI_USER_READ_CONFIG(size, type) \
int pci_user_read_config_##size \
(struct pci_dev *dev, int pos, type *val) \
{ \
EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
/* Returns 0 on success, negative values indicate error. */
-#define PCI_USER_WRITE_CONFIG(size,type) \
+#define PCI_USER_WRITE_CONFIG(size, type) \
int pci_user_write_config_##size \
(struct pci_dev *dev, int pos, type val) \
{ \
type_mask |= IORESOURCE_TYPE_BITS;
pci_bus_for_each_resource(bus, r, i) {
+ resource_size_t min_used = min;
+
if (!r)
continue;
* overrides "min".
*/
if (avail.start)
- min = avail.start;
+ min_used = avail.start;
max = avail.end;
/* Ok, try it out.. */
- ret = allocate_resource(r, res, size, min, max,
+ ret = allocate_resource(r, res, size, min_used, max,
align, alignf, alignf_data);
if (ret == 0)
return 0;
config PCI_RCAR_GEN2_PCIE
bool "Renesas R-Car PCIe controller"
- depends on ARM
- depends on ARCH_SHMOBILE || COMPILE_TEST
+ depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
help
Say Y here if you want PCIe controller support on R-Car Gen2 SoCs.
depends on ARCH_VERSATILE
config PCIE_IPROC
- tristate "Broadcom iProc PCIe controller"
- depends on OF && (ARM || ARM64)
- default n
+ tristate
help
This enables the iProc PCIe core controller support for Broadcom's
- iProc family of SoCs. An appropriate bus interface driver also needs
- to be enabled
+ iProc family of SoCs. An appropriate bus interface driver needs
+ to be enabled to select this.
config PCIE_IPROC_PLATFORM
tristate "Broadcom iProc PCIe platform bus driver"
Say Y here if you want to use the Broadcom iProc PCIe controller
through the BCMA bus interface
+config PCIE_IPROC_MSI
+ bool "Broadcom iProc PCIe MSI support"
+ depends on PCIE_IPROC_PLATFORM || PCIE_IPROC_BCMA
+ depends on PCI_MSI
+ select PCI_MSI_IRQ_DOMAIN
+ default ARCH_BCM_IPROC
+ help
+ Say Y here if you want to enable MSI support for Broadcom's iProc
+ PCIe controller
+
config PCIE_ALTERA
bool "Altera PCIe controller"
depends on ARM || NIOS2
config PCI_HISI
depends on OF && ARM64
- bool "HiSilicon SoC HIP05 PCIe controller"
+ bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
select PCIEPORTBUS
select PCIE_DW
help
- Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
+ Say Y here if you want PCIe controller support on HiSilicon
+ Hip05 and Hip06 SoCs
+
+config PCIE_QCOM
+ bool "Qualcomm PCIe controller"
+ depends on ARCH_QCOM && OF
+ select PCIE_DW
+ select PCIEPORTBUS
+ help
+ Say Y here to enable PCIe controller support on Qualcomm SoCs. The
+ PCIe controller uses the Designware core plus Qualcomm-specific
+ hardware wrappers.
endmenu
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
+obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
}
ret = devm_request_irq(&pdev->dev, pp->irq,
- dra7xx_pcie_msi_irq_handler, IRQF_SHARED,
+ dra7xx_pcie_msi_irq_handler,
+ IRQF_SHARED | IRQF_NO_THREAD,
"dra7-pcie-msi", pp);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
ret = devm_request_irq(&pdev->dev, pp->msi_irq,
exynos_pcie_msi_irq_handler,
- IRQF_SHARED, "exynos-pcie", pp);
+ IRQF_SHARED | IRQF_NO_THREAD,
+ "exynos-pcie", pp);
if (ret) {
dev_err(&pdev->dev, "failed to request msi irq\n");
return ret;
struct gen_pci_cfg_bus_ops *ops;
};
-/*
- * ARM pcibios functions expect the ARM struct pci_sys_data as the PCI
- * sysdata. Add pci_sys_data as the first element in struct gen_pci so
- * that when we use a gen_pci pointer as sysdata, it is also a pointer to
- * a struct pci_sys_data.
- */
struct gen_pci {
-#ifdef CONFIG_ARM
- struct pci_sys_data sys;
-#endif
struct pci_host_bridge host;
struct gen_pci_cfg_windows cfg;
struct list_head resources;
#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
struct imx6_pcie {
- int reset_gpio;
+ struct gpio_desc *reset_gpio;
struct clk *pcie_bus;
struct clk *pcie_phy;
struct clk *pcie;
}
/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
-static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
+static int pcie_phy_read(void __iomem *dbi_base, int addr, int *data)
{
u32 val, phy_ctl;
int ret;
usleep_range(200, 500);
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- gpio_set_value(imx6_pcie->reset_gpio, 0);
+ if (imx6_pcie->reset_gpio) {
+ gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0);
msleep(100);
- gpio_set_value(imx6_pcie->reset_gpio, 1);
+ gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
}
return 0;
ret = devm_request_irq(&pdev->dev, pp->msi_irq,
imx6_pcie_msi_handler,
- IRQF_SHARED, "mx6-pcie-msi", pp);
+ IRQF_SHARED | IRQF_NO_THREAD,
+ "mx6-pcie-msi", pp);
if (ret) {
dev_err(&pdev->dev, "failed to request MSI irq\n");
return ret;
{
struct imx6_pcie *imx6_pcie;
struct pcie_port *pp;
- struct device_node *np = pdev->dev.of_node;
struct resource *dbi_base;
int ret;
return PTR_ERR(pp->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
- GPIOF_OUT_INIT_LOW, "PCIe reset");
- if (ret) {
- dev_err(&pdev->dev, "unable to get reset gpio\n");
- return ret;
- }
- }
+ imx6_pcie->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
+ GPIOD_OUT_LOW);
/* Fetch clocks */
imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
unsigned busnr;
int irq;
unsigned long window_size;
+ unsigned long window_addr;
+ unsigned long window_pci;
};
/* PCI configuration space operations */
RCAR_PCI_ARBITER_PCIBP_MODE;
iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
- /* PCI-AHB mapping: 0x40000000 base */
- iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
+ /* PCI-AHB mapping */
+ iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
reg + RCAR_PCIAHB_WIN1_CTR_REG);
/* AHB-PCI mapping: OHCI/EHCI registers */
iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
reg + RCAR_AHBPCI_WIN1_CTR_REG);
/* Set PCI-AHB Window1 address */
- iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
+ iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
reg + PCI_BASE_ADDRESS_1);
/* Set AHB-PCI bridge PCI communication area address */
val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
.write = pci_generic_config_write,
};
+static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+ struct device_node *node)
+{
+ const int na = 3, ns = 2;
+ int rlen;
+
+ parser->node = node;
+ parser->pna = of_n_addr_cells(node);
+ parser->np = parser->pna + na + ns;
+
+ parser->range = of_get_property(node, "dma-ranges", &rlen);
+ if (!parser->range)
+ return -ENOENT;
+
+ parser->end = parser->range + rlen / sizeof(__be32);
+ return 0;
+}
+
+static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
+ struct device_node *np)
+{
+ struct of_pci_range range;
+ struct of_pci_range_parser parser;
+ int index = 0;
+
+ /* Failure to parse is ok as we fall back to defaults */
+ if (pci_dma_range_parser_init(&parser, np))
+ return 0;
+
+ /* Get the dma-ranges from DT */
+ for_each_of_pci_range(&parser, &range) {
+ /* Hardware only allows one inbound 32-bit range */
+ if (index)
+ return -EINVAL;
+
+ pci->window_addr = (unsigned long)range.cpu_addr;
+ pci->window_pci = (unsigned long)range.pci_addr;
+ pci->window_size = (unsigned long)range.size;
+
+ /* Catch HW limitations */
+ if (!(range.flags & IORESOURCE_PREFETCH)) {
+ dev_err(pci->dev, "window must be prefetchable\n");
+ return -EINVAL;
+ }
+ if (pci->window_addr) {
+ u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
+
+ if (lowaddr < pci->window_size) {
+ dev_err(pci->dev, "invalid window size/addr\n");
+ return -EINVAL;
+ }
+ }
+ index++;
+ }
+
+ return 0;
+}
+
static int rcar_pci_probe(struct platform_device *pdev)
{
struct resource *cfg_res, *mem_res;
return priv->irq;
}
+ /* default window addr and size if not specified in DT */
+ priv->window_addr = 0x40000000;
+ priv->window_pci = 0x40000000;
priv->window_size = SZ_1G;
if (pdev->dev.of_node) {
priv->busnr = busnr.start;
if (busnr.end != busnr.start)
dev_warn(&pdev->dev, "only one bus number supported\n");
+
+ ret = rcar_pci_parse_map_dma_ranges(priv, pdev->dev.of_node);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse dma-range\n");
+ return ret;
+ }
} else {
priv->busnr = pdev->id;
}
}
static struct of_device_id rcar_pci_of_match[] = {
+ { .compatible = "renesas,pci-rcar-gen2", },
{ .compatible = "renesas,pci-r8a7790", },
{ .compatible = "renesas,pci-r8a7791", },
{ .compatible = "renesas,pci-r8a7794", },
msi->irq = err;
- err = request_irq(msi->irq, tegra_pcie_msi_irq, 0,
+ err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
tegra_msi_irq_chip.name, pcie);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
return err;
}
-/* Unused, temporary to satisfy ARM arch code */
-struct pci_sys_data sys;
-
static int versatile_pci_probe(struct platform_device *pdev)
{
struct resource *res;
pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);
- bus = pci_scan_root_bus(&pdev->dev, 0, &pci_versatile_ops, &sys, &pci_res);
+ bus = pci_scan_root_bus(&pdev->dev, 0, &pci_versatile_ops, NULL, &pci_res);
if (!bus)
return -ENOMEM;
static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
- int ret;
-
if (pp->ops->rd_own_conf)
- ret = pp->ops->rd_own_conf(pp, where, size, val);
- else
- ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+ return pp->ops->rd_own_conf(pp, where, size, val);
- return ret;
+ return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
}
static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
u32 val)
{
- int ret;
-
if (pp->ops->wr_own_conf)
- ret = pp->ops->wr_own_conf(pp, where, size, val);
- else
- ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
+ return pp->ops->wr_own_conf(pp, where, size, val);
- return ret;
+ return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
}
static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
int type, u64 cpu_addr, u64 pci_addr, u32 size)
{
+ u32 val;
+
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+
+ /*
+ * Make sure ATU enable takes effect before any subsequent config
+ * and I/O accesses.
+ */
+ dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
}
static struct irq_chip dw_msi_irq_chip = {
{
if (pp->ops->link_up)
return pp->ops->link_up(pp);
- else
- return 0;
+
+ return 0;
}
static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
u64 cpu_addr;
void __iomem *va_cfg_base;
+ if (pp->ops->rd_other_conf)
+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
u64 cpu_addr;
void __iomem *va_cfg_base;
+ if (pp->ops->wr_other_conf)
+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
int size, u32 *val)
{
struct pcie_port *pp = bus->sysdata;
- int ret;
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
- if (bus->number != pp->root_bus_nr)
- if (pp->ops->rd_other_conf)
- ret = pp->ops->rd_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_rd_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_rd_own_conf(pp, where, size, val);
+ if (bus->number == pp->root_bus_nr)
+ return dw_pcie_rd_own_conf(pp, where, size, val);
- return ret;
+ return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
}
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
struct pcie_port *pp = bus->sysdata;
- int ret;
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
- if (bus->number != pp->root_bus_nr)
- if (pp->ops->wr_other_conf)
- ret = pp->ops->wr_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_wr_other_conf(pp, bus, devfn,
- where, size, val);
- else
- ret = dw_pcie_wr_own_conf(pp, where, size, val);
+ if (bus->number == pp->root_bus_nr)
+ return dw_pcie_wr_own_conf(pp, where, size, val);
- return ret;
+ return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
}
static struct pci_ops dw_pcie_ops = {
/*
- * PCIe host controller driver for HiSilicon Hip05 SoC
+ * PCIe host controller driver for HiSilicon SoCs
*
* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
*
- * Author: Zhou Wang <wangzhou1@hisilicon.com>
- * Dacai Zhu <zhudacai@hisilicon.com>
+ * Authors: Zhou Wang <wangzhou1@hisilicon.com>
+ * Dacai Zhu <zhudacai@hisilicon.com>
+ * Gabriele Paoloni <gabriele.paoloni@huawei.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/platform_device.h>
+#include <linux/of_device.h>
#include <linux/regmap.h>
#include "pcie-designware.h"
-#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
-#define PCIE_LTSSM_LINKUP_STATE 0x11
-#define PCIE_LTSSM_STATE_MASK 0x3F
+#define PCIE_LTSSM_LINKUP_STATE 0x11
+#define PCIE_LTSSM_STATE_MASK 0x3F
+#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
+#define PCIE_SYS_STATE4 0x31c
+#define PCIE_HIP06_CTRL_OFF 0x1000
#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
+struct hisi_pcie;
+
+struct pcie_soc_ops {
+ int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
+};
+
struct hisi_pcie {
struct regmap *subctrl;
void __iomem *reg_base;
u32 port_id;
struct pcie_port pp;
+ struct pcie_soc_ops *soc_ops;
};
static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
return readl(pcie->reg_base + reg);
}
-/* Hip05 PCIe host only supports 32-bit config access */
+/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
u32 *val)
{
return PCIBIOS_SUCCESSFUL;
}
-/* Hip05 PCIe host only supports 32-bit config access */
+/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
u32 val)
{
return PCIBIOS_SUCCESSFUL;
}
-static int hisi_pcie_link_up(struct pcie_port *pp)
+static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
{
u32 val;
- struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
0x100 * hisi_pcie->port_id, &val);
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}
+static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
+{
+ u32 val;
+
+ val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF +
+ PCIE_SYS_STATE4);
+
+ return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
+static int hisi_pcie_link_up(struct pcie_port *pp)
+{
+ struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
+
+ return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
+}
+
static struct pcie_host_ops hisi_pcie_host_ops = {
.rd_own_conf = hisi_pcie_cfg_read,
.wr_own_conf = hisi_pcie_cfg_write,
{
struct hisi_pcie *hisi_pcie;
struct pcie_port *pp;
+ const struct of_device_id *match;
struct resource *reg;
+ struct device_driver *driver;
int ret;
hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL);
pp = &hisi_pcie->pp;
pp->dev = &pdev->dev;
+ driver = (pdev->dev).driver;
+
+ match = of_match_device(driver->of_match_table, &pdev->dev);
+ hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
hisi_pcie->subctrl =
syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
return 0;
}
+static struct pcie_soc_ops hip05_ops = {
+ &hisi_pcie_link_up_hip05
+};
+
+static struct pcie_soc_ops hip06_ops = {
+ &hisi_pcie_link_up_hip06
+};
+
static const struct of_device_id hisi_pcie_of_match[] = {
- {.compatible = "hisilicon,hip05-pcie",},
+ {
+ .compatible = "hisilicon,hip05-pcie",
+ .data = (void *) &hip05_ops,
+ },
+ {
+ .compatible = "hisilicon,hip06-pcie",
+ .data = (void *) &hip06_ops,
+ },
{},
};
+
MODULE_DEVICE_TABLE(of, hisi_pcie_of_match);
static struct platform_driver hisi_pcie_driver = {
};
module_platform_driver(hisi_pcie_driver);
+
+MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
+MODULE_AUTHOR("Dacai Zhu <zhudacai@hisilicon.com>");
+MODULE_AUTHOR("Gabriele Paoloni <gabriele.paoloni@huawei.com>");
+MODULE_LICENSE("GPL v2");
bcma_set_drvdata(bdev, pcie);
pcie->base = bdev->io_addr;
+ pcie->base_addr = bdev->addr;
res_mem.start = bdev->addr_s[0];
res_mem.end = bdev->addr_s[0] + SZ_128M - 1;
--- /dev/null
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/msi.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+
+#include "pcie-iproc.h"
+
+#define IPROC_MSI_INTR_EN_SHIFT 11
+#define IPROC_MSI_INTR_EN BIT(IPROC_MSI_INTR_EN_SHIFT)
+#define IPROC_MSI_INT_N_EVENT_SHIFT 1
+#define IPROC_MSI_INT_N_EVENT BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
+#define IPROC_MSI_EQ_EN_SHIFT 0
+#define IPROC_MSI_EQ_EN BIT(IPROC_MSI_EQ_EN_SHIFT)
+
+#define IPROC_MSI_EQ_MASK 0x3f
+
+/* Max number of GIC interrupts */
+#define NR_HW_IRQS 6
+
+/* Number of entries in each event queue */
+#define EQ_LEN 64
+
+/* Size of each event queue memory region */
+#define EQ_MEM_REGION_SIZE SZ_4K
+
+/* Size of each MSI address region */
+#define MSI_MEM_REGION_SIZE SZ_4K
+
+enum iproc_msi_reg {
+ IPROC_MSI_EQ_PAGE = 0,
+ IPROC_MSI_EQ_PAGE_UPPER,
+ IPROC_MSI_PAGE,
+ IPROC_MSI_PAGE_UPPER,
+ IPROC_MSI_CTRL,
+ IPROC_MSI_EQ_HEAD,
+ IPROC_MSI_EQ_TAIL,
+ IPROC_MSI_INTS_EN,
+ IPROC_MSI_REG_SIZE,
+};
+
+struct iproc_msi;
+
+/**
+ * iProc MSI group
+ *
+ * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
+ * event queue.
+ *
+ * @msi: pointer to iProc MSI data
+ * @gic_irq: GIC interrupt
+ * @eq: Event queue number
+ */
+struct iproc_msi_grp {
+ struct iproc_msi *msi;
+ int gic_irq;
+ unsigned int eq;
+};
+
+/**
+ * iProc event queue based MSI
+ *
+ * Only meant to be used on platforms without MSI support integrated into the
+ * GIC.
+ *
+ * @pcie: pointer to iProc PCIe data
+ * @reg_offsets: MSI register offsets
+ * @grps: MSI groups
+ * @nr_irqs: number of total interrupts connected to GIC
+ * @nr_cpus: number of toal CPUs
+ * @has_inten_reg: indicates the MSI interrupt enable register needs to be
+ * set explicitly (required for some legacy platforms)
+ * @bitmap: MSI vector bitmap
+ * @bitmap_lock: lock to protect access to the MSI bitmap
+ * @nr_msi_vecs: total number of MSI vectors
+ * @inner_domain: inner IRQ domain
+ * @msi_domain: MSI IRQ domain
+ * @nr_eq_region: required number of 4K aligned memory region for MSI event
+ * queues
+ * @nr_msi_region: required number of 4K aligned address region for MSI posted
+ * writes
+ * @eq_cpu: pointer to allocated memory region for MSI event queues
+ * @eq_dma: DMA address of MSI event queues
+ * @msi_addr: MSI address
+ */
+struct iproc_msi {
+ struct iproc_pcie *pcie;
+ const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
+ struct iproc_msi_grp *grps;
+ int nr_irqs;
+ int nr_cpus;
+ bool has_inten_reg;
+ unsigned long *bitmap;
+ struct mutex bitmap_lock;
+ unsigned int nr_msi_vecs;
+ struct irq_domain *inner_domain;
+ struct irq_domain *msi_domain;
+ unsigned int nr_eq_region;
+ unsigned int nr_msi_region;
+ void *eq_cpu;
+ dma_addr_t eq_dma;
+ phys_addr_t msi_addr;
+};
+
+static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
+};
+
+static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
+ { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
+ { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
+ { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
+ { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
+};
+
+static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
+ enum iproc_msi_reg reg,
+ unsigned int eq)
+{
+ struct iproc_pcie *pcie = msi->pcie;
+
+ return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
+}
+
+static inline void iproc_msi_write_reg(struct iproc_msi *msi,
+ enum iproc_msi_reg reg,
+ int eq, u32 val)
+{
+ struct iproc_pcie *pcie = msi->pcie;
+
+ writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
+}
+
+static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
+{
+ return (hwirq % msi->nr_irqs);
+}
+
+static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
+ unsigned long hwirq)
+{
+ if (msi->nr_msi_region > 1)
+ return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
+ else
+ return hwirq_to_group(msi, hwirq) * sizeof(u32);
+}
+
+static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
+{
+ if (msi->nr_eq_region > 1)
+ return eq * EQ_MEM_REGION_SIZE;
+ else
+ return eq * EQ_LEN * sizeof(u32);
+}
+
+static struct irq_chip iproc_msi_irq_chip = {
+ .name = "iProc-MSI",
+};
+
+static struct msi_domain_info iproc_msi_domain_info = {
+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX,
+ .chip = &iproc_msi_irq_chip,
+};
+
+/*
+ * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
+ * dedicated event queue. Each MSI group can support up to 64 MSI vectors.
+ *
+ * The number of MSI groups varies between different iProc SoCs. The total
+ * number of CPU cores also varies. To support MSI IRQ affinity, we
+ * distribute GIC interrupts across all available CPUs. MSI vector is moved
+ * from one GIC interrupt to another to steer to the target CPU.
+ *
+ * Assuming:
+ * - the number of MSI groups is M
+ * - the number of CPU cores is N
+ * - M is always a multiple of N
+ *
+ * Total number of raw MSI vectors = M * 64
+ * Total number of supported MSI vectors = (M * 64) / N
+ */
+static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
+{
+ return (hwirq % msi->nr_cpus);
+}
+
+static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
+ unsigned long hwirq)
+{
+ return (hwirq - hwirq_to_cpu(msi, hwirq));
+}
+
+static int iproc_msi_irq_set_affinity(struct irq_data *data,
+ const struct cpumask *mask, bool force)
+{
+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
+ int target_cpu = cpumask_first(mask);
+ int curr_cpu;
+
+ curr_cpu = hwirq_to_cpu(msi, data->hwirq);
+ if (curr_cpu == target_cpu)
+ return IRQ_SET_MASK_OK_DONE;
+
+ /* steer MSI to the target CPU */
+ data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
+
+ return IRQ_SET_MASK_OK;
+}
+
+static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
+ struct msi_msg *msg)
+{
+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
+ dma_addr_t addr;
+
+ addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
+ msg->address_lo = lower_32_bits(addr);
+ msg->address_hi = upper_32_bits(addr);
+ msg->data = data->hwirq;
+}
+
+static struct irq_chip iproc_msi_bottom_irq_chip = {
+ .name = "MSI",
+ .irq_set_affinity = iproc_msi_irq_set_affinity,
+ .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
+};
+
+static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs,
+ void *args)
+{
+ struct iproc_msi *msi = domain->host_data;
+ int hwirq;
+
+ mutex_lock(&msi->bitmap_lock);
+
+ /* Allocate 'nr_cpus' number of MSI vectors each time */
+ hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
+ msi->nr_cpus, 0);
+ if (hwirq < msi->nr_msi_vecs) {
+ bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
+ } else {
+ mutex_unlock(&msi->bitmap_lock);
+ return -ENOSPC;
+ }
+
+ mutex_unlock(&msi->bitmap_lock);
+
+ irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
+ domain->host_data, handle_simple_irq, NULL, NULL);
+
+ return 0;
+}
+
+static void iproc_msi_irq_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct irq_data *data = irq_domain_get_irq_data(domain, virq);
+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
+ unsigned int hwirq;
+
+ mutex_lock(&msi->bitmap_lock);
+
+ hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
+ bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
+
+ mutex_unlock(&msi->bitmap_lock);
+
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+}
+
+static const struct irq_domain_ops msi_domain_ops = {
+ .alloc = iproc_msi_irq_domain_alloc,
+ .free = iproc_msi_irq_domain_free,
+};
+
+static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
+{
+ u32 *msg, hwirq;
+ unsigned int offs;
+
+ offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
+ msg = (u32 *)(msi->eq_cpu + offs);
+ hwirq = *msg & IPROC_MSI_EQ_MASK;
+
+ /*
+ * Since we have multiple hwirq mapped to a single MSI vector,
+ * now we need to derive the hwirq at CPU0. It can then be used to
+ * mapped back to virq.
+ */
+ return hwirq_to_canonical_hwirq(msi, hwirq);
+}
+
+static void iproc_msi_handler(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct iproc_msi_grp *grp;
+ struct iproc_msi *msi;
+ struct iproc_pcie *pcie;
+ u32 eq, head, tail, nr_events;
+ unsigned long hwirq;
+ int virq;
+
+ chained_irq_enter(chip, desc);
+
+ grp = irq_desc_get_handler_data(desc);
+ msi = grp->msi;
+ pcie = msi->pcie;
+ eq = grp->eq;
+
+ /*
+ * iProc MSI event queue is tracked by head and tail pointers. Head
+ * pointer indicates the next entry (MSI data) to be consumed by SW in
+ * the queue and needs to be updated by SW. iProc MSI core uses the
+ * tail pointer as the next data insertion point.
+ *
+ * Entries between head and tail pointers contain valid MSI data. MSI
+ * data is guaranteed to be in the event queue memory before the tail
+ * pointer is updated by the iProc MSI core.
+ */
+ head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
+ eq) & IPROC_MSI_EQ_MASK;
+ do {
+ tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
+ eq) & IPROC_MSI_EQ_MASK;
+
+ /*
+ * Figure out total number of events (MSI data) to be
+ * processed.
+ */
+ nr_events = (tail < head) ?
+ (EQ_LEN - (head - tail)) : (tail - head);
+ if (!nr_events)
+ break;
+
+ /* process all outstanding events */
+ while (nr_events--) {
+ hwirq = decode_msi_hwirq(msi, eq, head);
+ virq = irq_find_mapping(msi->inner_domain, hwirq);
+ generic_handle_irq(virq);
+
+ head++;
+ head %= EQ_LEN;
+ }
+
+ /*
+ * Now all outstanding events have been processed. Update the
+ * head pointer.
+ */
+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
+
+ /*
+ * Now go read the tail pointer again to see if there are new
+ * oustanding events that came in during the above window.
+ */
+ } while (true);
+
+ chained_irq_exit(chip, desc);
+}
+
+static void iproc_msi_enable(struct iproc_msi *msi)
+{
+ int i, eq;
+ u32 val;
+
+ /* Program memory region for each event queue */
+ for (i = 0; i < msi->nr_eq_region; i++) {
+ dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
+
+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
+ lower_32_bits(addr));
+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
+ upper_32_bits(addr));
+ }
+
+ /* Program address region for MSI posted writes */
+ for (i = 0; i < msi->nr_msi_region; i++) {
+ phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
+
+ iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
+ lower_32_bits(addr));
+ iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
+ upper_32_bits(addr));
+ }
+
+ for (eq = 0; eq < msi->nr_irqs; eq++) {
+ /* Enable MSI event queue */
+ val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
+ IPROC_MSI_EQ_EN;
+ iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
+
+ /*
+ * Some legacy platforms require the MSI interrupt enable
+ * register to be set explicitly.
+ */
+ if (msi->has_inten_reg) {
+ val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
+ val |= BIT(eq);
+ iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
+ }
+ }
+}
+
+static void iproc_msi_disable(struct iproc_msi *msi)
+{
+ u32 eq, val;
+
+ for (eq = 0; eq < msi->nr_irqs; eq++) {
+ if (msi->has_inten_reg) {
+ val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
+ val &= ~BIT(eq);
+ iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
+ }
+
+ val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
+ val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
+ IPROC_MSI_EQ_EN);
+ iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
+ }
+}
+
+static int iproc_msi_alloc_domains(struct device_node *node,
+ struct iproc_msi *msi)
+{
+ msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
+ &msi_domain_ops, msi);
+ if (!msi->inner_domain)
+ return -ENOMEM;
+
+ msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+ &iproc_msi_domain_info,
+ msi->inner_domain);
+ if (!msi->msi_domain) {
+ irq_domain_remove(msi->inner_domain);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static void iproc_msi_free_domains(struct iproc_msi *msi)
+{
+ if (msi->msi_domain)
+ irq_domain_remove(msi->msi_domain);
+
+ if (msi->inner_domain)
+ irq_domain_remove(msi->inner_domain);
+}
+
+static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
+{
+ int i;
+
+ for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
+ irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
+ NULL, NULL);
+ }
+}
+
+static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
+{
+ int i, ret;
+ cpumask_var_t mask;
+ struct iproc_pcie *pcie = msi->pcie;
+
+ for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
+ irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
+ iproc_msi_handler,
+ &msi->grps[i]);
+ /* Dedicate GIC interrupt to each CPU core */
+ if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
+ cpumask_clear(mask);
+ cpumask_set_cpu(cpu, mask);
+ ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
+ if (ret)
+ dev_err(pcie->dev,
+ "failed to set affinity for IRQ%d\n",
+ msi->grps[i].gic_irq);
+ free_cpumask_var(mask);
+ } else {
+ dev_err(pcie->dev, "failed to alloc CPU mask\n");
+ ret = -EINVAL;
+ }
+
+ if (ret) {
+ /* Free all configured/unconfigured IRQs */
+ iproc_msi_irq_free(msi, cpu);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
+{
+ struct iproc_msi *msi;
+ int i, ret;
+ unsigned int cpu;
+
+ if (!of_device_is_compatible(node, "brcm,iproc-msi"))
+ return -ENODEV;
+
+ if (!of_find_property(node, "msi-controller", NULL))
+ return -ENODEV;
+
+ if (pcie->msi)
+ return -EBUSY;
+
+ msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
+ if (!msi)
+ return -ENOMEM;
+
+ msi->pcie = pcie;
+ pcie->msi = msi;
+ msi->msi_addr = pcie->base_addr;
+ mutex_init(&msi->bitmap_lock);
+ msi->nr_cpus = num_possible_cpus();
+
+ msi->nr_irqs = of_irq_count(node);
+ if (!msi->nr_irqs) {
+ dev_err(pcie->dev, "found no MSI GIC interrupt\n");
+ return -ENODEV;
+ }
+
+ if (msi->nr_irqs > NR_HW_IRQS) {
+ dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
+ msi->nr_irqs);
+ msi->nr_irqs = NR_HW_IRQS;
+ }
+
+ if (msi->nr_irqs < msi->nr_cpus) {
+ dev_err(pcie->dev,
+ "not enough GIC interrupts for MSI affinity\n");
+ return -EINVAL;
+ }
+
+ if (msi->nr_irqs % msi->nr_cpus != 0) {
+ msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
+ dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
+ msi->nr_irqs);
+ }
+
+ switch (pcie->type) {
+ case IPROC_PCIE_PAXB:
+ msi->reg_offsets = iproc_msi_reg_paxb;
+ msi->nr_eq_region = 1;
+ msi->nr_msi_region = 1;
+ break;
+ case IPROC_PCIE_PAXC:
+ msi->reg_offsets = iproc_msi_reg_paxc;
+ msi->nr_eq_region = msi->nr_irqs;
+ msi->nr_msi_region = msi->nr_irqs;
+ break;
+ default:
+ dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
+ return -EINVAL;
+ }
+
+ if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
+ msi->has_inten_reg = true;
+
+ msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
+ msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
+ sizeof(*msi->bitmap), GFP_KERNEL);
+ if (!msi->bitmap)
+ return -ENOMEM;
+
+ msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
+ GFP_KERNEL);
+ if (!msi->grps)
+ return -ENOMEM;
+
+ for (i = 0; i < msi->nr_irqs; i++) {
+ unsigned int irq = irq_of_parse_and_map(node, i);
+
+ if (!irq) {
+ dev_err(pcie->dev, "unable to parse/map interrupt\n");
+ ret = -ENODEV;
+ goto free_irqs;
+ }
+ msi->grps[i].gic_irq = irq;
+ msi->grps[i].msi = msi;
+ msi->grps[i].eq = i;
+ }
+
+ /* Reserve memory for event queue and make sure memories are zeroed */
+ msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
+ msi->nr_eq_region * EQ_MEM_REGION_SIZE,
+ &msi->eq_dma, GFP_KERNEL);
+ if (!msi->eq_cpu) {
+ ret = -ENOMEM;
+ goto free_irqs;
+ }
+
+ ret = iproc_msi_alloc_domains(node, msi);
+ if (ret) {
+ dev_err(pcie->dev, "failed to create MSI domains\n");
+ goto free_eq_dma;
+ }
+
+ for_each_online_cpu(cpu) {
+ ret = iproc_msi_irq_setup(msi, cpu);
+ if (ret)
+ goto free_msi_irq;
+ }
+
+ iproc_msi_enable(msi);
+
+ return 0;
+
+free_msi_irq:
+ for_each_online_cpu(cpu)
+ iproc_msi_irq_free(msi, cpu);
+ iproc_msi_free_domains(msi);
+
+free_eq_dma:
+ dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
+ msi->eq_cpu, msi->eq_dma);
+
+free_irqs:
+ for (i = 0; i < msi->nr_irqs; i++) {
+ if (msi->grps[i].gic_irq)
+ irq_dispose_mapping(msi->grps[i].gic_irq);
+ }
+ pcie->msi = NULL;
+ return ret;
+}
+EXPORT_SYMBOL(iproc_msi_init);
+
+void iproc_msi_exit(struct iproc_pcie *pcie)
+{
+ struct iproc_msi *msi = pcie->msi;
+ unsigned int i, cpu;
+
+ if (!msi)
+ return;
+
+ iproc_msi_disable(msi);
+
+ for_each_online_cpu(cpu)
+ iproc_msi_irq_free(msi, cpu);
+
+ iproc_msi_free_domains(msi);
+
+ dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
+ msi->eq_cpu, msi->eq_dma);
+
+ for (i = 0; i < msi->nr_irqs; i++) {
+ if (msi->grps[i].gic_irq)
+ irq_dispose_mapping(msi->grps[i].gic_irq);
+ }
+}
+EXPORT_SYMBOL(iproc_msi_exit);
#include "pcie-iproc.h"
+static const struct of_device_id iproc_pcie_of_match_table[] = {
+ {
+ .compatible = "brcm,iproc-pcie",
+ .data = (int *)IPROC_PCIE_PAXB,
+ }, {
+ .compatible = "brcm,iproc-pcie-paxc",
+ .data = (int *)IPROC_PCIE_PAXC,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
+
static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
{
+ const struct of_device_id *of_id;
struct iproc_pcie *pcie;
struct device_node *np = pdev->dev.of_node;
struct resource reg;
LIST_HEAD(res);
int ret;
+ of_id = of_match_device(iproc_pcie_of_match_table, &pdev->dev);
+ if (!of_id)
+ return -EINVAL;
+
pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
pcie->dev = &pdev->dev;
+ pcie->type = (enum iproc_pcie_type)of_id->data;
platform_set_drvdata(pdev, pcie);
ret = of_address_to_resource(np, 0, ®);
dev_err(pcie->dev, "unable to map controller registers\n");
return -ENOMEM;
}
+ pcie->base_addr = reg.start;
if (of_property_read_bool(np, "brcm,pcie-ob")) {
u32 val;
return iproc_pcie_remove(pcie);
}
-static const struct of_device_id iproc_pcie_of_match_table[] = {
- { .compatible = "brcm,iproc-pcie", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
-
static struct platform_driver iproc_pcie_pltfm_driver = {
.driver = {
.name = "iproc-pcie",
#include "pcie-iproc.h"
-#define CLK_CONTROL_OFFSET 0x000
#define EP_PERST_SOURCE_SELECT_SHIFT 2
#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
#define EP_MODE_SURVIVE_PERST_SHIFT 1
#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
#define RC_PCIE_RST_OUTPUT_SHIFT 0
#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
+#define PAXC_RESET_MASK 0x7f
-#define CFG_IND_ADDR_OFFSET 0x120
#define CFG_IND_ADDR_MASK 0x00001ffc
-#define CFG_IND_DATA_OFFSET 0x124
-
-#define CFG_ADDR_OFFSET 0x1f8
#define CFG_ADDR_BUS_NUM_SHIFT 20
#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
#define CFG_ADDR_DEV_NUM_SHIFT 15
#define CFG_ADDR_CFG_TYPE_SHIFT 0
#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
-#define CFG_DATA_OFFSET 0x1fc
-
-#define SYS_RC_INTX_EN 0x330
#define SYS_RC_INTX_MASK 0xf
-#define PCIE_LINK_STATUS_OFFSET 0xf0c
#define PCIE_PHYLINKUP_SHIFT 3
#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
#define PCIE_DL_ACTIVE_SHIFT 2
#define OARR_SIZE_CFG_SHIFT 1
#define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT)
-#define OARR_LO(window) (0xd20 + (window) * 8)
-#define OARR_HI(window) (0xd24 + (window) * 8)
-#define OMAP_LO(window) (0xd40 + (window) * 8)
-#define OMAP_HI(window) (0xd44 + (window) * 8)
-
#define MAX_NUM_OB_WINDOWS 2
+#define MAX_NUM_PAXC_PF 4
+
+#define IPROC_PCIE_REG_INVALID 0xffff
+
+enum iproc_pcie_reg {
+ IPROC_PCIE_CLK_CTRL = 0,
+ IPROC_PCIE_CFG_IND_ADDR,
+ IPROC_PCIE_CFG_IND_DATA,
+ IPROC_PCIE_CFG_ADDR,
+ IPROC_PCIE_CFG_DATA,
+ IPROC_PCIE_INTX_EN,
+ IPROC_PCIE_OARR_LO,
+ IPROC_PCIE_OARR_HI,
+ IPROC_PCIE_OMAP_LO,
+ IPROC_PCIE_OMAP_HI,
+ IPROC_PCIE_LINK_STATUS,
+};
+
+/* iProc PCIe PAXB registers */
+static const u16 iproc_pcie_reg_paxb[] = {
+ [IPROC_PCIE_CLK_CTRL] = 0x000,
+ [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
+ [IPROC_PCIE_CFG_IND_DATA] = 0x124,
+ [IPROC_PCIE_CFG_ADDR] = 0x1f8,
+ [IPROC_PCIE_CFG_DATA] = 0x1fc,
+ [IPROC_PCIE_INTX_EN] = 0x330,
+ [IPROC_PCIE_OARR_LO] = 0xd20,
+ [IPROC_PCIE_OARR_HI] = 0xd24,
+ [IPROC_PCIE_OMAP_LO] = 0xd40,
+ [IPROC_PCIE_OMAP_HI] = 0xd44,
+ [IPROC_PCIE_LINK_STATUS] = 0xf0c,
+};
+
+/* iProc PCIe PAXC v1 registers */
+static const u16 iproc_pcie_reg_paxc[] = {
+ [IPROC_PCIE_CLK_CTRL] = 0x000,
+ [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
+ [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
+ [IPROC_PCIE_CFG_ADDR] = 0x1f8,
+ [IPROC_PCIE_CFG_DATA] = 0x1fc,
+ [IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID,
+ [IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID,
+ [IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID,
+ [IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID,
+ [IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID,
+ [IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID,
+};
static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
{
return pcie;
}
+static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
+{
+ return !!(reg_offset == IPROC_PCIE_REG_INVALID);
+}
+
+static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
+ enum iproc_pcie_reg reg)
+{
+ return pcie->reg_offsets[reg];
+}
+
+static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
+ enum iproc_pcie_reg reg)
+{
+ u16 offset = iproc_pcie_reg_offset(pcie, reg);
+
+ if (iproc_pcie_reg_is_invalid(offset))
+ return 0;
+
+ return readl(pcie->base + offset);
+}
+
+static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
+ enum iproc_pcie_reg reg, u32 val)
+{
+ u16 offset = iproc_pcie_reg_offset(pcie, reg);
+
+ if (iproc_pcie_reg_is_invalid(offset))
+ return;
+
+ writel(val, pcie->base + offset);
+}
+
+static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
+ enum iproc_pcie_reg reg,
+ unsigned window, u32 val)
+{
+ u16 offset = iproc_pcie_reg_offset(pcie, reg);
+
+ if (iproc_pcie_reg_is_invalid(offset))
+ return;
+
+ writel(val, pcie->base + offset + (window * 8));
+}
+
+static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
+ unsigned int slot,
+ unsigned int fn)
+{
+ if (slot > 0)
+ return false;
+
+ /* PAXC can only support limited number of functions */
+ if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
+ return false;
+
+ return true;
+}
+
/**
* Note access to the configuration registers are protected at the higher layer
* by 'pci_lock' in drivers/pci/access.c
unsigned fn = PCI_FUNC(devfn);
unsigned busno = bus->number;
u32 val;
+ u16 offset;
+
+ if (!iproc_pcie_device_is_valid(pcie, slot, fn))
+ return NULL;
/* root complex access */
if (busno == 0) {
- if (slot >= 1)
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
+ where & CFG_IND_ADDR_MASK);
+ offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
+ if (iproc_pcie_reg_is_invalid(offset))
return NULL;
- writel(where & CFG_IND_ADDR_MASK,
- pcie->base + CFG_IND_ADDR_OFFSET);
- return (pcie->base + CFG_IND_DATA_OFFSET);
+ else
+ return (pcie->base + offset);
}
- if (fn > 1)
- return NULL;
-
/* EP device access */
val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
(slot << CFG_ADDR_DEV_NUM_SHIFT) |
(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
(where & CFG_ADDR_REG_NUM_MASK) |
(1 & CFG_ADDR_CFG_TYPE_MASK);
- writel(val, pcie->base + CFG_ADDR_OFFSET);
-
- return (pcie->base + CFG_DATA_OFFSET);
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
+ offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
+ if (iproc_pcie_reg_is_invalid(offset))
+ return NULL;
+ else
+ return (pcie->base + offset);
}
static struct pci_ops iproc_pcie_ops = {
{
u32 val;
+ if (pcie->type == IPROC_PCIE_PAXC) {
+ val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
+ val &= ~PAXC_RESET_MASK;
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
+ udelay(100);
+ val |= PAXC_RESET_MASK;
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
+ udelay(100);
+ return;
+ }
+
/*
* Select perst_b signal as reset source. Put the device into reset,
* and then bring it out of reset
*/
- val = readl(pcie->base + CLK_CONTROL_OFFSET);
+ val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
~RC_PCIE_RST_OUTPUT;
- writel(val, pcie->base + CLK_CONTROL_OFFSET);
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
udelay(250);
val |= RC_PCIE_RST_OUTPUT;
- writel(val, pcie->base + CLK_CONTROL_OFFSET);
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
msleep(100);
}
u16 pos, link_status;
bool link_is_active = false;
- val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
+ /*
+ * PAXC connects to emulated endpoint devices directly and does not
+ * have a Serdes. Therefore skip the link detection logic here.
+ */
+ if (pcie->type == IPROC_PCIE_PAXC)
+ return 0;
+
+ val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
return -ENODEV;
static void iproc_pcie_enable(struct iproc_pcie *pcie)
{
- writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
+ iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
}
/**
if (size > max_size) {
dev_err(pcie->dev,
- "res size 0x%pap exceeds max supported size 0x%llx\n",
+ "res size %pap exceeds max supported size 0x%llx\n",
&size, max_size);
return -EINVAL;
}
axi_addr -= ob->axi_offset;
for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
- writel(lower_32_bits(axi_addr) | OARR_VALID |
- (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
- writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
- writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
- writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
+ lower_32_bits(axi_addr) | OARR_VALID |
+ (ob->set_oarr_size ? 1 : 0));
+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
+ upper_32_bits(axi_addr));
+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
+ lower_32_bits(pci_addr));
+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
+ upper_32_bits(pci_addr));
size -= ob->window_size;
if (size == 0)
return 0;
}
+static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
+{
+ struct device_node *msi_node;
+
+ msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
+ if (!msi_node)
+ return -ENODEV;
+
+ /*
+ * If another MSI controller is being used, the call below should fail
+ * but that is okay
+ */
+ return iproc_msi_init(pcie, msi_node);
+}
+
+static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
+{
+ iproc_msi_exit(pcie);
+}
+
int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
{
int ret;
goto err_exit_phy;
}
+ switch (pcie->type) {
+ case IPROC_PCIE_PAXB:
+ pcie->reg_offsets = iproc_pcie_reg_paxb;
+ break;
+ case IPROC_PCIE_PAXC:
+ pcie->reg_offsets = iproc_pcie_reg_paxc;
+ break;
+ default:
+ dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
+ ret = -EINVAL;
+ goto err_power_off_phy;
+ }
+
iproc_pcie_reset(pcie);
if (pcie->need_ob_cfg) {
iproc_pcie_enable(pcie);
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ if (iproc_pcie_msi_enable(pcie))
+ dev_info(pcie->dev, "not using iProc MSI\n");
+
pci_scan_child_bus(bus);
pci_assign_unassigned_bus_resources(bus);
pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
pci_stop_root_bus(pcie->root_bus);
pci_remove_root_bus(pcie->root_bus);
+ iproc_pcie_msi_disable(pcie);
+
phy_power_off(pcie->phy);
phy_exit(pcie->phy);
#ifndef _PCIE_IPROC_H
#define _PCIE_IPROC_H
+/**
+ * iProc PCIe interface type
+ *
+ * PAXB is the wrapper used in root complex that can be connected to an
+ * external endpoint device.
+ *
+ * PAXC is the wrapper used in root complex dedicated for internal emulated
+ * endpoint devices.
+ */
+enum iproc_pcie_type {
+ IPROC_PCIE_PAXB = 0,
+ IPROC_PCIE_PAXC,
+};
+
/**
* iProc PCIe outbound mapping
* @set_oarr_size: indicates the OARR size bit needs to be set
resource_size_t window_size;
};
+struct iproc_msi;
+
/**
* iProc PCIe device
+ *
* @dev: pointer to device data structure
+ * @type: iProc PCIe interface type
+ * @reg_offsets: register offsets
* @base: PCIe host controller I/O register base
+ * @base_addr: PCIe host controller register base physical address
* @sysdata: Per PCI controller data (ARM-specific)
* @root_bus: pointer to root bus
* @phy: optional PHY device that controls the Serdes
- * @irqs: interrupt IDs
* @map_irq: function callback to map interrupts
- * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
+ * @need_ob_cfg: indicates SW needs to configure the outbound mapping window
* @ob: outbound mapping parameters
+ * @msi: MSI data
*/
struct iproc_pcie {
struct device *dev;
+ enum iproc_pcie_type type;
+ const u16 *reg_offsets;
void __iomem *base;
+ phys_addr_t base_addr;
#ifdef CONFIG_ARM
struct pci_sys_data sysdata;
#endif
int (*map_irq)(const struct pci_dev *, u8, u8);
bool need_ob_cfg;
struct iproc_pcie_ob ob;
+ struct iproc_msi *msi;
};
int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);
int iproc_pcie_remove(struct iproc_pcie *pcie);
+#ifdef CONFIG_PCIE_IPROC_MSI
+int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);
+void iproc_msi_exit(struct iproc_pcie *pcie);
+#else
+static inline int iproc_msi_init(struct iproc_pcie *pcie,
+ struct device_node *node)
+{
+ return -ENODEV;
+}
+static inline void iproc_msi_exit(struct iproc_pcie *pcie)
+{
+}
+#endif
+
#endif /* _PCIE_IPROC_H */
--- /dev/null
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Copyright 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+#define PCIE20_PARF_PHY_CTRL 0x40
+#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define PCIE20_PARF_DBI_BASE_ADDR 0x168
+#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
+#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
+
+#define PCIE20_ELBI_SYS_CTRL 0x04
+#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
+
+#define PCIE20_CAP 0x70
+
+#define PERST_DELAY_US 1000
+
+struct qcom_pcie_resources_v0 {
+ struct clk *iface_clk;
+ struct clk *core_clk;
+ struct clk *phy_clk;
+ struct reset_control *pci_reset;
+ struct reset_control *axi_reset;
+ struct reset_control *ahb_reset;
+ struct reset_control *por_reset;
+ struct reset_control *phy_reset;
+ struct regulator *vdda;
+ struct regulator *vdda_phy;
+ struct regulator *vdda_refclk;
+};
+
+struct qcom_pcie_resources_v1 {
+ struct clk *iface;
+ struct clk *aux;
+ struct clk *master_bus;
+ struct clk *slave_bus;
+ struct reset_control *core;
+ struct regulator *vdda;
+};
+
+union qcom_pcie_resources {
+ struct qcom_pcie_resources_v0 v0;
+ struct qcom_pcie_resources_v1 v1;
+};
+
+struct qcom_pcie;
+
+struct qcom_pcie_ops {
+ int (*get_resources)(struct qcom_pcie *pcie);
+ int (*init)(struct qcom_pcie *pcie);
+ void (*deinit)(struct qcom_pcie *pcie);
+};
+
+struct qcom_pcie {
+ struct pcie_port pp;
+ struct device *dev;
+ union qcom_pcie_resources res;
+ void __iomem *parf;
+ void __iomem *dbi;
+ void __iomem *elbi;
+ struct phy *phy;
+ struct gpio_desc *reset;
+ struct qcom_pcie_ops *ops;
+};
+
+#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
+
+static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
+{
+ gpiod_set_value(pcie->reset, 1);
+ usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
+}
+
+static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
+{
+ gpiod_set_value(pcie->reset, 0);
+ usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
+}
+
+static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+
+ return dw_handle_msi_irq(pp);
+}
+
+static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ unsigned int retries = 0;
+ u32 val;
+
+ if (dw_pcie_link_up(&pcie->pp))
+ return 0;
+
+ /* enable link training */
+ val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
+ val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
+ writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
+
+ do {
+ if (dw_pcie_link_up(&pcie->pp))
+ return 0;
+ usleep_range(250, 1000);
+ } while (retries < 200);
+
+ dev_warn(dev, "phy link never came up\n");
+
+ return -ETIMEDOUT;
+}
+
+static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+ struct device *dev = pcie->dev;
+
+ res->vdda = devm_regulator_get(dev, "vdda");
+ if (IS_ERR(res->vdda))
+ return PTR_ERR(res->vdda);
+
+ res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
+ if (IS_ERR(res->vdda_phy))
+ return PTR_ERR(res->vdda_phy);
+
+ res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
+ if (IS_ERR(res->vdda_refclk))
+ return PTR_ERR(res->vdda_refclk);
+
+ res->iface_clk = devm_clk_get(dev, "iface");
+ if (IS_ERR(res->iface_clk))
+ return PTR_ERR(res->iface_clk);
+
+ res->core_clk = devm_clk_get(dev, "core");
+ if (IS_ERR(res->core_clk))
+ return PTR_ERR(res->core_clk);
+
+ res->phy_clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(res->phy_clk))
+ return PTR_ERR(res->phy_clk);
+
+ res->pci_reset = devm_reset_control_get(dev, "pci");
+ if (IS_ERR(res->pci_reset))
+ return PTR_ERR(res->pci_reset);
+
+ res->axi_reset = devm_reset_control_get(dev, "axi");
+ if (IS_ERR(res->axi_reset))
+ return PTR_ERR(res->axi_reset);
+
+ res->ahb_reset = devm_reset_control_get(dev, "ahb");
+ if (IS_ERR(res->ahb_reset))
+ return PTR_ERR(res->ahb_reset);
+
+ res->por_reset = devm_reset_control_get(dev, "por");
+ if (IS_ERR(res->por_reset))
+ return PTR_ERR(res->por_reset);
+
+ res->phy_reset = devm_reset_control_get(dev, "phy");
+ if (IS_ERR(res->phy_reset))
+ return PTR_ERR(res->phy_reset);
+
+ return 0;
+}
+
+static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+ struct device *dev = pcie->dev;
+
+ res->vdda = devm_regulator_get(dev, "vdda");
+ if (IS_ERR(res->vdda))
+ return PTR_ERR(res->vdda);
+
+ res->iface = devm_clk_get(dev, "iface");
+ if (IS_ERR(res->iface))
+ return PTR_ERR(res->iface);
+
+ res->aux = devm_clk_get(dev, "aux");
+ if (IS_ERR(res->aux))
+ return PTR_ERR(res->aux);
+
+ res->master_bus = devm_clk_get(dev, "master_bus");
+ if (IS_ERR(res->master_bus))
+ return PTR_ERR(res->master_bus);
+
+ res->slave_bus = devm_clk_get(dev, "slave_bus");
+ if (IS_ERR(res->slave_bus))
+ return PTR_ERR(res->slave_bus);
+
+ res->core = devm_reset_control_get(dev, "core");
+ if (IS_ERR(res->core))
+ return PTR_ERR(res->core);
+
+ return 0;
+}
+
+static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+
+ reset_control_assert(res->pci_reset);
+ reset_control_assert(res->axi_reset);
+ reset_control_assert(res->ahb_reset);
+ reset_control_assert(res->por_reset);
+ reset_control_assert(res->pci_reset);
+ clk_disable_unprepare(res->iface_clk);
+ clk_disable_unprepare(res->core_clk);
+ clk_disable_unprepare(res->phy_clk);
+ regulator_disable(res->vdda);
+ regulator_disable(res->vdda_phy);
+ regulator_disable(res->vdda_refclk);
+}
+
+static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+ struct device *dev = pcie->dev;
+ u32 val;
+ int ret;
+
+ ret = regulator_enable(res->vdda);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda regulator\n");
+ return ret;
+ }
+
+ ret = regulator_enable(res->vdda_refclk);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda_refclk regulator\n");
+ goto err_refclk;
+ }
+
+ ret = regulator_enable(res->vdda_phy);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda_phy regulator\n");
+ goto err_vdda_phy;
+ }
+
+ ret = reset_control_assert(res->ahb_reset);
+ if (ret) {
+ dev_err(dev, "cannot assert ahb reset\n");
+ goto err_assert_ahb;
+ }
+
+ ret = clk_prepare_enable(res->iface_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable iface clock\n");
+ goto err_assert_ahb;
+ }
+
+ ret = clk_prepare_enable(res->phy_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable phy clock\n");
+ goto err_clk_phy;
+ }
+
+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
+ ret = reset_control_deassert(res->ahb_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert ahb reset\n");
+ goto err_deassert_ahb;
+ }
+
+ /* enable PCIe clocks and resets */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ /* enable external reference clock */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ val |= BIT(16);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+
+ ret = reset_control_deassert(res->phy_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert phy reset\n");
+ return ret;
+ }
+
+ ret = reset_control_deassert(res->pci_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert pci reset\n");
+ return ret;
+ }
+
+ ret = reset_control_deassert(res->por_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert por reset\n");
+ return ret;
+ }
+
+ ret = reset_control_deassert(res->axi_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert axi reset\n");
+ return ret;
+ }
+
+ /* wait for clock acquisition */
+ usleep_range(1000, 1500);
+
+ return 0;
+
+err_deassert_ahb:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
+ clk_disable_unprepare(res->phy_clk);
+err_clk_phy:
+ clk_disable_unprepare(res->iface_clk);
+err_assert_ahb:
+ regulator_disable(res->vdda_phy);
+err_vdda_phy:
+ regulator_disable(res->vdda_refclk);
+err_refclk:
+ regulator_disable(res->vdda);
+
+ return ret;
+}
+
+static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+
+ reset_control_assert(res->core);
+ clk_disable_unprepare(res->slave_bus);
+ clk_disable_unprepare(res->master_bus);
+ clk_disable_unprepare(res->iface);
+ clk_disable_unprepare(res->aux);
+ regulator_disable(res->vdda);
+}
+
+static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+ struct device *dev = pcie->dev;
+ int ret;
+
+ ret = reset_control_deassert(res->core);
+ if (ret) {
+ dev_err(dev, "cannot deassert core reset\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(res->aux);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_res;
+ }
+
+ ret = clk_prepare_enable(res->iface);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable iface clock\n");
+ goto err_aux;
+ }
+
+ ret = clk_prepare_enable(res->master_bus);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable master_bus clock\n");
+ goto err_iface;
+ }
+
+ ret = clk_prepare_enable(res->slave_bus);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable slave_bus clock\n");
+ goto err_master;
+ }
+
+ ret = regulator_enable(res->vdda);
+ if (ret) {
+ dev_err(dev, "cannot enable vdda regulator\n");
+ goto err_slave;
+ }
+
+ /* change DBI base address */
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+
+ val |= BIT(31);
+ writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+ }
+
+ return 0;
+err_slave:
+ clk_disable_unprepare(res->slave_bus);
+err_master:
+ clk_disable_unprepare(res->master_bus);
+err_iface:
+ clk_disable_unprepare(res->iface);
+err_aux:
+ clk_disable_unprepare(res->aux);
+err_res:
+ reset_control_assert(res->core);
+
+ return ret;
+}
+
+static int qcom_pcie_link_up(struct pcie_port *pp)
+{
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
+ u16 val = readw(pcie->dbi + PCIE20_CAP + PCI_EXP_LNKSTA);
+
+ return !!(val & PCI_EXP_LNKSTA_DLLLA);
+}
+
+static void qcom_pcie_host_init(struct pcie_port *pp)
+{
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
+ int ret;
+
+ qcom_ep_reset_assert(pcie);
+
+ ret = pcie->ops->init(pcie);
+ if (ret)
+ goto err_deinit;
+
+ ret = phy_power_on(pcie->phy);
+ if (ret)
+ goto err_deinit;
+
+ dw_pcie_setup_rc(pp);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ dw_pcie_msi_init(pp);
+
+ qcom_ep_reset_deassert(pcie);
+
+ ret = qcom_pcie_establish_link(pcie);
+ if (ret)
+ goto err;
+
+ return;
+err:
+ qcom_ep_reset_assert(pcie);
+ phy_power_off(pcie->phy);
+err_deinit:
+ pcie->ops->deinit(pcie);
+}
+
+static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
+ u32 *val)
+{
+ /* the device class is not reported correctly from the register */
+ if (where == PCI_CLASS_REVISION && size == 4) {
+ *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
+ *val &= 0xff; /* keep revision id */
+ *val |= PCI_CLASS_BRIDGE_PCI << 16;
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+ return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+}
+
+static struct pcie_host_ops qcom_pcie_dw_ops = {
+ .link_up = qcom_pcie_link_up,
+ .host_init = qcom_pcie_host_init,
+ .rd_own_conf = qcom_pcie_rd_own_conf,
+};
+
+static const struct qcom_pcie_ops ops_v0 = {
+ .get_resources = qcom_pcie_get_resources_v0,
+ .init = qcom_pcie_init_v0,
+ .deinit = qcom_pcie_deinit_v0,
+};
+
+static const struct qcom_pcie_ops ops_v1 = {
+ .get_resources = qcom_pcie_get_resources_v1,
+ .init = qcom_pcie_init_v1,
+ .deinit = qcom_pcie_deinit_v1,
+};
+
+static int qcom_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct qcom_pcie *pcie;
+ struct pcie_port *pp;
+ int ret;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
+ pcie->dev = dev;
+
+ pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
+ if (IS_ERR(pcie->reset))
+ return PTR_ERR(pcie->reset);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
+ pcie->parf = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->parf))
+ return PTR_ERR(pcie->parf);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ pcie->dbi = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->dbi))
+ return PTR_ERR(pcie->dbi);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
+ pcie->elbi = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->elbi))
+ return PTR_ERR(pcie->elbi);
+
+ pcie->phy = devm_phy_optional_get(dev, "pciephy");
+ if (IS_ERR(pcie->phy))
+ return PTR_ERR(pcie->phy);
+
+ ret = pcie->ops->get_resources(pcie);
+ if (ret)
+ return ret;
+
+ pp = &pcie->pp;
+ pp->dev = dev;
+ pp->dbi_base = pcie->dbi;
+ pp->root_bus_nr = -1;
+ pp->ops = &qcom_pcie_dw_ops;
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
+ if (pp->msi_irq < 0)
+ return pp->msi_irq;
+
+ ret = devm_request_irq(dev, pp->msi_irq,
+ qcom_pcie_msi_irq_handler,
+ IRQF_SHARED, "qcom-pcie-msi", pp);
+ if (ret) {
+ dev_err(dev, "cannot request msi irq\n");
+ return ret;
+ }
+ }
+
+ ret = phy_init(pcie->phy);
+ if (ret)
+ return ret;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "cannot initialize host\n");
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pcie);
+
+ return 0;
+}
+
+static int qcom_pcie_remove(struct platform_device *pdev)
+{
+ struct qcom_pcie *pcie = platform_get_drvdata(pdev);
+
+ qcom_ep_reset_assert(pcie);
+ phy_power_off(pcie->phy);
+ phy_exit(pcie->phy);
+ pcie->ops->deinit(pcie);
+
+ return 0;
+}
+
+static const struct of_device_id qcom_pcie_match[] = {
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
+ { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
+ { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qcom_pcie_match);
+
+static struct platform_driver qcom_pcie_driver = {
+ .probe = qcom_pcie_probe,
+ .remove = qcom_pcie_remove,
+ .driver = {
+ .name = "qcom-pcie",
+ .of_match_table = qcom_pcie_match,
+ },
+};
+
+module_platform_driver(qcom_pcie_driver);
+
+MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
+MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
+MODULE_LICENSE("GPL v2");
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/slab.h>
#define DRV_NAME "rcar-pcie"
#define H1_PCIEPHYDOUTR 0x040014
#define H1_PCIEPHYSR 0x040018
+/* R-Car Gen2 PHY */
+#define GEN2_PCIEPHYADDR 0x780
+#define GEN2_PCIEPHYDATA 0x784
+#define GEN2_PCIEPHYCTRL 0x78c
+
#define INT_PCI_MSI_NR 32
#define RCONF(x) (PCICONF(0)+(x))
#define RCAR_PCI_MAX_RESOURCES 4
#define MAX_NR_INBOUND_MAPS 6
-static unsigned long global_io_offset;
-
struct rcar_msi {
DECLARE_BITMAP(used, INT_PCI_MSI_NR);
struct irq_domain *domain;
}
/* Structure representing the PCIe interface */
-/*
- * ARM pcibios functions expect the ARM struct pci_sys_data as the PCI
- * sysdata. Add pci_sys_data as the first element in struct gen_pci so
- * that when we use a gen_pci pointer as sysdata, it is also a pointer to
- * a struct pci_sys_data.
- */
struct rcar_pcie {
-#ifdef CONFIG_ARM
- struct pci_sys_data sys;
-#endif
struct device *dev;
void __iomem *base;
- struct resource res[RCAR_PCI_MAX_RESOURCES];
- struct resource busn;
+ struct list_head resources;
int root_bus_nr;
struct clk *clk;
struct clk *bus_clk;
.write = rcar_pcie_write_conf,
};
-static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
+static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
+ struct resource *res)
{
- struct resource *res = &pcie->res[win];
-
/* Setup PCIe address space mappings for each resource */
resource_size_t size;
resource_size_t res_start;
rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
}
-static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pcie)
+static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
{
- struct resource *res;
- int i;
-
- pcie->root_bus_nr = pcie->busn.start;
+ struct resource_entry *win;
+ int i = 0;
/* Setup PCI resources */
- for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
+ resource_list_for_each_entry(win, &pci->resources) {
+ struct resource *res = win->res;
- res = &pcie->res[i];
if (!res->flags)
continue;
- rcar_pcie_setup_window(i, pcie);
-
- if (res->flags & IORESOURCE_IO) {
- phys_addr_t io_start = pci_pio_to_address(res->start);
- pci_ioremap_io(global_io_offset, io_start);
- global_io_offset += SZ_64K;
+ switch (resource_type(res)) {
+ case IORESOURCE_IO:
+ case IORESOURCE_MEM:
+ rcar_pcie_setup_window(i, pci, res);
+ i++;
+ break;
+ case IORESOURCE_BUS:
+ pci->root_bus_nr = res->start;
+ break;
+ default:
+ continue;
}
pci_add_resource(resource, res);
}
- pci_add_resource(resource, &pcie->busn);
return 1;
}
return -ETIMEDOUT;
}
+static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
+{
+ /*
+ * These settings come from the R-Car Series, 2nd Generation User's
+ * Manual, section 50.3.1 (2) Initialization of the physical layer.
+ */
+ rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
+ rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
+ rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
+ rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
+
+ rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
+ /* The following value is for DC connection, no termination resistor */
+ rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
+ rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
+ rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
+
+ return rcar_pcie_hw_init(pcie);
+}
+
static int rcar_msi_alloc(struct rcar_msi *chip)
{
int msi;
/* Two irqs are for MSI, but they are also used for non-MSI irqs */
err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
- IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
+ IRQF_SHARED | IRQF_NO_THREAD,
+ rcar_msi_irq_chip.name, pcie);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
goto err;
}
err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
- IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
+ IRQF_SHARED | IRQF_NO_THREAD,
+ rcar_msi_irq_chip.name, pcie);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
goto err;
static const struct of_device_id rcar_pcie_of_match[] = {
{ .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
- { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
- { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
+ { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 },
+ { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init_gen2 },
+ { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init_gen2 },
+ { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
{},
};
MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
+static void rcar_pcie_release_of_pci_ranges(struct rcar_pcie *pci)
+{
+ pci_free_resource_list(&pci->resources);
+}
+
+static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
+{
+ int err;
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
+ resource_size_t iobase;
+ struct resource_entry *win;
+
+ err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, &iobase);
+ if (err)
+ return err;
+
+ resource_list_for_each_entry(win, &pci->resources) {
+ struct resource *parent, *res = win->res;
+
+ switch (resource_type(res)) {
+ case IORESOURCE_IO:
+ parent = &ioport_resource;
+ err = pci_remap_iospace(res, iobase);
+ if (err) {
+ dev_warn(dev, "error %d: failed to map resource %pR\n",
+ err, res);
+ continue;
+ }
+ break;
+ case IORESOURCE_MEM:
+ parent = &iomem_resource;
+ break;
+
+ case IORESOURCE_BUS:
+ default:
+ continue;
+ }
+
+ err = devm_request_resource(dev, parent, res);
+ if (err)
+ goto out_release_res;
+ }
+
+ return 0;
+
+out_release_res:
+ rcar_pcie_release_of_pci_ranges(pci);
+ return err;
+}
+
static int rcar_pcie_probe(struct platform_device *pdev)
{
struct rcar_pcie *pcie;
unsigned int data;
- struct of_pci_range range;
- struct of_pci_range_parser parser;
const struct of_device_id *of_id;
- int err, win = 0;
+ int err;
int (*hw_init_fn)(struct rcar_pcie *);
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
pcie->dev = &pdev->dev;
platform_set_drvdata(pdev, pcie);
- /* Get the bus range */
- if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
- dev_err(&pdev->dev, "failed to parse bus-range property\n");
- return -EINVAL;
- }
+ INIT_LIST_HEAD(&pcie->resources);
- if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
- dev_err(&pdev->dev, "missing ranges property\n");
- return -EINVAL;
- }
+ rcar_pcie_parse_request_of_pci_ranges(pcie);
err = rcar_pcie_get_resources(pdev, pcie);
if (err < 0) {
return err;
}
- for_each_of_pci_range(&parser, &range) {
- err = of_pci_range_to_resource(&range, pdev->dev.of_node,
- &pcie->res[win++]);
- if (err < 0)
- return err;
-
- if (win > RCAR_PCI_MAX_RESOURCES)
- break;
- }
-
err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
if (err)
return err;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- err = rcar_pcie_enable_msi(pcie);
- if (err < 0) {
- dev_err(&pdev->dev,
- "failed to enable MSI support: %d\n",
- err);
- return err;
- }
- }
-
of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
if (!of_id || !of_id->data)
return -EINVAL;
hw_init_fn = of_id->data;
+ pm_runtime_enable(pcie->dev);
+ err = pm_runtime_get_sync(pcie->dev);
+ if (err < 0) {
+ dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
+
/* Failure to get a link might just be that no cards are inserted */
err = hw_init_fn(pcie);
if (err) {
dev_info(&pdev->dev, "PCIe link down\n");
- return 0;
+ err = 0;
+ goto err_pm_put;
}
data = rcar_pci_read_reg(pcie, MACSR);
dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
- return rcar_pcie_enable(pcie);
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ err = rcar_pcie_enable_msi(pcie);
+ if (err < 0) {
+ dev_err(&pdev->dev,
+ "failed to enable MSI support: %d\n",
+ err);
+ goto err_pm_put;
+ }
+ }
+
+ err = rcar_pcie_enable(pcie);
+ if (err)
+ goto err_pm_put;
+
+ return 0;
+
+err_pm_put:
+ pm_runtime_put(pcie->dev);
+
+err_pm_disable:
+ pm_runtime_disable(pcie->dev);
+ return err;
}
static struct platform_driver rcar_pcie_driver = {
return -ENODEV;
}
ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
- IRQF_SHARED, "spear1340-pcie", pp);
+ IRQF_SHARED | IRQF_NO_THREAD,
+ "spear1340-pcie", pp);
if (ret) {
dev_err(dev, "failed to request irq %d\n", pp->irq);
return ret;
port->irq = irq_of_parse_and_map(node, 0);
err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
- IRQF_SHARED, "xilinx-pcie", port);
+ IRQF_SHARED | IRQF_NO_THREAD,
+ "xilinx-pcie", port);
if (err) {
dev_err(dev, "unable to request irq %d\n", port->irq);
return err;
#define MY_NAME "acpi_pcihp"
-#define dbg(fmt, arg...) do { if (debug_acpi) printk(KERN_DEBUG "%s: %s: " fmt , MY_NAME , __func__ , ## arg); } while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
+#define dbg(fmt, arg...) do { if (debug_acpi) printk(KERN_DEBUG "%s: %s: " fmt, MY_NAME, __func__, ## arg); } while (0)
+#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
#define METHOD_NAME__SUN "_SUN"
#define METHOD_NAME_OSHP "OSHP"
while (handle) {
acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
- dbg("Trying to get hotplug control for %s \n",
+ dbg("Trying to get hotplug control for %s\n",
(char *)string.pointer);
status = acpi_run_oshp(handle);
if (ACPI_SUCCESS(status))
/* function prototypes */
/* acpiphp_core.c */
-int acpiphp_register_attention(struct acpiphp_attention_info*info);
+int acpiphp_register_attention(struct acpiphp_attention_info *info);
int acpiphp_unregister_attention(struct acpiphp_attention_info *info);
int acpiphp_register_hotplug_slot(struct acpiphp_slot *slot, unsigned int sun);
void acpiphp_unregister_hotplug_slot(struct acpiphp_slot *slot);
MODULE_PARM_DESC(disable, "disable acpiphp driver");
module_param_named(disable, acpiphp_disabled, bool, 0444);
-static int enable_slot (struct hotplug_slot *slot);
-static int disable_slot (struct hotplug_slot *slot);
-static int set_attention_status (struct hotplug_slot *slot, u8 value);
-static int get_power_status (struct hotplug_slot *slot, u8 *value);
-static int get_attention_status (struct hotplug_slot *slot, u8 *value);
-static int get_latch_status (struct hotplug_slot *slot, u8 *value);
-static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
+static int enable_slot(struct hotplug_slot *slot);
+static int disable_slot(struct hotplug_slot *slot);
+static int set_attention_status(struct hotplug_slot *slot, u8 value);
+static int get_power_status(struct hotplug_slot *slot, u8 *value);
+static int get_attention_status(struct hotplug_slot *slot, u8 *value);
+static int get_latch_status(struct hotplug_slot *slot, u8 *value);
+static int get_adapter_status(struct hotplug_slot *slot, u8 *value);
static struct hotplug_slot_ops acpi_hotplug_slot_ops = {
.enable_slot = enable_slot,
unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
list_for_each_entry_safe_reverse(dev, tmp, &bus->devices, bus_list) {
- for (i=0; i<PCI_BRIDGE_RESOURCES; i++) {
+ for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
struct resource *res = &dev->resource[i];
if ((res->flags & type_mask) && !res->start &&
res->end) {
ibm_slot_done:
if (ret) {
ret = kmalloc(sizeof(union apci_descriptor), GFP_KERNEL);
- memcpy(ret, des, sizeof(union apci_descriptor));
+ if (ret)
+ memcpy(ret, des, sizeof(union apci_descriptor));
}
kfree(table);
return ret;
acpi_status stat;
unsigned long long rc;
union apci_descriptor *ibm_slot;
+ int id = hpslot_to_sun(slot);
- ibm_slot = ibm_slot_from_id(hpslot_to_sun(slot));
+ ibm_slot = ibm_slot_from_id(id);
+ if (!ibm_slot) {
+ pr_err("APLS null ACPI descriptor for slot %d\n", id);
+ return -ENODEV;
+ }
pr_debug("%s: set slot %d (%d) attention status to %d\n", __func__,
ibm_slot->slot.slot_num, ibm_slot->slot.slot_id,
static int ibm_get_attention_status(struct hotplug_slot *slot, u8 *status)
{
union apci_descriptor *ibm_slot;
+ int id = hpslot_to_sun(slot);
- ibm_slot = ibm_slot_from_id(hpslot_to_sun(slot));
+ ibm_slot = ibm_slot_from_id(id);
+ if (!ibm_slot) {
+ pr_err("APLS null ACPI descriptor for slot %d\n", id);
+ return -ENODEV;
+ }
if (ibm_slot->slot.attn & 0xa0 || ibm_slot->slot.status[1] & 0x08)
*status = 1;
}
size = 0;
- for (i=0; i<package->package.count; i++) {
+ for (i = 0; i < package->package.count; i++) {
memcpy(&lbuf[size],
package->package.elements[i].buffer.pointer,
package->package.elements[i].buffer.length);
};
struct cpci_hp_controller_ops {
- int (*query_enum) (void);
- int (*enable_irq) (void);
- int (*disable_irq) (void);
- int (*check_irq) (void *dev_id);
- int (*hardware_test) (struct slot *slot, u32 value);
- u8 (*get_power) (struct slot *slot);
- int (*set_power) (struct slot *slot, int value);
+ int (*query_enum)(void);
+ int (*enable_irq)(void);
+ int (*disable_irq)(void);
+ int (*check_irq)(void *dev_id);
+ int (*hardware_test)(struct slot *slot, u32 value);
+ u8 (*get_power)(struct slot *slot);
+ int (*set_power)(struct slot *slot, int value);
};
struct cpci_hp_controller {
#define dbg(format, arg...) \
do { \
if (cpci_debug) \
- printk (KERN_DEBUG "%s: " format "\n", \
- MY_NAME , ## arg); \
+ printk(KERN_DEBUG "%s: " format "\n", \
+ MY_NAME, ## arg); \
} while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
/* local variables */
static DECLARE_RWSEM(list_rwsem);
* with the pci_hotplug subsystem.
*/
for (i = first; i <= last; ++i) {
- slot = kzalloc(sizeof (struct slot), GFP_KERNEL);
+ slot = kzalloc(sizeof(struct slot), GFP_KERNEL);
if (!slot) {
status = -ENOMEM;
goto error;
}
hotplug_slot =
- kzalloc(sizeof (struct hotplug_slot), GFP_KERNEL);
+ kzalloc(sizeof(struct hotplug_slot), GFP_KERNEL);
if (!hotplug_slot) {
status = -ENOMEM;
goto error_slot;
}
slot->hotplug_slot = hotplug_slot;
- info = kzalloc(sizeof (struct hotplug_slot_info), GFP_KERNEL);
+ info = kzalloc(sizeof(struct hotplug_slot_info), GFP_KERNEL);
if (!info) {
status = -ENOMEM;
goto error_hpslot;
#define dbg(format, arg...) \
do { \
if (cpci_debug) \
- printk (KERN_DEBUG "%s: " format "\n", \
- MY_NAME , ## arg); \
+ printk(KERN_DEBUG "%s: " format "\n", \
+ MY_NAME, ## arg); \
} while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
u8 cpci_get_attention_status(struct slot *slot)
#define dbg(format, arg...) \
do { \
if (debug) \
- printk (KERN_DEBUG "%s: " format "\n", \
- MY_NAME , ## arg); \
+ printk(KERN_DEBUG "%s: " format "\n", \
+ MY_NAME, ## arg); \
} while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
/* local variables */
static bool debug;
bus = dev->subordinate;
pci_dev_put(dev);
- memset(&generic_hpc, 0, sizeof (struct cpci_hp_controller));
+ memset(&generic_hpc, 0, sizeof(struct cpci_hp_controller));
generic_hpc_ops.query_enum = query_enum;
generic_hpc.ops = &generic_hpc_ops;
#define dbg(format, arg...) \
do { \
if (debug) \
- printk (KERN_DEBUG "%s: " format "\n", \
- MY_NAME , ## arg); \
+ printk(KERN_DEBUG "%s: " format "\n", \
+ MY_NAME, ## arg); \
} while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
/* local variables */
static bool debug;
return 0;
}
-static int zt5550_hc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
+static int zt5550_hc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int status;
dbg("returned from zt5550_hc_config");
- memset(&zt5550_hpc, 0, sizeof (struct cpci_hp_controller));
+ memset(&zt5550_hpc, 0, sizeof(struct cpci_hp_controller));
zt5550_hpc_ops.query_enum = zt5550_hc_query_enum;
zt5550_hpc.ops = &zt5550_hpc_ops;
if (!poll) {
#define MY_NAME "cpqphp"
-#define dbg(fmt, arg...) do { if (cpqhp_debug) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
+#define dbg(fmt, arg...) do { if (cpqhp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
+#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
int cpqhp_hardware_test(struct controller *ctrl, int test_num);
/* resource functions */
-int cpqhp_resource_sort_and_combine (struct pci_resource **head);
+int cpqhp_resource_sort_and_combine(struct pci_resource **head);
/* pci functions */
int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num);
u8 hp_slot;
hp_slot = slot->device - ctrl->slot_device_offset;
- dbg("%s: slot->device = %d, ctrl->slot_device_offset = %d \n",
+ dbg("%s: slot->device = %d, ctrl->slot_device_offset = %d\n",
__func__, slot->device, ctrl->slot_device_offset);
status = (readl(ctrl->hpc_reg + INT_INPUT_CLEAR) & (0x01L << hp_slot));
static inline int wait_for_ctrl_irq(struct controller *ctrl)
{
- DECLARE_WAITQUEUE(wait, current);
+ DECLARE_WAITQUEUE(wait, current);
int retval = 0;
dbg("%s - start\n", __func__);
kfree(slot);
}
-static int ctrl_slot_cleanup (struct controller *ctrl)
+static int ctrl_slot_cleanup(struct controller *ctrl)
{
struct slot *old_slot, *next_slot;
while (old_slot) {
/* memory will be freed by the release_slot callback */
next_slot = old_slot->next;
- pci_hp_deregister (old_slot->hotplug_slot);
+ pci_hp_deregister(old_slot->hotplug_slot);
old_slot = next_slot;
}
mutex_lock(&ctrl->crit_sect);
if (status == 1)
- amber_LED_on (ctrl, hp_slot);
+ amber_LED_on(ctrl, hp_slot);
else if (status == 0)
- amber_LED_off (ctrl, hp_slot);
+ amber_LED_off(ctrl, hp_slot);
else {
/* Done with exclusive hardware access */
mutex_unlock(&ctrl->crit_sect);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
/* Done with exclusive hardware access */
mutex_unlock(&ctrl->crit_sect);
* @hotplug_slot: slot to change LED on
* @status: LED control flag
*/
-static int set_attention_status (struct hotplug_slot *hotplug_slot, u8 status)
+static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status)
{
struct pci_func *slot_func;
struct slot *slot = hotplug_slot->private;
u8 ctrl_slot;
u32 tempdword;
char name[SLOT_NAME_SIZE];
- void __iomem *slot_entry= NULL;
+ void __iomem *slot_entry = NULL;
int result;
dbg("%s\n", __func__);
if (cpqhp_debug)
pci_print_IRQ_route();
- dbg("Initialize + Start the notification mechanism \n");
+ dbg("Initialize + Start the notification mechanism\n");
retval = cpqhp_event_start_thread();
if (retval)
/* Map rom address */
cpqhp_rom_start = ioremap(ROM_PHY_ADDR, ROM_PHY_LEN);
if (!cpqhp_rom_start) {
- err ("Could not ioremap memory region for ROM\n");
+ err("Could not ioremap memory region for ROM\n");
retval = -EIO;
goto error;
}
smbios_table = detect_SMBIOS_pointer(cpqhp_rom_start,
cpqhp_rom_start + ROM_PHY_LEN);
if (!smbios_table) {
- err ("Could not find the SMBIOS pointer in memory\n");
+ err("Could not find the SMBIOS pointer in memory\n");
retval = -EIO;
goto error_rom_start;
}
smbios_start = ioremap(readl(smbios_table + ST_ADDRESS),
readw(smbios_table + ST_LENGTH));
if (!smbios_start) {
- err ("Could not ioremap memory region taken from SMBIOS values\n");
+ err("Could not ioremap memory region taken from SMBIOS values\n");
retval = -EIO;
goto error_smbios_start;
}
* Finish setting up the hot plug ctrl device
*/
ctrl->slot_device_offset = readb(ctrl->hpc_reg + SLOT_MASK) >> 4;
- dbg("NumSlots %d \n", ctrl->slot_device_offset);
+ dbg("NumSlots %d\n", ctrl->slot_device_offset);
ctrl->next_event = 0;
writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_MASK);
/* set up the interrupt */
- dbg("HPC interrupt = %d \n", ctrl->interrupt);
+ dbg("HPC interrupt = %d\n", ctrl->interrupt);
if (request_irq(ctrl->interrupt, cpqhp_ctrl_intr,
IRQF_SHARED, MY_NAME, ctrl)) {
err("Can't get irq %d for the hotplug pci controller\n",
while (ctrl) {
if (ctrl->hpc_reg) {
u16 misc;
- rc = read_slot_enable (ctrl);
+ rc = read_slot_enable(ctrl);
writeb(0, ctrl->hpc_reg + SLOT_SERR);
writel(0xFFFFFFC0L | ~rc, ctrl->hpc_reg + INT_MASK);
kfree(tres);
}
- kfree (ctrl->pci_bus);
+ kfree(ctrl->pci_bus);
tctrl = ctrl;
ctrl = ctrl->next;
cpqhp_debug = debug;
- info (DRIVER_DESC " version: " DRIVER_VERSION "\n");
+ info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
cpqhp_initialize_debugfs();
result = pci_register_driver(&cpqhpc_driver);
dbg("pci_register_driver = %d\n", result);
* Presence Change
*/
dbg("cpqsbd: Presence/Notify input change.\n");
- dbg(" Changed bits are 0x%4.4x\n", change );
+ dbg(" Changed bits are 0x%4.4x\n", change);
for (hp_slot = 0; hp_slot < 6; hp_slot++) {
if (change & (0x0101 << hp_slot)) {
taskInfo->event_type = INT_POWER_FAULT;
if (ctrl->rev < 4) {
- amber_LED_on (ctrl, hp_slot);
- green_LED_off (ctrl, hp_slot);
- set_SOGO (ctrl);
+ amber_LED_on(ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
+ set_SOGO(ctrl);
/* this is a fatal condition, we want
* to crash the machine to protect from
node = *head;
- if (node->length & (alignment -1)) {
+ if (node->length & (alignment - 1)) {
/* this one isn't an aligned length, so we'll make a new entry
* and split it up.
*/
if (!(*head))
return 1;
- dbg("*head->next = %p\n",(*head)->next);
+ dbg("*head->next = %p\n", (*head)->next);
if (!(*head)->next)
return 0; /* only one item on the list, already sorted! */
- dbg("*head->base = 0x%x\n",(*head)->base);
- dbg("*head->next->base = 0x%x\n",(*head)->next->base);
+ dbg("*head->base = 0x%x\n", (*head)->base);
+ dbg("*head->next->base = 0x%x\n", (*head)->next->base);
while (out_of_order) {
out_of_order = 0;
/* Read to clear posted writes */
misc = readw(ctrl->hpc_reg + MISC);
- dbg ("%s - waking up\n", __func__);
+ dbg("%s - waking up\n", __func__);
wake_up_interruptible(&ctrl->queue);
}
/*
* The board is already on
*/
- else if (is_slot_enabled (ctrl, hp_slot))
+ else if (is_slot_enabled(ctrl, hp_slot))
rc = CARD_FUNCTIONING;
else {
mutex_lock(&ctrl->crit_sect);
/* turn on board without attaching to the bus */
- enable_slot_power (ctrl, hp_slot);
+ enable_slot_power(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
/* Change bits in slot power register to force another shift out
* NOTE: this is to work around the timer bug */
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
adapter_speed = get_adapter_speed(ctrl, hp_slot);
if (bus->cur_bus_speed != adapter_speed)
rc = WRONG_BUS_FREQUENCY;
/* turn off board without attaching to the bus */
- disable_slot_power (ctrl, hp_slot);
+ disable_slot_power(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
mutex_lock(&ctrl->crit_sect);
- slot_enable (ctrl, hp_slot);
- green_LED_blink (ctrl, hp_slot);
+ slot_enable(ctrl, hp_slot);
+ green_LED_blink(ctrl, hp_slot);
- amber_LED_off (ctrl, hp_slot);
+ amber_LED_off(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
mutex_lock(&ctrl->crit_sect);
- amber_LED_on (ctrl, hp_slot);
- green_LED_off (ctrl, hp_slot);
- slot_disable (ctrl, hp_slot);
+ amber_LED_on(ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
+ slot_disable(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
mutex_lock(&ctrl->crit_sect);
- amber_LED_on (ctrl, hp_slot);
- green_LED_off (ctrl, hp_slot);
- slot_disable (ctrl, hp_slot);
+ amber_LED_on(ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
+ slot_disable(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
}
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
/* Change bits in slot power register to force another shift out
* NOTE: this is to work around the timer bug
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
adapter_speed = get_adapter_speed(ctrl, hp_slot);
if (bus->cur_bus_speed != adapter_speed)
rc = WRONG_BUS_FREQUENCY;
/* turn off board without attaching to the bus */
- disable_slot_power (ctrl, hp_slot);
+ disable_slot_power(ctrl, hp_slot);
set_SOGO(ctrl);
dbg("%s: after down\n", __func__);
dbg("%s: before slot_enable\n", __func__);
- slot_enable (ctrl, hp_slot);
+ slot_enable(ctrl, hp_slot);
dbg("%s: before green_LED_blink\n", __func__);
- green_LED_blink (ctrl, hp_slot);
+ green_LED_blink(ctrl, hp_slot);
dbg("%s: before amber_LED_blink\n", __func__);
- amber_LED_off (ctrl, hp_slot);
+ amber_LED_off(ctrl, hp_slot);
dbg("%s: before set_SOGO\n", __func__);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
dbg("%s: before wait_for_ctrl_irq\n", __func__);
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
dbg("%s: after wait_for_ctrl_irq\n", __func__);
dbg("%s: before up\n", __func__);
} else {
/* Get vendor/device ID u32 */
ctrl->pci_bus->number = func->bus;
- rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), PCI_VENDOR_ID, &temp_register);
+ rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(func->device, func->function), PCI_VENDOR_ID, &temp_register);
dbg("%s: pci_read_config_dword returns %d\n", __func__, rc);
dbg("%s: temp_register is %x\n", __func__, temp_register);
if (rc) {
mutex_lock(&ctrl->crit_sect);
- amber_LED_on (ctrl, hp_slot);
- green_LED_off (ctrl, hp_slot);
- slot_disable (ctrl, hp_slot);
+ amber_LED_on(ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
+ slot_disable(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
return rc;
mutex_lock(&ctrl->crit_sect);
- green_LED_on (ctrl, hp_slot);
+ green_LED_on(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
} else {
mutex_lock(&ctrl->crit_sect);
- amber_LED_on (ctrl, hp_slot);
- green_LED_off (ctrl, hp_slot);
- slot_disable (ctrl, hp_slot);
+ amber_LED_on(ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
+ slot_disable(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
mutex_lock(&ctrl->crit_sect);
- green_LED_off (ctrl, hp_slot);
- slot_disable (ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
+ slot_disable(ctrl, hp_slot);
set_SOGO(ctrl);
writeb(temp_byte, ctrl->hpc_reg + SLOT_SERR);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
if (pushbutton_pending)
cpqhp_pushbutton_thread(pushbutton_pending);
else
- for (ctrl = cpqhp_ctrl_list; ctrl; ctrl=ctrl->next)
+ for (ctrl = cpqhp_ctrl_list; ctrl; ctrl = ctrl->next)
interrupt_event_handler(ctrl);
}
dbg("event_thread signals exit\n");
{
cpqhp_event_thread = kthread_run(event_thread, NULL, "phpd_event");
if (IS_ERR(cpqhp_event_thread)) {
- err ("Can't start up our event thread\n");
+ err("Can't start up our event thread\n");
return PTR_ERR(cpqhp_event_thread);
}
info->latch_status = cpq_get_latch_status(ctrl, slot);
info->adapter_status = get_presence_status(ctrl, slot);
result = pci_hp_change_slot_info(slot->hotplug_slot, info);
- kfree (info);
+ kfree(info);
return result;
}
if (p_slot->state == BLINKINGOFF_STATE) {
/* slot is on */
dbg("turn on green LED\n");
- green_LED_on (ctrl, hp_slot);
+ green_LED_on(ctrl, hp_slot);
} else if (p_slot->state == BLINKINGON_STATE) {
/* slot is off */
dbg("turn off green LED\n");
- green_LED_off (ctrl, hp_slot);
+ green_LED_off(ctrl, hp_slot);
}
info(msg_button_cancel, p_slot->number);
p_slot->state = STATIC_STATE;
- amber_LED_off (ctrl, hp_slot);
+ amber_LED_off(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
}
else if (ctrl->event_queue[loop].event_type == INT_BUTTON_RELEASE) {
dbg("button release\n");
- if (is_slot_enabled (ctrl, hp_slot)) {
+ if (is_slot_enabled(ctrl, hp_slot)) {
dbg("slot is on\n");
p_slot->state = BLINKINGOFF_STATE;
info(msg_button_off, p_slot->number);
dbg("blink green LED and turn off amber\n");
- amber_LED_off (ctrl, hp_slot);
- green_LED_blink (ctrl, hp_slot);
+ amber_LED_off(ctrl, hp_slot);
+ green_LED_blink(ctrl, hp_slot);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
mutex_unlock(&ctrl->crit_sect);
init_timer(&p_slot->task_event);
dbg("In power_down_board, func = %p, ctrl = %p\n", func, ctrl);
if (!func) {
dbg("Error! func NULL in %s\n", __func__);
- return ;
+ return;
}
if (cpqhp_process_SS(ctrl, func) != 0) {
dbg("In add_board, func = %p, ctrl = %p\n", func, ctrl);
if (!func) {
dbg("Error! func NULL in %s\n", __func__);
- return ;
+ return;
}
if (ctrl != NULL) {
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
}
}
unsigned int devfn;
struct slot *p_slot;
struct pci_bus *pci_bus = ctrl->pci_bus;
- int physical_slot=0;
+ int physical_slot = 0;
device = func->device;
func = cpqhp_slot_find(ctrl->bus, device, index++);
devfn = PCI_DEVFN(func->device, func->function);
/* Check the Class Code */
- rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
+ rc = pci_bus_read_config_byte(pci_bus, devfn, 0x0B, &class_code);
if (rc)
return rc;
rc = REMOVE_NOT_SUPPORTED;
} else {
/* See if it's a bridge */
- rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
+ rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
if (rc)
return rc;
/* If it's a bridge, check the VGA Enable bit */
if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
- rc = pci_bus_read_config_byte (pci_bus, devfn, PCI_BRIDGE_CONTROL, &BCR);
+ rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_BRIDGE_CONTROL, &BCR);
if (rc)
return rc;
set_SOGO(ctrl);
/* Wait for SOGO interrupt */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
/* Get ready for next iteration */
long_delay((3*HZ)/10);
set_SOGO(ctrl);
/* Wait for SOGO interrupt */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
/* Get ready for next iteration */
long_delay((3*HZ)/10);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- wait_for_ctrl_irq (ctrl);
+ wait_for_ctrl_irq(ctrl);
break;
case 2:
/* Do other stuff here! */
dbg("%s\n", __func__);
/* Check for Multi-function device */
ctrl->pci_bus->number = func->bus;
- rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
+ rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
if (rc) {
dbg("%s: rc = %d\n", __func__, rc);
return rc;
rc = configure_new_function(ctrl, new_slot, behind_bridge, resources);
if (rc) {
- dbg("configure_new_function failed %d\n",rc);
+ dbg("configure_new_function failed %d\n", rc);
index = 0;
while (new_slot) {
* and creates a board structure */
while ((function < max_functions) && (!stop_it)) {
- pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(func->device, function), 0x00, &ID);
+ pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(func->device, function), 0x00, &ID);
if (ID == 0xFFFFFFFF) {
function++;
/* set Pre Mem base and Limit registers */
temp_word = p_mem_node->base >> 16;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
temp_word = (p_mem_node->base + p_mem_node->length - 1) >> 16;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
/* Adjust this to compensate for extra adjustment in first loop
*/
ID = 0xFFFFFFFF;
pci_bus->number = hold_bus_node->base;
- pci_bus_read_config_dword (pci_bus, PCI_DEVFN(device, 0), 0x00, &ID);
+ pci_bus_read_config_dword(pci_bus, PCI_DEVFN(device, 0), 0x00, &ID);
pci_bus->number = func->bus;
if (ID != 0xFFFFFFFF) { /* device present */
new_slot->status = 0;
rc = configure_new_device(ctrl, new_slot, 1, &temp_resources);
- dbg("configure_new_device rc=0x%x\n",rc);
+ dbg("configure_new_device rc=0x%x\n", rc);
} /* End of IF (device in slot?) */
} /* End of FOR loop */
temp_byte = temp_resources.bus_head->base - 1;
/* set subordinate bus */
- rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
+ rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
if (temp_resources.bus_head->length == 0) {
kfree(temp_resources.bus_head);
hold_IO_node->base = io_node->base + io_node->length;
temp_byte = (hold_IO_node->base) >> 8;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_IO_BASE, temp_byte);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_IO_BASE, temp_byte);
return_resource(&(resources->io_head), io_node);
}
func->io_head = hold_IO_node;
temp_byte = (io_node->base - 1) >> 8;
- rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
+ rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
return_resource(&(resources->io_head), io_node);
} else {
/* it doesn't need any IO */
temp_word = 0x0000;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_IO_LIMIT, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_IO_LIMIT, temp_word);
return_resource(&(resources->io_head), io_node);
kfree(hold_IO_node);
hold_mem_node->base = mem_node->base + mem_node->length;
temp_word = (hold_mem_node->base) >> 16;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_BASE, temp_word);
return_resource(&(resources->mem_head), mem_node);
}
/* configure end address */
temp_word = (mem_node->base - 1) >> 16;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
/* Return unused resources to the pool */
return_resource(&(resources->mem_head), mem_node);
} else {
/* it doesn't need any Mem */
temp_word = 0x0000;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, temp_word);
return_resource(&(resources->mem_head), mem_node);
kfree(hold_mem_node);
hold_p_mem_node->base = p_mem_node->base + p_mem_node->length;
temp_word = (hold_p_mem_node->base) >> 16;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, temp_word);
return_resource(&(resources->p_mem_head), p_mem_node);
}
func->p_mem_head = hold_p_mem_node;
temp_word = (p_mem_node->base - 1) >> 16;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
return_resource(&(resources->p_mem_head), p_mem_node);
} else {
/* it doesn't need any PMem */
temp_word = 0x0000;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, temp_word);
return_resource(&(resources->p_mem_head), p_mem_node);
kfree(hold_p_mem_node);
* PCI_COMMAND_INVALIDATE |
* PCI_COMMAND_PARITY |
* PCI_COMMAND_SERR */
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_COMMAND, command);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
/* set Bridge Control Register */
command = 0x07; /* = PCI_BRIDGE_CTL_PARITY |
* PCI_BRIDGE_CTL_SERR |
* PCI_BRIDGE_CTL_NO_ISA */
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
+ rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
} else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
/* Standard device */
- rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
+ rc = pci_bus_read_config_byte(pci_bus, devfn, 0x0B, &class_code);
if (class_code == PCI_BASE_CLASS_DISPLAY) {
/* Display (video) adapter (not supported) */
temp_register = 0xFFFFFFFF;
dbg("CND: bus=%d, devfn=%d, offset=%d\n", pci_bus->number, devfn, cloop);
- rc = pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
+ rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
- rc = pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp_register);
+ rc = pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);
dbg("CND: base = 0x%x\n", temp_register);
if (temp_register) { /* If this register is implemented */
} /* End of base register loop */
if (cpqhp_legacy_mode) {
/* Figure out which interrupt pin this function uses */
- rc = pci_bus_read_config_byte (pci_bus, devfn,
+ rc = pci_bus_read_config_byte(pci_bus, devfn,
PCI_INTERRUPT_PIN, &temp_byte);
/* If this function needs an interrupt and we are behind
resources->irqs->barber_pole - 1) & 0x03];
} else {
/* Program IRQ based on card type */
- rc = pci_bus_read_config_byte (pci_bus, devfn, 0x0B, &class_code);
+ rc = pci_bus_read_config_byte(pci_bus, devfn, 0x0B, &class_code);
if (class_code == PCI_BASE_CLASS_STORAGE)
IRQ = cpqhp_disk_irq;
}
/* IRQ Line */
- rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_INTERRUPT_LINE, IRQ);
+ rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_INTERRUPT_LINE, IRQ);
}
if (!behind_bridge) {
* PCI_COMMAND_INVALIDATE |
* PCI_COMMAND_PARITY |
* PCI_COMMAND_SERR */
- rc = pci_bus_write_config_word (pci_bus, devfn,
+ rc = pci_bus_write_config_word(pci_bus, devfn,
PCI_COMMAND, temp_word);
} else { /* End of Not-A-Bridge else */
/* It's some strange type of PCI adapter (Cardbus?) */
return 0;
free_and_out:
- cpqhp_destroy_resource_list (&temp_resources);
+ cpqhp_destroy_resource_list(&temp_resources);
- return_resource(&(resources-> bus_head), hold_bus_node);
- return_resource(&(resources-> io_head), hold_IO_node);
- return_resource(&(resources-> mem_head), hold_mem_node);
- return_resource(&(resources-> p_mem_head), hold_p_mem_node);
+ return_resource(&(resources->bus_head), hold_bus_node);
+ return_resource(&(resources->io_head), hold_IO_node);
+ return_resource(&(resources->mem_head), hold_mem_node);
+ return_resource(&(resources->p_mem_head), hold_p_mem_node);
return rc;
}
if ((*used + 1) > *avail)
return(1);
- *((u8*)*p_buffer) = value;
- tByte = (u8**)p_buffer;
+ *((u8 *)*p_buffer) = value;
+ tByte = (u8 **)p_buffer;
(*tByte)++;
- *used+=1;
+ *used += 1;
return(0);
}
**p_buffer = value;
(*p_buffer)++;
- *used+=4;
+ *used += 4;
return(0);
}
*
* returns 0 for non-Compaq ROM, 1 for Compaq ROM
*/
-static int check_for_compaq_ROM (void __iomem *rom_start)
+static int check_for_compaq_ROM(void __iomem *rom_start)
{
u8 temp1, temp2, temp3, temp4, temp5, temp6;
int result = 0;
(temp6 == 'Q')) {
result = 1;
}
- dbg ("%s - returned %d\n", __func__, result);
+ dbg("%s - returned %d\n", __func__, result);
return result;
}
-static u32 access_EV (u16 operation, u8 *ev_name, u8 *buffer, u32 *buf_size)
+static u32 access_EV(u16 operation, u8 *ev_name, u8 *buffer, u32 *buf_size)
{
unsigned long flags;
int op = operation;
*
* Read the hot plug Resource Table from NVRAM
*/
-static int load_HRT (void __iomem *rom_start)
+static int load_HRT(void __iomem *rom_start)
{
u32 available;
u32 temp_dword;
*
* Save the hot plug Resource Table in NVRAM
*/
-static u32 store_HRT (void __iomem *rom_start)
+static u32 store_HRT(void __iomem *rom_start)
{
u32 *buffer;
u32 *pFill;
if (!check_for_compaq_ROM(rom_start))
return(1);
- buffer = (u32*) evbuffer;
+ buffer = (u32 *) evbuffer;
if (!buffer)
return(1);
loop = 0;
while (resNode) {
- loop ++;
+ loop++;
/* base */
rc = add_dword(&pFill, resNode->base, &usedbytes, &available);
loop = 0;
while (resNode) {
- loop ++;
+ loop++;
/* base */
rc = add_dword(&pFill, resNode->base, &usedbytes, &available);
loop = 0;
while (resNode) {
- loop ++;
+ loop++;
/* base */
rc = add_dword(&pFill, resNode->base, &usedbytes, &available);
loop = 0;
while (resNode) {
- loop ++;
+ loop++;
/* base */
rc = add_dword(&pFill, resNode->base, &usedbytes, &available);
temp_dword = usedbytes;
- rc = access_EV(WRITE_EV, "CQTHPS", (u8*) buffer, &temp_dword);
+ rc = access_EV(WRITE_EV, "CQTHPS", (u8 *) buffer, &temp_dword);
dbg("usedbytes = 0x%x, length = 0x%x\n", usedbytes, temp_dword);
}
-void compaq_nvram_init (void __iomem *rom_start)
+void compaq_nvram_init(void __iomem *rom_start)
{
if (rom_start)
compaq_int15_entry_point = (rom_start + ROM_INT15_PHY_ADDR - ROM_PHY_ADDR);
}
-int compaq_nvram_load (void __iomem *rom_start, struct controller *ctrl)
+int compaq_nvram_load(void __iomem *rom_start, struct controller *ctrl)
{
u8 bus, device, function;
u8 nummem, numpmem, numio, numbus;
if (!evbuffer_init) {
/* Read the resource list information in from NVRAM */
if (load_HRT(rom_start))
- memset (evbuffer, 0, 1024);
+ memset(evbuffer, 0, 1024);
evbuffer_init = 1;
}
p_byte += 3;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length))
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length))
return 2;
bus = p_ev_ctrl->bus;
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length))
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length))
return 2;
/* Skip forward to the next entry */
p_byte += (nummem + numpmem + numio + numbus) * 8;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length))
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length))
return 2;
p_ev_ctrl = (struct ev_hrt_ctrl *) p_byte;
p_byte += 3;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length))
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length))
return 2;
bus = p_ev_ctrl->bus;
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length))
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length))
return 2;
while (nummem--) {
if (!mem_node)
break;
- mem_node->base = *(u32*)p_byte;
- dbg("mem base = %8.8x\n",mem_node->base);
+ mem_node->base = *(u32 *)p_byte;
+ dbg("mem base = %8.8x\n", mem_node->base);
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(mem_node);
return 2;
}
- mem_node->length = *(u32*)p_byte;
- dbg("mem length = %8.8x\n",mem_node->length);
+ mem_node->length = *(u32 *)p_byte;
+ dbg("mem length = %8.8x\n", mem_node->length);
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(mem_node);
return 2;
}
if (!p_mem_node)
break;
- p_mem_node->base = *(u32*)p_byte;
- dbg("pre-mem base = %8.8x\n",p_mem_node->base);
+ p_mem_node->base = *(u32 *)p_byte;
+ dbg("pre-mem base = %8.8x\n", p_mem_node->base);
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(p_mem_node);
return 2;
}
- p_mem_node->length = *(u32*)p_byte;
- dbg("pre-mem length = %8.8x\n",p_mem_node->length);
+ p_mem_node->length = *(u32 *)p_byte;
+ dbg("pre-mem length = %8.8x\n", p_mem_node->length);
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(p_mem_node);
return 2;
}
if (!io_node)
break;
- io_node->base = *(u32*)p_byte;
- dbg("io base = %8.8x\n",io_node->base);
+ io_node->base = *(u32 *)p_byte;
+ dbg("io base = %8.8x\n", io_node->base);
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(io_node);
return 2;
}
- io_node->length = *(u32*)p_byte;
- dbg("io length = %8.8x\n",io_node->length);
+ io_node->length = *(u32 *)p_byte;
+ dbg("io length = %8.8x\n", io_node->length);
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(io_node);
return 2;
}
if (!bus_node)
break;
- bus_node->base = *(u32*)p_byte;
+ bus_node->base = *(u32 *)p_byte;
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(bus_node);
return 2;
}
- bus_node->length = *(u32*)p_byte;
+ bus_node->length = *(u32 *)p_byte;
p_byte += 4;
- if (p_byte > ((u8*)p_EV_header + evbuffer_length)) {
+ if (p_byte > ((u8 *)p_EV_header + evbuffer_length)) {
kfree(bus_node);
return 2;
}
}
-int compaq_nvram_store (void __iomem *rom_start)
+int compaq_nvram_store(void __iomem *rom_start)
{
int rc = 1;
}
-int cpqhp_configure_device (struct controller *ctrl, struct pci_func *func)
+int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
{
struct pci_bus *child;
int num;
pci_lock_rescan_remove();
if (func->pci_dev == NULL)
- func->pci_dev = pci_get_bus_and_slot(func->bus,PCI_DEVFN(func->device, func->function));
+ func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
/* No pci device, we need to create it then */
if (func->pci_dev == NULL) {
dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
pci_lock_rescan_remove();
- for (j=0; j<8 ; j++) {
+ for (j = 0; j < 8 ; j++) {
struct pci_dev *temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j));
if (temp) {
pci_dev_put(temp);
{
u32 vendID = 0;
- if (pci_bus_read_config_dword (bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
+ if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
return -1;
if (vendID == 0xffffffff)
return -1;
- return pci_bus_read_config_dword (bus, devfn, offset, value);
+ return pci_bus_read_config_dword(bus, devfn, offset, value);
}
* @dev_num: device number of PCI device
* @slot: pointer to u8 where slot number will be returned
*/
-int cpqhp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
+int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
{
int rc = 0;
dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
/* Yep we got one. bridge ? */
if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
- pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
+ pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
/* XXX: no recursion, wtf? */
dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
return 0;
*bus_num = tbus;
*dev_num = tdevice;
ctrl->pci_bus->number = tbus;
- pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
+ pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
if (!nobridge || (work == 0xffffffff))
return 0;
dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
- pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
+ pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
- pci_bus_read_config_byte (ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
+ pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
dbg("Scan bus for Non Bridge: bus %d\n", tbus);
if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
*bus_num = tbus;
}
-int cpqhp_get_bus_dev (struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot)
+int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot)
{
/* plain (bridges allowed) */
return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
new_slot->pci_dev = pci_get_bus_and_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
for (cloop = 0; cloop < 0x20; cloop++) {
- rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
+ rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
if (rc)
return rc;
}
*
* returns 0 if success
*/
-int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func *new_slot)
+int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot)
{
long rc;
u8 class_code;
ID = 0xFFFFFFFF;
ctrl->pci_bus->number = new_slot->bus;
- pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
+ pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
if (ID == 0xFFFFFFFF)
return 2;
while (function < max_functions) {
if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
/* Recurse the subordinate bus */
- pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
+ pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
sub_bus = (int) secondary_bus;
new_slot->status = 0;
for (cloop = 0; cloop < 0x20; cloop++)
- pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
+ pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
function++;
devfn = PCI_DEVFN(func->device, func->function);
/* Check for Bridge */
- pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
+ pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
- pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
+ pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
sub_bus = (int) secondary_bus;
*/
for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
temp_register = 0xFFFFFFFF;
- pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
- pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
+ pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
+ pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
/* If this register is implemented */
if (base) {
if (base & 0x01L) {
/* Figure out IO and memory base lengths */
for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
temp_register = 0xFFFFFFFF;
- pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
- pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
+ pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
+ pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
/* If this register is implemented */
if (base) {
*
* returns 0 if success
*/
-int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func *func)
+int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func)
{
u8 cloop;
u8 header_type;
}
/* Figure out IO and memory base lengths */
for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
- pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base);
+ pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
temp_register = 0xFFFFFFFF;
pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
* registers are programmed last
*/
for (cloop = 0x3C; cloop > 0; cloop -= 4)
- pci_bus_write_config_dword (pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
+ pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
- pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
+ pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
/* If this is a bridge device, restore subordinate devices */
if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
- pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
+ pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
sub_bus = (int) secondary_bus;
*/
for (cloop = 16; cloop < 40; cloop += 4) {
- pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp);
+ pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp);
if (temp != func->config_space[cloop >> 2]) {
dbg("Config space compare failure!!! offset = %x\n", cloop);
pci_bus->number = func->bus;
devfn = PCI_DEVFN(func->device, func->function);
- pci_bus_read_config_dword (pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
+ pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
/* No adapter present */
if (temp_register == 0xFFFFFFFF)
return(ADAPTER_NOT_SAME);
/* Check for same revision number and class code */
- pci_bus_read_config_dword (pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
+ pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
/* Adapter not the same */
if (temp_register != func->config_space[0x08 >> 2])
return(ADAPTER_NOT_SAME);
/* Check for Bridge */
- pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
+ pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
/* In order to continue checking, we must program the
*/
temp_register = func->config_space[0x18 >> 2];
- pci_bus_write_config_dword (pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
+ pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
secondary_bus = (temp_register >> 8) & 0xFF;
/* Check to see if it is a standard config header */
else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
/* Check subsystem vendor and ID */
- pci_bus_read_config_dword (pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
+ pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
if (temp_register != func->config_space[0x2C >> 2]) {
/* If it's a SMART-2 and the register isn't
/* Figure out IO and memory base lengths */
for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
temp_register = 0xFFFFFFFF;
- pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
- pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
+ pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
+ pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
/* If this register is implemented */
if (base) {
if (rc)
return rc;
- one_slot = rom_resource_table + sizeof (struct hrt);
+ one_slot = rom_resource_table + sizeof(struct hrt);
i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
dbg("number_of_entries = %d\n", i);
/* If this entry isn't for our controller's bus, ignore it */
if (primary_bus != ctrl->bus) {
i--;
- one_slot += sizeof (struct slot_rt);
+ one_slot += sizeof(struct slot_rt);
continue;
}
/* find out if this entry is for an occupied slot */
ctrl->pci_bus->number = primary_bus;
- pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
+ pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
dbg("temp_D_word = %x\n", temp_dword);
if (temp_dword != 0xFFFFFFFF) {
/* If we can't find a match, skip this table entry */
if (!func) {
i--;
- one_slot += sizeof (struct slot_rt);
+ one_slot += sizeof(struct slot_rt);
continue;
}
/* this may not work and shouldn't be used */
}
i--;
- one_slot += sizeof (struct slot_rt);
+ one_slot += sizeof(struct slot_rt);
}
/* If all of the following fail, we don't have any resources for
*
* Puts node back in the resource list pointed to by head
*/
-void cpqhp_destroy_resource_list (struct resource_lists *resources)
+void cpqhp_destroy_resource_list(struct resource_lists *resources)
{
struct pci_resource *res, *tres;
*
* Puts node back in the resource list pointed to by head
*/
-void cpqhp_destroy_board_resources (struct pci_func *func)
+void cpqhp_destroy_board_resources(struct pci_func *func)
{
struct pci_resource *res, *tres;
#include "cpqphp.h"
static DEFINE_MUTEX(cpqphp_mutex);
-static int show_ctrl (struct controller *ctrl, char *buf)
+static int show_ctrl(struct controller *ctrl, char *buf)
{
char *out = buf;
int index;
return out - buf;
}
-static int show_dev (struct controller *ctrl, char *buf)
+static int show_dev(struct controller *ctrl, char *buf)
{
char *out = buf;
int index;
out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length);
res = res->next;
}
- slot=slot->next;
+ slot = slot->next;
}
return out - buf;
#else
#define MY_NAME THIS_MODULE->name
#endif
-#define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
-#define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
+#define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
+#define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
+#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
/* EBDA stuff */
#define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
-#define SLOT_ATTN(s,es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
+#define SLOT_ATTN(s, es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
? HPC_SLOT_ATTN_BLINK \
: ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
#include <asm/io_apic.h>
#include "ibmphp.h"
-#define attn_on(sl) ibmphp_hpc_writeslot (sl, HPC_SLOT_ATTNON)
-#define attn_off(sl) ibmphp_hpc_writeslot (sl, HPC_SLOT_ATTNOFF)
-#define attn_LED_blink(sl) ibmphp_hpc_writeslot (sl, HPC_SLOT_BLINKLED)
-#define get_ctrl_revision(sl, rev) ibmphp_hpc_readslot (sl, READ_REVLEVEL, rev)
-#define get_hpc_options(sl, opt) ibmphp_hpc_readslot (sl, READ_HPCOPTIONS, opt)
+#define attn_on(sl) ibmphp_hpc_writeslot(sl, HPC_SLOT_ATTNON)
+#define attn_off(sl) ibmphp_hpc_writeslot(sl, HPC_SLOT_ATTNOFF)
+#define attn_LED_blink(sl) ibmphp_hpc_writeslot(sl, HPC_SLOT_BLINKLED)
+#define get_ctrl_revision(sl, rev) ibmphp_hpc_readslot(sl, READ_REVLEVEL, rev)
+#define get_hpc_options(sl, opt) ibmphp_hpc_readslot(sl, READ_HPCOPTIONS, opt)
#define DRIVER_VERSION "0.6"
#define DRIVER_DESC "IBM Hot Plug PCI Controller Driver"
static bool debug;
module_param(debug, bool, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC (debug, "Debugging mode enabled or not");
-MODULE_LICENSE ("GPL");
-MODULE_DESCRIPTION (DRIVER_DESC);
+MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION(DRIVER_DESC);
struct pci_bus *ibmphp_pci_bus;
static int max_slots;
return rc;
}
-static int __init get_max_slots (void)
+static int __init get_max_slots(void)
{
struct slot *slot_cur;
- struct list_head *tmp;
u8 slot_count = 0;
- list_for_each(tmp, &ibmphp_slot_head) {
- slot_cur = list_entry(tmp, struct slot, ibm_slot_list);
+ list_for_each_entry(slot_cur, &ibmphp_slot_head, ibm_slot_list) {
/* sometimes the hot-pluggable slots start with 4 (not always from 1) */
slot_count = max(slot_count, slot_cur->number);
}
*value = SLOT_SPEED(myslot.ext_status);
} else
*value = MAX_ADAPTER_NONE;
- }
+ }
}
if (flag)
static int __init init_ops(void)
{
struct slot *slot_cur;
- struct list_head *tmp;
int retval;
int rc;
- list_for_each(tmp, &ibmphp_slot_head) {
- slot_cur = list_entry(tmp, struct slot, ibm_slot_list);
-
- if (!slot_cur)
- return -ENODEV;
-
+ list_for_each_entry(slot_cur, &ibmphp_slot_head, ibm_slot_list) {
debug("BEFORE GETTING SLOT STATUS, slot # %x\n",
slot_cur->number);
if (slot_cur->ctrl->revision == 0xFF)
info->attention_status = SLOT_ATTN(slot_cur->status,
slot_cur->ext_status);
info->latch_status = SLOT_LATCH(slot_cur->status);
- if (!SLOT_PRESENT(slot_cur->status)) {
- info->adapter_status = 0;
+ if (!SLOT_PRESENT(slot_cur->status)) {
+ info->adapter_status = 0;
/* info->max_adapter_speed_status = MAX_ADAPTER_NONE; */
} else {
- info->adapter_status = 1;
+ info->adapter_status = 1;
/* get_max_adapter_speed_1(slot_cur->hotplug_slot,
&info->max_adapter_speed_status, 0); */
}
{
struct pci_func *func_cur;
struct slot *slot_cur;
- struct list_head *tmp;
- list_for_each(tmp, &ibmphp_slot_head) {
- slot_cur = list_entry(tmp, struct slot, ibm_slot_list);
+ list_for_each_entry(slot_cur, &ibmphp_slot_head, ibm_slot_list) {
if (slot_cur->func) {
func_cur = slot_cur->func;
while (func_cur) {
*************************************************************/
static void free_slots(void)
{
- struct slot *slot_cur;
- struct list_head *tmp;
- struct list_head *next;
+ struct slot *slot_cur, *next;
debug("%s -- enter\n", __func__);
- list_for_each_safe(tmp, next, &ibmphp_slot_head) {
- slot_cur = list_entry(tmp, struct slot, ibm_slot_list);
+ list_for_each_entry_safe(slot_cur, next, &ibmphp_slot_head,
+ ibm_slot_list) {
pci_hp_deregister(slot_cur->hotplug_slot);
}
debug("%s -- exit\n", __func__);
int retval;
static struct pci_device_id ciobx[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 0x0101) },
- { },
+ { },
};
debug("%s - entry slot # %d\n", __func__, slot_cur->number);
* HOT REMOVING ADAPTER CARD *
* INPUT: POINTER TO THE HOTPLUG SLOT STRUCTURE *
* OUTPUT: SUCCESS 0 ; FAILURE: UNCONFIGURE , VALIDATE *
- DISABLE POWER , *
+* DISABLE POWER , *
**************************************************************/
static int ibmphp_disable_slot(struct hotplug_slot *hotplug_slot)
{
*/
/* Global lists */
-LIST_HEAD (ibmphp_ebda_pci_rsrc_head);
-LIST_HEAD (ibmphp_slot_head);
+LIST_HEAD(ibmphp_ebda_pci_rsrc_head);
+LIST_HEAD(ibmphp_slot_head);
/* Local variables */
static struct ebda_hpc_list *hpc_list_ptr;
static struct ebda_rsrc_list *rsrc_list_ptr;
static struct rio_table_hdr *rio_table_ptr = NULL;
-static LIST_HEAD (ebda_hpc_head);
-static LIST_HEAD (bus_info_head);
-static LIST_HEAD (rio_vg_head);
-static LIST_HEAD (rio_lo_head);
-static LIST_HEAD (opt_vg_head);
-static LIST_HEAD (opt_lo_head);
+static LIST_HEAD(ebda_hpc_head);
+static LIST_HEAD(bus_info_head);
+static LIST_HEAD(rio_vg_head);
+static LIST_HEAD(rio_lo_head);
+static LIST_HEAD(opt_vg_head);
+static LIST_HEAD(opt_lo_head);
static void __iomem *io_mem;
/* Local functions */
-static int ebda_rsrc_controller (void);
-static int ebda_rsrc_rsrc (void);
-static int ebda_rio_table (void);
+static int ebda_rsrc_controller(void);
+static int ebda_rsrc_rsrc(void);
+static int ebda_rio_table(void);
-static struct ebda_hpc_list * __init alloc_ebda_hpc_list (void)
+static struct ebda_hpc_list * __init alloc_ebda_hpc_list(void)
{
return kzalloc(sizeof(struct ebda_hpc_list), GFP_KERNEL);
}
-static struct controller *alloc_ebda_hpc (u32 slot_count, u32 bus_count)
+static struct controller *alloc_ebda_hpc(u32 slot_count, u32 bus_count)
{
struct controller *controller;
struct ebda_hpc_slot *slots;
return NULL;
}
-static void free_ebda_hpc (struct controller *controller)
+static void free_ebda_hpc(struct controller *controller)
{
- kfree (controller->slots);
- kfree (controller->buses);
- kfree (controller);
+ kfree(controller->slots);
+ kfree(controller->buses);
+ kfree(controller);
}
-static struct ebda_rsrc_list * __init alloc_ebda_rsrc_list (void)
+static struct ebda_rsrc_list * __init alloc_ebda_rsrc_list(void)
{
return kzalloc(sizeof(struct ebda_rsrc_list), GFP_KERNEL);
}
-static struct ebda_pci_rsrc *alloc_ebda_pci_rsrc (void)
+static struct ebda_pci_rsrc *alloc_ebda_pci_rsrc(void)
{
return kzalloc(sizeof(struct ebda_pci_rsrc), GFP_KERNEL);
}
-static void __init print_bus_info (void)
+static void __init print_bus_info(void)
{
struct bus_info *ptr;
list_for_each_entry(ptr, &bus_info_head, bus_info_list) {
- debug ("%s - slot_min = %x\n", __func__, ptr->slot_min);
- debug ("%s - slot_max = %x\n", __func__, ptr->slot_max);
- debug ("%s - slot_count = %x\n", __func__, ptr->slot_count);
- debug ("%s - bus# = %x\n", __func__, ptr->busno);
- debug ("%s - current_speed = %x\n", __func__, ptr->current_speed);
- debug ("%s - controller_id = %x\n", __func__, ptr->controller_id);
-
- debug ("%s - slots_at_33_conv = %x\n", __func__, ptr->slots_at_33_conv);
- debug ("%s - slots_at_66_conv = %x\n", __func__, ptr->slots_at_66_conv);
- debug ("%s - slots_at_66_pcix = %x\n", __func__, ptr->slots_at_66_pcix);
- debug ("%s - slots_at_100_pcix = %x\n", __func__, ptr->slots_at_100_pcix);
- debug ("%s - slots_at_133_pcix = %x\n", __func__, ptr->slots_at_133_pcix);
+ debug("%s - slot_min = %x\n", __func__, ptr->slot_min);
+ debug("%s - slot_max = %x\n", __func__, ptr->slot_max);
+ debug("%s - slot_count = %x\n", __func__, ptr->slot_count);
+ debug("%s - bus# = %x\n", __func__, ptr->busno);
+ debug("%s - current_speed = %x\n", __func__, ptr->current_speed);
+ debug("%s - controller_id = %x\n", __func__, ptr->controller_id);
+
+ debug("%s - slots_at_33_conv = %x\n", __func__, ptr->slots_at_33_conv);
+ debug("%s - slots_at_66_conv = %x\n", __func__, ptr->slots_at_66_conv);
+ debug("%s - slots_at_66_pcix = %x\n", __func__, ptr->slots_at_66_pcix);
+ debug("%s - slots_at_100_pcix = %x\n", __func__, ptr->slots_at_100_pcix);
+ debug("%s - slots_at_133_pcix = %x\n", __func__, ptr->slots_at_133_pcix);
}
}
-static void print_lo_info (void)
+static void print_lo_info(void)
{
struct rio_detail *ptr;
- debug ("print_lo_info ----\n");
+ debug("print_lo_info ----\n");
list_for_each_entry(ptr, &rio_lo_head, rio_detail_list) {
- debug ("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id);
- debug ("%s - rio_type = %x\n", __func__, ptr->rio_type);
- debug ("%s - owner_id = %x\n", __func__, ptr->owner_id);
- debug ("%s - first_slot_num = %x\n", __func__, ptr->first_slot_num);
- debug ("%s - wpindex = %x\n", __func__, ptr->wpindex);
- debug ("%s - chassis_num = %x\n", __func__, ptr->chassis_num);
+ debug("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id);
+ debug("%s - rio_type = %x\n", __func__, ptr->rio_type);
+ debug("%s - owner_id = %x\n", __func__, ptr->owner_id);
+ debug("%s - first_slot_num = %x\n", __func__, ptr->first_slot_num);
+ debug("%s - wpindex = %x\n", __func__, ptr->wpindex);
+ debug("%s - chassis_num = %x\n", __func__, ptr->chassis_num);
}
}
-static void print_vg_info (void)
+static void print_vg_info(void)
{
struct rio_detail *ptr;
- debug ("%s ---\n", __func__);
+ debug("%s ---\n", __func__);
list_for_each_entry(ptr, &rio_vg_head, rio_detail_list) {
- debug ("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id);
- debug ("%s - rio_type = %x\n", __func__, ptr->rio_type);
- debug ("%s - owner_id = %x\n", __func__, ptr->owner_id);
- debug ("%s - first_slot_num = %x\n", __func__, ptr->first_slot_num);
- debug ("%s - wpindex = %x\n", __func__, ptr->wpindex);
- debug ("%s - chassis_num = %x\n", __func__, ptr->chassis_num);
+ debug("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id);
+ debug("%s - rio_type = %x\n", __func__, ptr->rio_type);
+ debug("%s - owner_id = %x\n", __func__, ptr->owner_id);
+ debug("%s - first_slot_num = %x\n", __func__, ptr->first_slot_num);
+ debug("%s - wpindex = %x\n", __func__, ptr->wpindex);
+ debug("%s - chassis_num = %x\n", __func__, ptr->chassis_num);
}
}
-static void __init print_ebda_pci_rsrc (void)
+static void __init print_ebda_pci_rsrc(void)
{
struct ebda_pci_rsrc *ptr;
list_for_each_entry(ptr, &ibmphp_ebda_pci_rsrc_head, ebda_pci_rsrc_list) {
- debug ("%s - rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
- __func__, ptr->rsrc_type ,ptr->bus_num, ptr->dev_fun,ptr->start_addr, ptr->end_addr);
+ debug("%s - rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
+ __func__, ptr->rsrc_type, ptr->bus_num, ptr->dev_fun, ptr->start_addr, ptr->end_addr);
}
}
-static void __init print_ibm_slot (void)
+static void __init print_ibm_slot(void)
{
struct slot *ptr;
list_for_each_entry(ptr, &ibmphp_slot_head, ibm_slot_list) {
- debug ("%s - slot_number: %x\n", __func__, ptr->number);
+ debug("%s - slot_number: %x\n", __func__, ptr->number);
}
}
-static void __init print_opt_vg (void)
+static void __init print_opt_vg(void)
{
struct opt_rio *ptr;
- debug ("%s ---\n", __func__);
+ debug("%s ---\n", __func__);
list_for_each_entry(ptr, &opt_vg_head, opt_rio_list) {
- debug ("%s - rio_type %x\n", __func__, ptr->rio_type);
- debug ("%s - chassis_num: %x\n", __func__, ptr->chassis_num);
- debug ("%s - first_slot_num: %x\n", __func__, ptr->first_slot_num);
- debug ("%s - middle_num: %x\n", __func__, ptr->middle_num);
+ debug("%s - rio_type %x\n", __func__, ptr->rio_type);
+ debug("%s - chassis_num: %x\n", __func__, ptr->chassis_num);
+ debug("%s - first_slot_num: %x\n", __func__, ptr->first_slot_num);
+ debug("%s - middle_num: %x\n", __func__, ptr->middle_num);
}
}
-static void __init print_ebda_hpc (void)
+static void __init print_ebda_hpc(void)
{
struct controller *hpc_ptr;
u16 index;
list_for_each_entry(hpc_ptr, &ebda_hpc_head, ebda_hpc_list) {
for (index = 0; index < hpc_ptr->slot_count; index++) {
- debug ("%s - physical slot#: %x\n", __func__, hpc_ptr->slots[index].slot_num);
- debug ("%s - pci bus# of the slot: %x\n", __func__, hpc_ptr->slots[index].slot_bus_num);
- debug ("%s - index into ctlr addr: %x\n", __func__, hpc_ptr->slots[index].ctl_index);
- debug ("%s - cap of the slot: %x\n", __func__, hpc_ptr->slots[index].slot_cap);
+ debug("%s - physical slot#: %x\n", __func__, hpc_ptr->slots[index].slot_num);
+ debug("%s - pci bus# of the slot: %x\n", __func__, hpc_ptr->slots[index].slot_bus_num);
+ debug("%s - index into ctlr addr: %x\n", __func__, hpc_ptr->slots[index].ctl_index);
+ debug("%s - cap of the slot: %x\n", __func__, hpc_ptr->slots[index].slot_cap);
}
for (index = 0; index < hpc_ptr->bus_count; index++)
- debug ("%s - bus# of each bus controlled by this ctlr: %x\n", __func__, hpc_ptr->buses[index].bus_num);
+ debug("%s - bus# of each bus controlled by this ctlr: %x\n", __func__, hpc_ptr->buses[index].bus_num);
- debug ("%s - type of hpc: %x\n", __func__, hpc_ptr->ctlr_type);
+ debug("%s - type of hpc: %x\n", __func__, hpc_ptr->ctlr_type);
switch (hpc_ptr->ctlr_type) {
case 1:
- debug ("%s - bus: %x\n", __func__, hpc_ptr->u.pci_ctlr.bus);
- debug ("%s - dev_fun: %x\n", __func__, hpc_ptr->u.pci_ctlr.dev_fun);
- debug ("%s - irq: %x\n", __func__, hpc_ptr->irq);
+ debug("%s - bus: %x\n", __func__, hpc_ptr->u.pci_ctlr.bus);
+ debug("%s - dev_fun: %x\n", __func__, hpc_ptr->u.pci_ctlr.dev_fun);
+ debug("%s - irq: %x\n", __func__, hpc_ptr->irq);
break;
case 0:
- debug ("%s - io_start: %x\n", __func__, hpc_ptr->u.isa_ctlr.io_start);
- debug ("%s - io_end: %x\n", __func__, hpc_ptr->u.isa_ctlr.io_end);
- debug ("%s - irq: %x\n", __func__, hpc_ptr->irq);
+ debug("%s - io_start: %x\n", __func__, hpc_ptr->u.isa_ctlr.io_start);
+ debug("%s - io_end: %x\n", __func__, hpc_ptr->u.isa_ctlr.io_end);
+ debug("%s - irq: %x\n", __func__, hpc_ptr->irq);
break;
case 2:
case 4:
- debug ("%s - wpegbbar: %lx\n", __func__, hpc_ptr->u.wpeg_ctlr.wpegbbar);
- debug ("%s - i2c_addr: %x\n", __func__, hpc_ptr->u.wpeg_ctlr.i2c_addr);
- debug ("%s - irq: %x\n", __func__, hpc_ptr->irq);
+ debug("%s - wpegbbar: %lx\n", __func__, hpc_ptr->u.wpeg_ctlr.wpegbbar);
+ debug("%s - i2c_addr: %x\n", __func__, hpc_ptr->u.wpeg_ctlr.i2c_addr);
+ debug("%s - irq: %x\n", __func__, hpc_ptr->irq);
break;
}
}
}
-int __init ibmphp_access_ebda (void)
+int __init ibmphp_access_ebda(void)
{
u8 format, num_ctlrs, rio_complete, hs_complete, ebda_sz;
u16 ebda_seg, num_entries, next_offset, offset, blk_id, sub_addr, re, rc_id, re_id, base;
rio_complete = 0;
hs_complete = 0;
- io_mem = ioremap ((0x40 << 4) + 0x0e, 2);
- if (!io_mem )
+ io_mem = ioremap((0x40 << 4) + 0x0e, 2);
+ if (!io_mem)
return -ENOMEM;
- ebda_seg = readw (io_mem);
- iounmap (io_mem);
- debug ("returned ebda segment: %x\n", ebda_seg);
+ ebda_seg = readw(io_mem);
+ iounmap(io_mem);
+ debug("returned ebda segment: %x\n", ebda_seg);
io_mem = ioremap(ebda_seg<<4, 1);
if (!io_mem)
return -ENOMEM;
io_mem = ioremap(ebda_seg<<4, (ebda_sz * 1024));
- if (!io_mem )
+ if (!io_mem)
return -ENOMEM;
next_offset = 0x180;
"ibmphp_ebda: next read is beyond ebda_sz\n"))
break;
- next_offset = readw (io_mem + offset); /* offset of next blk */
+ next_offset = readw(io_mem + offset); /* offset of next blk */
offset += 2;
if (next_offset == 0) /* 0 indicate it's last blk */
break;
- blk_id = readw (io_mem + offset); /* this blk id */
+ blk_id = readw(io_mem + offset); /* this blk id */
offset += 2;
/* check if it is hot swap block or rio block */
continue;
/* found hs table */
if (blk_id == 0x4853) {
- debug ("now enter hot swap block---\n");
- debug ("hot blk id: %x\n", blk_id);
- format = readb (io_mem + offset);
+ debug("now enter hot swap block---\n");
+ debug("hot blk id: %x\n", blk_id);
+ format = readb(io_mem + offset);
offset += 1;
if (format != 4)
goto error_nodev;
- debug ("hot blk format: %x\n", format);
+ debug("hot blk format: %x\n", format);
/* hot swap sub blk */
base = offset;
sub_addr = base;
- re = readw (io_mem + sub_addr); /* next sub blk */
+ re = readw(io_mem + sub_addr); /* next sub blk */
sub_addr += 2;
- rc_id = readw (io_mem + sub_addr); /* sub blk id */
+ rc_id = readw(io_mem + sub_addr); /* sub blk id */
sub_addr += 2;
if (rc_id != 0x5243)
goto error_nodev;
/* rc sub blk signature */
- num_ctlrs = readb (io_mem + sub_addr);
+ num_ctlrs = readb(io_mem + sub_addr);
sub_addr += 1;
- hpc_list_ptr = alloc_ebda_hpc_list ();
+ hpc_list_ptr = alloc_ebda_hpc_list();
if (!hpc_list_ptr) {
rc = -ENOMEM;
goto out;
hpc_list_ptr->format = format;
hpc_list_ptr->num_ctlrs = num_ctlrs;
hpc_list_ptr->phys_addr = sub_addr; /* offset of RSRC_CONTROLLER blk */
- debug ("info about hpc descriptor---\n");
- debug ("hot blk format: %x\n", format);
- debug ("num of controller: %x\n", num_ctlrs);
- debug ("offset of hpc data structure entries: %x\n ", sub_addr);
+ debug("info about hpc descriptor---\n");
+ debug("hot blk format: %x\n", format);
+ debug("num of controller: %x\n", num_ctlrs);
+ debug("offset of hpc data structure entries: %x\n ", sub_addr);
sub_addr = base + re; /* re sub blk */
/* FIXME: rc is never used/checked */
- rc = readw (io_mem + sub_addr); /* next sub blk */
+ rc = readw(io_mem + sub_addr); /* next sub blk */
sub_addr += 2;
- re_id = readw (io_mem + sub_addr); /* sub blk id */
+ re_id = readw(io_mem + sub_addr); /* sub blk id */
sub_addr += 2;
if (re_id != 0x5245)
goto error_nodev;
/* signature of re */
- num_entries = readw (io_mem + sub_addr);
+ num_entries = readw(io_mem + sub_addr);
sub_addr += 2; /* offset of RSRC_ENTRIES blk */
- rsrc_list_ptr = alloc_ebda_rsrc_list ();
- if (!rsrc_list_ptr ) {
+ rsrc_list_ptr = alloc_ebda_rsrc_list();
+ if (!rsrc_list_ptr) {
rc = -ENOMEM;
goto out;
}
rsrc_list_ptr->num_entries = num_entries;
rsrc_list_ptr->phys_addr = sub_addr;
- debug ("info about rsrc descriptor---\n");
- debug ("format: %x\n", format);
- debug ("num of rsrc: %x\n", num_entries);
- debug ("offset of rsrc data structure entries: %x\n ", sub_addr);
+ debug("info about rsrc descriptor---\n");
+ debug("format: %x\n", format);
+ debug("num of rsrc: %x\n", num_entries);
+ debug("offset of rsrc data structure entries: %x\n ", sub_addr);
hs_complete = 1;
} else {
/* found rio table, blk_id == 0x4752 */
- debug ("now enter io table ---\n");
- debug ("rio blk id: %x\n", blk_id);
+ debug("now enter io table ---\n");
+ debug("rio blk id: %x\n", blk_id);
rio_table_ptr = kzalloc(sizeof(struct rio_table_hdr), GFP_KERNEL);
if (!rio_table_ptr) {
rc = -ENOMEM;
goto out;
}
- rio_table_ptr->ver_num = readb (io_mem + offset);
- rio_table_ptr->scal_count = readb (io_mem + offset + 1);
- rio_table_ptr->riodev_count = readb (io_mem + offset + 2);
- rio_table_ptr->offset = offset +3 ;
+ rio_table_ptr->ver_num = readb(io_mem + offset);
+ rio_table_ptr->scal_count = readb(io_mem + offset + 1);
+ rio_table_ptr->riodev_count = readb(io_mem + offset + 2);
+ rio_table_ptr->offset = offset + 3 ;
debug("info about rio table hdr ---\n");
debug("ver_num: %x\nscal_count: %x\nriodev_count: %x\noffset of rio table: %x\n ",
if (rio_table_ptr) {
if (rio_complete && rio_table_ptr->ver_num == 3) {
- rc = ebda_rio_table ();
+ rc = ebda_rio_table();
if (rc)
goto out;
}
}
- rc = ebda_rsrc_controller ();
+ rc = ebda_rsrc_controller();
if (rc)
goto out;
- rc = ebda_rsrc_rsrc ();
+ rc = ebda_rsrc_rsrc();
goto out;
error_nodev:
rc = -ENODEV;
out:
- iounmap (io_mem);
+ iounmap(io_mem);
return rc;
}
/*
* map info of scalability details and rio details from physical address
*/
-static int __init ebda_rio_table (void)
+static int __init ebda_rio_table(void)
{
u16 offset;
u8 i;
rio_detail_ptr = kzalloc(sizeof(struct rio_detail), GFP_KERNEL);
if (!rio_detail_ptr)
return -ENOMEM;
- rio_detail_ptr->rio_node_id = readb (io_mem + offset);
- rio_detail_ptr->bbar = readl (io_mem + offset + 1);
- rio_detail_ptr->rio_type = readb (io_mem + offset + 5);
- rio_detail_ptr->owner_id = readb (io_mem + offset + 6);
- rio_detail_ptr->port0_node_connect = readb (io_mem + offset + 7);
- rio_detail_ptr->port0_port_connect = readb (io_mem + offset + 8);
- rio_detail_ptr->port1_node_connect = readb (io_mem + offset + 9);
- rio_detail_ptr->port1_port_connect = readb (io_mem + offset + 10);
- rio_detail_ptr->first_slot_num = readb (io_mem + offset + 11);
- rio_detail_ptr->status = readb (io_mem + offset + 12);
- rio_detail_ptr->wpindex = readb (io_mem + offset + 13);
- rio_detail_ptr->chassis_num = readb (io_mem + offset + 14);
-// debug ("rio_node_id: %x\nbbar: %x\nrio_type: %x\nowner_id: %x\nport0_node: %x\nport0_port: %x\nport1_node: %x\nport1_port: %x\nfirst_slot_num: %x\nstatus: %x\n", rio_detail_ptr->rio_node_id, rio_detail_ptr->bbar, rio_detail_ptr->rio_type, rio_detail_ptr->owner_id, rio_detail_ptr->port0_node_connect, rio_detail_ptr->port0_port_connect, rio_detail_ptr->port1_node_connect, rio_detail_ptr->port1_port_connect, rio_detail_ptr->first_slot_num, rio_detail_ptr->status);
+ rio_detail_ptr->rio_node_id = readb(io_mem + offset);
+ rio_detail_ptr->bbar = readl(io_mem + offset + 1);
+ rio_detail_ptr->rio_type = readb(io_mem + offset + 5);
+ rio_detail_ptr->owner_id = readb(io_mem + offset + 6);
+ rio_detail_ptr->port0_node_connect = readb(io_mem + offset + 7);
+ rio_detail_ptr->port0_port_connect = readb(io_mem + offset + 8);
+ rio_detail_ptr->port1_node_connect = readb(io_mem + offset + 9);
+ rio_detail_ptr->port1_port_connect = readb(io_mem + offset + 10);
+ rio_detail_ptr->first_slot_num = readb(io_mem + offset + 11);
+ rio_detail_ptr->status = readb(io_mem + offset + 12);
+ rio_detail_ptr->wpindex = readb(io_mem + offset + 13);
+ rio_detail_ptr->chassis_num = readb(io_mem + offset + 14);
+// debug("rio_node_id: %x\nbbar: %x\nrio_type: %x\nowner_id: %x\nport0_node: %x\nport0_port: %x\nport1_node: %x\nport1_port: %x\nfirst_slot_num: %x\nstatus: %x\n", rio_detail_ptr->rio_node_id, rio_detail_ptr->bbar, rio_detail_ptr->rio_type, rio_detail_ptr->owner_id, rio_detail_ptr->port0_node_connect, rio_detail_ptr->port0_port_connect, rio_detail_ptr->port1_node_connect, rio_detail_ptr->port1_port_connect, rio_detail_ptr->first_slot_num, rio_detail_ptr->status);
//create linked list of chassis
if (rio_detail_ptr->rio_type == 4 || rio_detail_ptr->rio_type == 5)
- list_add (&rio_detail_ptr->rio_detail_list, &rio_vg_head);
+ list_add(&rio_detail_ptr->rio_detail_list, &rio_vg_head);
//create linked list of expansion box
else if (rio_detail_ptr->rio_type == 6 || rio_detail_ptr->rio_type == 7)
- list_add (&rio_detail_ptr->rio_detail_list, &rio_lo_head);
+ list_add(&rio_detail_ptr->rio_detail_list, &rio_lo_head);
else
// not in my concern
- kfree (rio_detail_ptr);
+ kfree(rio_detail_ptr);
offset += 15;
}
- print_lo_info ();
- print_vg_info ();
+ print_lo_info();
+ print_vg_info();
return 0;
}
/*
* reorganizing linked list of chassis
*/
-static struct opt_rio *search_opt_vg (u8 chassis_num)
+static struct opt_rio *search_opt_vg(u8 chassis_num)
{
struct opt_rio *ptr;
list_for_each_entry(ptr, &opt_vg_head, opt_rio_list) {
return NULL;
}
-static int __init combine_wpg_for_chassis (void)
+static int __init combine_wpg_for_chassis(void)
{
struct opt_rio *opt_rio_ptr = NULL;
struct rio_detail *rio_detail_ptr = NULL;
list_for_each_entry(rio_detail_ptr, &rio_vg_head, rio_detail_list) {
- opt_rio_ptr = search_opt_vg (rio_detail_ptr->chassis_num);
+ opt_rio_ptr = search_opt_vg(rio_detail_ptr->chassis_num);
if (!opt_rio_ptr) {
opt_rio_ptr = kzalloc(sizeof(struct opt_rio), GFP_KERNEL);
if (!opt_rio_ptr)
opt_rio_ptr->chassis_num = rio_detail_ptr->chassis_num;
opt_rio_ptr->first_slot_num = rio_detail_ptr->first_slot_num;
opt_rio_ptr->middle_num = rio_detail_ptr->first_slot_num;
- list_add (&opt_rio_ptr->opt_rio_list, &opt_vg_head);
+ list_add(&opt_rio_ptr->opt_rio_list, &opt_vg_head);
} else {
- opt_rio_ptr->first_slot_num = min (opt_rio_ptr->first_slot_num, rio_detail_ptr->first_slot_num);
- opt_rio_ptr->middle_num = max (opt_rio_ptr->middle_num, rio_detail_ptr->first_slot_num);
+ opt_rio_ptr->first_slot_num = min(opt_rio_ptr->first_slot_num, rio_detail_ptr->first_slot_num);
+ opt_rio_ptr->middle_num = max(opt_rio_ptr->middle_num, rio_detail_ptr->first_slot_num);
}
}
- print_opt_vg ();
+ print_opt_vg();
return 0;
}
/*
* reorganizing linked list of expansion box
*/
-static struct opt_rio_lo *search_opt_lo (u8 chassis_num)
+static struct opt_rio_lo *search_opt_lo(u8 chassis_num)
{
struct opt_rio_lo *ptr;
list_for_each_entry(ptr, &opt_lo_head, opt_rio_lo_list) {
return NULL;
}
-static int combine_wpg_for_expansion (void)
+static int combine_wpg_for_expansion(void)
{
struct opt_rio_lo *opt_rio_lo_ptr = NULL;
struct rio_detail *rio_detail_ptr = NULL;
list_for_each_entry(rio_detail_ptr, &rio_lo_head, rio_detail_list) {
- opt_rio_lo_ptr = search_opt_lo (rio_detail_ptr->chassis_num);
+ opt_rio_lo_ptr = search_opt_lo(rio_detail_ptr->chassis_num);
if (!opt_rio_lo_ptr) {
opt_rio_lo_ptr = kzalloc(sizeof(struct opt_rio_lo), GFP_KERNEL);
if (!opt_rio_lo_ptr)
opt_rio_lo_ptr->middle_num = rio_detail_ptr->first_slot_num;
opt_rio_lo_ptr->pack_count = 1;
- list_add (&opt_rio_lo_ptr->opt_rio_lo_list, &opt_lo_head);
+ list_add(&opt_rio_lo_ptr->opt_rio_lo_list, &opt_lo_head);
} else {
- opt_rio_lo_ptr->first_slot_num = min (opt_rio_lo_ptr->first_slot_num, rio_detail_ptr->first_slot_num);
- opt_rio_lo_ptr->middle_num = max (opt_rio_lo_ptr->middle_num, rio_detail_ptr->first_slot_num);
+ opt_rio_lo_ptr->first_slot_num = min(opt_rio_lo_ptr->first_slot_num, rio_detail_ptr->first_slot_num);
+ opt_rio_lo_ptr->middle_num = max(opt_rio_lo_ptr->middle_num, rio_detail_ptr->first_slot_num);
opt_rio_lo_ptr->pack_count = 2;
}
}
* Arguments: slot_num, 1st slot number of the chassis we think we are on,
* var (0 = chassis, 1 = expansion box)
*/
-static int first_slot_num (u8 slot_num, u8 first_slot, u8 var)
+static int first_slot_num(u8 slot_num, u8 first_slot, u8 var)
{
struct opt_rio *opt_vg_ptr = NULL;
struct opt_rio_lo *opt_lo_ptr = NULL;
return rc;
}
-static struct opt_rio_lo *find_rxe_num (u8 slot_num)
+static struct opt_rio_lo *find_rxe_num(u8 slot_num)
{
struct opt_rio_lo *opt_lo_ptr;
list_for_each_entry(opt_lo_ptr, &opt_lo_head, opt_rio_lo_list) {
//check to see if this slot_num belongs to expansion box
- if ((slot_num >= opt_lo_ptr->first_slot_num) && (!first_slot_num (slot_num, opt_lo_ptr->first_slot_num, 1)))
+ if ((slot_num >= opt_lo_ptr->first_slot_num) && (!first_slot_num(slot_num, opt_lo_ptr->first_slot_num, 1)))
return opt_lo_ptr;
}
return NULL;
}
-static struct opt_rio *find_chassis_num (u8 slot_num)
+static struct opt_rio *find_chassis_num(u8 slot_num)
{
struct opt_rio *opt_vg_ptr;
list_for_each_entry(opt_vg_ptr, &opt_vg_head, opt_rio_list) {
//check to see if this slot_num belongs to chassis
- if ((slot_num >= opt_vg_ptr->first_slot_num) && (!first_slot_num (slot_num, opt_vg_ptr->first_slot_num, 0)))
+ if ((slot_num >= opt_vg_ptr->first_slot_num) && (!first_slot_num(slot_num, opt_vg_ptr->first_slot_num, 0)))
return opt_vg_ptr;
}
return NULL;
/* This routine will find out how many slots are in the chassis, so that
* the slot numbers for rxe100 would start from 1, and not from 7, or 6 etc
*/
-static u8 calculate_first_slot (u8 slot_num)
+static u8 calculate_first_slot(u8 slot_num)
{
u8 first_slot = 1;
struct slot *slot_cur;
#define SLOT_NAME_SIZE 30
-static char *create_file_name (struct slot *slot_cur)
+static char *create_file_name(struct slot *slot_cur)
{
struct opt_rio *opt_vg_ptr = NULL;
struct opt_rio_lo *opt_lo_ptr = NULL;
u8 flag = 0;
if (!slot_cur) {
- err ("Structure passed is empty\n");
+ err("Structure passed is empty\n");
return NULL;
}
slot_num = slot_cur->number;
- memset (str, 0, sizeof(str));
+ memset(str, 0, sizeof(str));
if (rio_table_ptr) {
if (rio_table_ptr->ver_num == 3) {
- opt_vg_ptr = find_chassis_num (slot_num);
- opt_lo_ptr = find_rxe_num (slot_num);
+ opt_vg_ptr = find_chassis_num(slot_num);
+ opt_lo_ptr = find_rxe_num(slot_num);
}
}
if (opt_vg_ptr) {
}
if (!flag) {
if (slot_cur->ctrl->ctlr_type == 4) {
- first_slot = calculate_first_slot (slot_num);
+ first_slot = calculate_first_slot(slot_num);
which = 1;
} else {
which = 0;
hotplug_slot->info->latch_status = SLOT_LATCH(slot->status);
// pci board - present:1 not:0
- if (SLOT_PRESENT (slot->status))
+ if (SLOT_PRESENT(slot->status))
hotplug_slot->info->adapter_status = 1;
else
hotplug_slot->info->adapter_status = 0;
/* we don't want to actually remove the resources, since free_resources will do just that */
ibmphp_unconfigure_card(&slot, -1);
- kfree (slot);
+ kfree(slot);
}
static struct pci_driver ibmphp_driver;
* each hpc from physical address to a list of hot plug controllers based on
* hpc descriptors.
*/
-static int __init ebda_rsrc_controller (void)
+static int __init ebda_rsrc_controller(void)
{
u16 addr, addr_slot, addr_bus;
u8 ctlr_id, temp, bus_index;
addr = hpc_list_ptr->phys_addr;
for (ctlr = 0; ctlr < hpc_list_ptr->num_ctlrs; ctlr++) {
bus_index = 1;
- ctlr_id = readb (io_mem + addr);
+ ctlr_id = readb(io_mem + addr);
addr += 1;
- slot_num = readb (io_mem + addr);
+ slot_num = readb(io_mem + addr);
addr += 1;
addr_slot = addr; /* offset of slot structure */
addr += (slot_num * 4);
- bus_num = readb (io_mem + addr);
+ bus_num = readb(io_mem + addr);
addr += 1;
addr_bus = addr; /* offset of bus */
addr += (bus_num * 9); /* offset of ctlr_type */
- temp = readb (io_mem + addr);
+ temp = readb(io_mem + addr);
addr += 1;
/* init hpc structure */
- hpc_ptr = alloc_ebda_hpc (slot_num, bus_num);
- if (!hpc_ptr ) {
+ hpc_ptr = alloc_ebda_hpc(slot_num, bus_num);
+ if (!hpc_ptr) {
rc = -ENOMEM;
goto error_no_hpc;
}
hpc_ptr->ctlr_relative_id = ctlr;
hpc_ptr->slot_count = slot_num;
hpc_ptr->bus_count = bus_num;
- debug ("now enter ctlr data structure ---\n");
- debug ("ctlr id: %x\n", ctlr_id);
- debug ("ctlr_relative_id: %x\n", hpc_ptr->ctlr_relative_id);
- debug ("count of slots controlled by this ctlr: %x\n", slot_num);
- debug ("count of buses controlled by this ctlr: %x\n", bus_num);
+ debug("now enter ctlr data structure ---\n");
+ debug("ctlr id: %x\n", ctlr_id);
+ debug("ctlr_relative_id: %x\n", hpc_ptr->ctlr_relative_id);
+ debug("count of slots controlled by this ctlr: %x\n", slot_num);
+ debug("count of buses controlled by this ctlr: %x\n", bus_num);
/* init slot structure, fetch slot, bus, cap... */
slot_ptr = hpc_ptr->slots;
for (slot = 0; slot < slot_num; slot++) {
- slot_ptr->slot_num = readb (io_mem + addr_slot);
- slot_ptr->slot_bus_num = readb (io_mem + addr_slot + slot_num);
- slot_ptr->ctl_index = readb (io_mem + addr_slot + 2*slot_num);
- slot_ptr->slot_cap = readb (io_mem + addr_slot + 3*slot_num);
+ slot_ptr->slot_num = readb(io_mem + addr_slot);
+ slot_ptr->slot_bus_num = readb(io_mem + addr_slot + slot_num);
+ slot_ptr->ctl_index = readb(io_mem + addr_slot + 2*slot_num);
+ slot_ptr->slot_cap = readb(io_mem + addr_slot + 3*slot_num);
// create bus_info lined list --- if only one slot per bus: slot_min = slot_max
- bus_info_ptr2 = ibmphp_find_same_bus_num (slot_ptr->slot_bus_num);
+ bus_info_ptr2 = ibmphp_find_same_bus_num(slot_ptr->slot_bus_num);
if (!bus_info_ptr2) {
bus_info_ptr1 = kzalloc(sizeof(struct bus_info), GFP_KERNEL);
if (!bus_info_ptr1) {
bus_info_ptr1->controller_id = hpc_ptr->ctlr_id;
- list_add_tail (&bus_info_ptr1->bus_info_list, &bus_info_head);
+ list_add_tail(&bus_info_ptr1->bus_info_list, &bus_info_head);
} else {
- bus_info_ptr2->slot_min = min (bus_info_ptr2->slot_min, slot_ptr->slot_num);
- bus_info_ptr2->slot_max = max (bus_info_ptr2->slot_max, slot_ptr->slot_num);
+ bus_info_ptr2->slot_min = min(bus_info_ptr2->slot_min, slot_ptr->slot_num);
+ bus_info_ptr2->slot_max = max(bus_info_ptr2->slot_max, slot_ptr->slot_num);
bus_info_ptr2->slot_count += 1;
}
/* init bus structure */
bus_ptr = hpc_ptr->buses;
for (bus = 0; bus < bus_num; bus++) {
- bus_ptr->bus_num = readb (io_mem + addr_bus + bus);
- bus_ptr->slots_at_33_conv = readb (io_mem + addr_bus + bus_num + 8 * bus);
- bus_ptr->slots_at_66_conv = readb (io_mem + addr_bus + bus_num + 8 * bus + 1);
+ bus_ptr->bus_num = readb(io_mem + addr_bus + bus);
+ bus_ptr->slots_at_33_conv = readb(io_mem + addr_bus + bus_num + 8 * bus);
+ bus_ptr->slots_at_66_conv = readb(io_mem + addr_bus + bus_num + 8 * bus + 1);
- bus_ptr->slots_at_66_pcix = readb (io_mem + addr_bus + bus_num + 8 * bus + 2);
+ bus_ptr->slots_at_66_pcix = readb(io_mem + addr_bus + bus_num + 8 * bus + 2);
- bus_ptr->slots_at_100_pcix = readb (io_mem + addr_bus + bus_num + 8 * bus + 3);
+ bus_ptr->slots_at_100_pcix = readb(io_mem + addr_bus + bus_num + 8 * bus + 3);
- bus_ptr->slots_at_133_pcix = readb (io_mem + addr_bus + bus_num + 8 * bus + 4);
+ bus_ptr->slots_at_133_pcix = readb(io_mem + addr_bus + bus_num + 8 * bus + 4);
- bus_info_ptr2 = ibmphp_find_same_bus_num (bus_ptr->bus_num);
+ bus_info_ptr2 = ibmphp_find_same_bus_num(bus_ptr->bus_num);
if (bus_info_ptr2) {
bus_info_ptr2->slots_at_33_conv = bus_ptr->slots_at_33_conv;
bus_info_ptr2->slots_at_66_conv = bus_ptr->slots_at_66_conv;
switch (hpc_ptr->ctlr_type) {
case 1:
- hpc_ptr->u.pci_ctlr.bus = readb (io_mem + addr);
- hpc_ptr->u.pci_ctlr.dev_fun = readb (io_mem + addr + 1);
- hpc_ptr->irq = readb (io_mem + addr + 2);
+ hpc_ptr->u.pci_ctlr.bus = readb(io_mem + addr);
+ hpc_ptr->u.pci_ctlr.dev_fun = readb(io_mem + addr + 1);
+ hpc_ptr->irq = readb(io_mem + addr + 2);
addr += 3;
- debug ("ctrl bus = %x, ctlr devfun = %x, irq = %x\n",
+ debug("ctrl bus = %x, ctlr devfun = %x, irq = %x\n",
hpc_ptr->u.pci_ctlr.bus,
hpc_ptr->u.pci_ctlr.dev_fun, hpc_ptr->irq);
break;
case 0:
- hpc_ptr->u.isa_ctlr.io_start = readw (io_mem + addr);
- hpc_ptr->u.isa_ctlr.io_end = readw (io_mem + addr + 2);
- if (!request_region (hpc_ptr->u.isa_ctlr.io_start,
+ hpc_ptr->u.isa_ctlr.io_start = readw(io_mem + addr);
+ hpc_ptr->u.isa_ctlr.io_end = readw(io_mem + addr + 2);
+ if (!request_region(hpc_ptr->u.isa_ctlr.io_start,
(hpc_ptr->u.isa_ctlr.io_end - hpc_ptr->u.isa_ctlr.io_start + 1),
"ibmphp")) {
rc = -ENODEV;
goto error_no_hp_slot;
}
- hpc_ptr->irq = readb (io_mem + addr + 4);
+ hpc_ptr->irq = readb(io_mem + addr + 4);
addr += 5;
break;
case 2:
case 4:
- hpc_ptr->u.wpeg_ctlr.wpegbbar = readl (io_mem + addr);
- hpc_ptr->u.wpeg_ctlr.i2c_addr = readb (io_mem + addr + 4);
- hpc_ptr->irq = readb (io_mem + addr + 5);
+ hpc_ptr->u.wpeg_ctlr.wpegbbar = readl(io_mem + addr);
+ hpc_ptr->u.wpeg_ctlr.i2c_addr = readb(io_mem + addr + 4);
+ hpc_ptr->irq = readb(io_mem + addr + 5);
addr += 6;
break;
default:
}
//reorganize chassis' linked list
- combine_wpg_for_chassis ();
- combine_wpg_for_expansion ();
+ combine_wpg_for_chassis();
+ combine_wpg_for_expansion();
hpc_ptr->revision = 0xff;
hpc_ptr->options = 0xff;
hpc_ptr->starting_slot_num = hpc_ptr->slots[0].slot_num;
tmp_slot->bus = hpc_ptr->slots[index].slot_bus_num;
- bus_info_ptr1 = ibmphp_find_same_bus_num (hpc_ptr->slots[index].slot_bus_num);
+ bus_info_ptr1 = ibmphp_find_same_bus_num(hpc_ptr->slots[index].slot_bus_num);
if (!bus_info_ptr1) {
kfree(tmp_slot);
rc = -ENODEV;
if (rc)
goto error;
- rc = ibmphp_init_devno ((struct slot **) &hp_slot_ptr->private);
+ rc = ibmphp_init_devno((struct slot **) &hp_slot_ptr->private);
if (rc)
goto error;
hp_slot_ptr->ops = &ibmphp_hotplug_slot_ops;
// end of registering ibm slot with hotplug core
- list_add (& ((struct slot *)(hp_slot_ptr->private))->ibm_slot_list, &ibmphp_slot_head);
+ list_add(&((struct slot *)(hp_slot_ptr->private))->ibm_slot_list, &ibmphp_slot_head);
}
- print_bus_info ();
- list_add (&hpc_ptr->ebda_hpc_list, &ebda_hpc_head );
+ print_bus_info();
+ list_add(&hpc_ptr->ebda_hpc_list, &ebda_hpc_head);
} /* each hpc */
pci_find_bus(0, tmp_slot->bus), tmp_slot->device, name);
}
- print_ebda_hpc ();
- print_ibm_slot ();
+ print_ebda_hpc();
+ print_ibm_slot();
return 0;
error:
- kfree (hp_slot_ptr->private);
+ kfree(hp_slot_ptr->private);
error_no_slot:
- kfree (hp_slot_ptr->info);
+ kfree(hp_slot_ptr->info);
error_no_hp_info:
- kfree (hp_slot_ptr);
+ kfree(hp_slot_ptr);
error_no_hp_slot:
- free_ebda_hpc (hpc_ptr);
+ free_ebda_hpc(hpc_ptr);
error_no_hpc:
- iounmap (io_mem);
+ iounmap(io_mem);
return rc;
}
* map info (bus, devfun, start addr, end addr..) of i/o, memory,
* pfm from the physical addr to a list of resource.
*/
-static int __init ebda_rsrc_rsrc (void)
+static int __init ebda_rsrc_rsrc(void)
{
u16 addr;
short rsrc;
struct ebda_pci_rsrc *rsrc_ptr;
addr = rsrc_list_ptr->phys_addr;
- debug ("now entering rsrc land\n");
- debug ("offset of rsrc: %x\n", rsrc_list_ptr->phys_addr);
+ debug("now entering rsrc land\n");
+ debug("offset of rsrc: %x\n", rsrc_list_ptr->phys_addr);
for (rsrc = 0; rsrc < rsrc_list_ptr->num_entries; rsrc++) {
- type = readb (io_mem + addr);
+ type = readb(io_mem + addr);
addr += 1;
rsrc_type = type & EBDA_RSRC_TYPE_MASK;
if (rsrc_type == EBDA_IO_RSRC_TYPE) {
- rsrc_ptr = alloc_ebda_pci_rsrc ();
+ rsrc_ptr = alloc_ebda_pci_rsrc();
if (!rsrc_ptr) {
- iounmap (io_mem);
+ iounmap(io_mem);
return -ENOMEM;
}
rsrc_ptr->rsrc_type = type;
- rsrc_ptr->bus_num = readb (io_mem + addr);
- rsrc_ptr->dev_fun = readb (io_mem + addr + 1);
- rsrc_ptr->start_addr = readw (io_mem + addr + 2);
- rsrc_ptr->end_addr = readw (io_mem + addr + 4);
+ rsrc_ptr->bus_num = readb(io_mem + addr);
+ rsrc_ptr->dev_fun = readb(io_mem + addr + 1);
+ rsrc_ptr->start_addr = readw(io_mem + addr + 2);
+ rsrc_ptr->end_addr = readw(io_mem + addr + 4);
addr += 6;
- debug ("rsrc from io type ----\n");
- debug ("rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
+ debug("rsrc from io type ----\n");
+ debug("rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
rsrc_ptr->rsrc_type, rsrc_ptr->bus_num, rsrc_ptr->dev_fun, rsrc_ptr->start_addr, rsrc_ptr->end_addr);
- list_add (&rsrc_ptr->ebda_pci_rsrc_list, &ibmphp_ebda_pci_rsrc_head);
+ list_add(&rsrc_ptr->ebda_pci_rsrc_list, &ibmphp_ebda_pci_rsrc_head);
}
if (rsrc_type == EBDA_MEM_RSRC_TYPE || rsrc_type == EBDA_PFM_RSRC_TYPE) {
- rsrc_ptr = alloc_ebda_pci_rsrc ();
- if (!rsrc_ptr ) {
- iounmap (io_mem);
+ rsrc_ptr = alloc_ebda_pci_rsrc();
+ if (!rsrc_ptr) {
+ iounmap(io_mem);
return -ENOMEM;
}
rsrc_ptr->rsrc_type = type;
- rsrc_ptr->bus_num = readb (io_mem + addr);
- rsrc_ptr->dev_fun = readb (io_mem + addr + 1);
- rsrc_ptr->start_addr = readl (io_mem + addr + 2);
- rsrc_ptr->end_addr = readl (io_mem + addr + 6);
+ rsrc_ptr->bus_num = readb(io_mem + addr);
+ rsrc_ptr->dev_fun = readb(io_mem + addr + 1);
+ rsrc_ptr->start_addr = readl(io_mem + addr + 2);
+ rsrc_ptr->end_addr = readl(io_mem + addr + 6);
addr += 10;
- debug ("rsrc from mem or pfm ---\n");
- debug ("rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
+ debug("rsrc from mem or pfm ---\n");
+ debug("rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
rsrc_ptr->rsrc_type, rsrc_ptr->bus_num, rsrc_ptr->dev_fun, rsrc_ptr->start_addr, rsrc_ptr->end_addr);
- list_add (&rsrc_ptr->ebda_pci_rsrc_list, &ibmphp_ebda_pci_rsrc_head);
+ list_add(&rsrc_ptr->ebda_pci_rsrc_list, &ibmphp_ebda_pci_rsrc_head);
}
}
- kfree (rsrc_list_ptr);
+ kfree(rsrc_list_ptr);
rsrc_list_ptr = NULL;
- print_ebda_pci_rsrc ();
+ print_ebda_pci_rsrc();
return 0;
}
-u16 ibmphp_get_total_controllers (void)
+u16 ibmphp_get_total_controllers(void)
{
return hpc_list_ptr->num_ctlrs;
}
-struct slot *ibmphp_get_slot_from_physical_num (u8 physical_num)
+struct slot *ibmphp_get_slot_from_physical_num(u8 physical_num)
{
struct slot *slot;
* - the total number of the slots based on each bus
* (if only one slot per bus slot_min = slot_max )
*/
-struct bus_info *ibmphp_find_same_bus_num (u32 num)
+struct bus_info *ibmphp_find_same_bus_num(u32 num)
{
struct bus_info *ptr;
/* Finding relative bus number, in order to map corresponding
* bus register
*/
-int ibmphp_get_bus_index (u8 num)
+int ibmphp_get_bus_index(u8 num)
{
struct bus_info *ptr;
return -ENODEV;
}
-void ibmphp_free_bus_info_queue (void)
+void ibmphp_free_bus_info_queue(void)
{
- struct bus_info *bus_info;
- struct list_head *list;
- struct list_head *next;
+ struct bus_info *bus_info, *next;
- list_for_each_safe (list, next, &bus_info_head ) {
- bus_info = list_entry (list, struct bus_info, bus_info_list);
+ list_for_each_entry_safe(bus_info, next, &bus_info_head,
+ bus_info_list) {
kfree (bus_info);
}
}
-void ibmphp_free_ebda_hpc_queue (void)
+void ibmphp_free_ebda_hpc_queue(void)
{
- struct controller *controller = NULL;
- struct list_head *list;
- struct list_head *next;
+ struct controller *controller = NULL, *next;
int pci_flag = 0;
- list_for_each_safe (list, next, &ebda_hpc_head) {
- controller = list_entry (list, struct controller, ebda_hpc_list);
+ list_for_each_entry_safe(controller, next, &ebda_hpc_head,
+ ebda_hpc_list) {
if (controller->ctlr_type == 0)
- release_region (controller->u.isa_ctlr.io_start, (controller->u.isa_ctlr.io_end - controller->u.isa_ctlr.io_start + 1));
+ release_region(controller->u.isa_ctlr.io_start, (controller->u.isa_ctlr.io_end - controller->u.isa_ctlr.io_start + 1));
else if ((controller->ctlr_type == 1) && (!pci_flag)) {
++pci_flag;
- pci_unregister_driver (&ibmphp_driver);
+ pci_unregister_driver(&ibmphp_driver);
}
- free_ebda_hpc (controller);
+ free_ebda_hpc(controller);
}
}
-void ibmphp_free_ebda_pci_rsrc_queue (void)
+void ibmphp_free_ebda_pci_rsrc_queue(void)
{
- struct ebda_pci_rsrc *resource;
- struct list_head *list;
- struct list_head *next;
+ struct ebda_pci_rsrc *resource, *next;
- list_for_each_safe (list, next, &ibmphp_ebda_pci_rsrc_head) {
- resource = list_entry (list, struct ebda_pci_rsrc, ebda_pci_rsrc_list);
+ list_for_each_entry_safe(resource, next, &ibmphp_ebda_pci_rsrc_head,
+ ebda_pci_rsrc_list) {
kfree (resource);
resource = NULL;
}
MODULE_DEVICE_TABLE(pci, id_table);
-static int ibmphp_probe (struct pci_dev *, const struct pci_device_id *);
+static int ibmphp_probe(struct pci_dev *, const struct pci_device_id *);
static struct pci_driver ibmphp_driver = {
.name = "ibmphp",
.id_table = id_table,
.probe = ibmphp_probe,
};
-int ibmphp_register_pci (void)
+int ibmphp_register_pci(void)
{
struct controller *ctrl;
int rc = 0;
}
return rc;
}
-static int ibmphp_probe (struct pci_dev *dev, const struct pci_device_id *ids)
+static int ibmphp_probe(struct pci_dev *dev, const struct pci_device_id *ids)
{
struct controller *ctrl;
- debug ("inside ibmphp_probe\n");
+ debug("inside ibmphp_probe\n");
list_for_each_entry(ctrl, &ebda_hpc_head, ebda_hpc_list) {
if (ctrl->ctlr_type == 1) {
if ((dev->devfn == ctrl->u.pci_ctlr.dev_fun) && (dev->bus->number == ctrl->u.pci_ctlr.bus)) {
ctrl->ctrl_dev = dev;
- debug ("found device!!!\n");
- debug ("dev->device = %x, dev->subsystem_device = %x\n", dev->device, dev->subsystem_device);
+ debug("found device!!!\n");
+ debug("dev->device = %x, dev->subsystem_device = %x\n", dev->device, dev->subsystem_device);
return 0;
}
}
#include "ibmphp.h"
static int to_debug = 0;
-#define debug_polling(fmt, arg...) do { if (to_debug) debug (fmt, arg); } while (0)
+#define debug_polling(fmt, arg...) do { if (to_debug) debug(fmt, arg); } while (0)
//----------------------------------------------------------------------------
// timeout values
//----------------------------------------------------------------------------
// local function prototypes
//----------------------------------------------------------------------------
-static u8 i2c_ctrl_read (struct controller *, void __iomem *, u8);
-static u8 i2c_ctrl_write (struct controller *, void __iomem *, u8, u8);
-static u8 hpc_writecmdtoindex (u8, u8);
-static u8 hpc_readcmdtoindex (u8, u8);
-static void get_hpc_access (void);
-static void free_hpc_access (void);
+static u8 i2c_ctrl_read(struct controller *, void __iomem *, u8);
+static u8 i2c_ctrl_write(struct controller *, void __iomem *, u8, u8);
+static u8 hpc_writecmdtoindex(u8, u8);
+static u8 hpc_readcmdtoindex(u8, u8);
+static void get_hpc_access(void);
+static void free_hpc_access(void);
static int poll_hpc(void *data);
-static int process_changeinstatus (struct slot *, struct slot *);
-static int process_changeinlatch (u8, u8, struct controller *);
-static int hpc_wait_ctlr_notworking (int, struct controller *, void __iomem *, u8 *);
+static int process_changeinstatus(struct slot *, struct slot *);
+static int process_changeinlatch(u8, u8, struct controller *);
+static int hpc_wait_ctlr_notworking(int, struct controller *, void __iomem *, u8 *);
//----------------------------------------------------------------------------
*
* Action: initialize semaphores and variables
*---------------------------------------------------------------------*/
-void __init ibmphp_hpc_initvars (void)
+void __init ibmphp_hpc_initvars(void)
{
- debug ("%s - Entry\n", __func__);
+ debug("%s - Entry\n", __func__);
mutex_init(&sem_hpcaccess);
sema_init(&semOperations, 1);
sema_init(&sem_exit, 0);
to_debug = 0;
- debug ("%s - Exit\n", __func__);
+ debug("%s - Exit\n", __func__);
}
/*----------------------------------------------------------------------
* Action: read from HPC over I2C
*
*---------------------------------------------------------------------*/
-static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index)
+static u8 i2c_ctrl_read(struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index)
{
u8 status;
int i;
unsigned long ultemp;
unsigned long data; // actual data HILO format
- debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index);
+ debug_polling("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index);
//--------------------------------------------------------------------
// READ - step 1
ultemp = ultemp << 8;
data |= ultemp;
} else {
- err ("this controller type is not supported \n");
+ err("this controller type is not supported \n");
return HPC_ERROR;
}
- wpg_data = swab32 (data); // swap data before writing
+ wpg_data = swab32(data); // swap data before writing
wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
- writel (wpg_data, wpg_addr);
+ writel(wpg_data, wpg_addr);
//--------------------------------------------------------------------
// READ - step 2 : clear the message buffer
data = 0x00000000;
- wpg_data = swab32 (data);
+ wpg_data = swab32(data);
wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
- writel (wpg_data, wpg_addr);
+ writel(wpg_data, wpg_addr);
//--------------------------------------------------------------------
// READ - step 3 : issue start operation, I2C master control bit 30:ON
// 2020 : [20] OR operation at [20] offset 0x20
data = WPG_I2CMCNTL_STARTOP_MASK;
- wpg_data = swab32 (data);
+ wpg_data = swab32(data);
wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
- writel (wpg_data, wpg_addr);
+ writel(wpg_data, wpg_addr);
//--------------------------------------------------------------------
// READ - step 4 : wait until start operation bit clears
while (i) {
msleep(10);
wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
- wpg_data = readl (wpg_addr);
- data = swab32 (wpg_data);
+ wpg_data = readl(wpg_addr);
+ data = swab32(wpg_data);
if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
break;
i--;
}
if (i == 0) {
- debug ("%s - Error : WPG timeout\n", __func__);
+ debug("%s - Error : WPG timeout\n", __func__);
return HPC_ERROR;
}
//--------------------------------------------------------------------
while (i) {
msleep(10);
wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
- wpg_data = readl (wpg_addr);
- data = swab32 (wpg_data);
- if (HPC_I2CSTATUS_CHECK (data))
+ wpg_data = readl(wpg_addr);
+ data = swab32(wpg_data);
+ if (HPC_I2CSTATUS_CHECK(data))
break;
i--;
}
if (i == 0) {
- debug ("ctrl_read - Exit Error:I2C timeout\n");
+ debug("ctrl_read - Exit Error:I2C timeout\n");
return HPC_ERROR;
}
//--------------------------------------------------------------------
// READ - step 6 : get DATA
wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
- wpg_data = readl (wpg_addr);
- data = swab32 (wpg_data);
+ wpg_data = readl(wpg_addr);
+ data = swab32(wpg_data);
status = (u8) data;
- debug_polling ("%s - Exit index[%x] status[%x]\n", __func__, index, status);
+ debug_polling("%s - Exit index[%x] status[%x]\n", __func__, index, status);
return (status);
}
*
* Return 0 or error codes
*---------------------------------------------------------------------*/
-static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd)
+static u8 i2c_ctrl_write(struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd)
{
u8 rc;
void __iomem *wpg_addr; // base addr + offset
unsigned long data; // actual data HILO format
int i;
- debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd);
+ debug_polling("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd);
rc = 0;
//--------------------------------------------------------------------
ultemp = ultemp << 8;
data |= ultemp;
} else {
- err ("this controller type is not supported \n");
+ err("this controller type is not supported \n");
return HPC_ERROR;
}
- wpg_data = swab32 (data); // swap data before writing
+ wpg_data = swab32(data); // swap data before writing
wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
- writel (wpg_data, wpg_addr);
+ writel(wpg_data, wpg_addr);
//--------------------------------------------------------------------
// WRITE - step 2 : clear the message buffer
data = 0x00000000 | (unsigned long)cmd;
- wpg_data = swab32 (data);
+ wpg_data = swab32(data);
wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
- writel (wpg_data, wpg_addr);
+ writel(wpg_data, wpg_addr);
//--------------------------------------------------------------------
// WRITE - step 3 : issue start operation,I2C master control bit 30:ON
// 2020 : [20] OR operation at [20] offset 0x20
data = WPG_I2CMCNTL_STARTOP_MASK;
- wpg_data = swab32 (data);
+ wpg_data = swab32(data);
wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
- writel (wpg_data, wpg_addr);
+ writel(wpg_data, wpg_addr);
//--------------------------------------------------------------------
// WRITE - step 4 : wait until start operation bit clears
while (i) {
msleep(10);
wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
- wpg_data = readl (wpg_addr);
- data = swab32 (wpg_data);
+ wpg_data = readl(wpg_addr);
+ data = swab32(wpg_data);
if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
break;
i--;
}
if (i == 0) {
- debug ("%s - Exit Error:WPG timeout\n", __func__);
+ debug("%s - Exit Error:WPG timeout\n", __func__);
rc = HPC_ERROR;
}
while (i) {
msleep(10);
wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
- wpg_data = readl (wpg_addr);
- data = swab32 (wpg_data);
- if (HPC_I2CSTATUS_CHECK (data))
+ wpg_data = readl(wpg_addr);
+ data = swab32(wpg_data);
+ if (HPC_I2CSTATUS_CHECK(data))
break;
i--;
}
if (i == 0) {
- debug ("ctrl_read - Error : I2C timeout\n");
+ debug("ctrl_read - Error : I2C timeout\n");
rc = HPC_ERROR;
}
- debug_polling ("%s Exit rc[%x]\n", __func__, rc);
+ debug_polling("%s Exit rc[%x]\n", __func__, rc);
return (rc);
}
//------------------------------------------------------------
// Read from ISA type HPC
//------------------------------------------------------------
-static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset)
+static u8 isa_ctrl_read(struct controller *ctlr_ptr, u8 offset)
{
u16 start_address;
u16 end_address;
start_address = ctlr_ptr->u.isa_ctlr.io_start;
end_address = ctlr_ptr->u.isa_ctlr.io_end;
- data = inb (start_address + offset);
+ data = inb(start_address + offset);
return data;
}
//--------------------------------------------------------------
// Write to ISA type HPC
//--------------------------------------------------------------
-static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data)
+static void isa_ctrl_write(struct controller *ctlr_ptr, u8 offset, u8 data)
{
u16 start_address;
u16 port_address;
start_address = ctlr_ptr->u.isa_ctlr.io_start;
port_address = start_address + (u16) offset;
- outb (data, port_address);
+ outb(data, port_address);
}
-static u8 pci_ctrl_read (struct controller *ctrl, u8 offset)
+static u8 pci_ctrl_read(struct controller *ctrl, u8 offset)
{
u8 data = 0x00;
- debug ("inside pci_ctrl_read\n");
+ debug("inside pci_ctrl_read\n");
if (ctrl->ctrl_dev)
- pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data);
+ pci_read_config_byte(ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data);
return data;
}
-static u8 pci_ctrl_write (struct controller *ctrl, u8 offset, u8 data)
+static u8 pci_ctrl_write(struct controller *ctrl, u8 offset, u8 data)
{
u8 rc = -ENODEV;
- debug ("inside pci_ctrl_write\n");
+ debug("inside pci_ctrl_write\n");
if (ctrl->ctrl_dev) {
- pci_write_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data);
+ pci_write_config_byte(ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data);
rc = 0;
}
return rc;
}
-static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset)
+static u8 ctrl_read(struct controller *ctlr, void __iomem *base, u8 offset)
{
u8 rc;
switch (ctlr->ctlr_type) {
case 0:
- rc = isa_ctrl_read (ctlr, offset);
+ rc = isa_ctrl_read(ctlr, offset);
break;
case 1:
- rc = pci_ctrl_read (ctlr, offset);
+ rc = pci_ctrl_read(ctlr, offset);
break;
case 2:
case 4:
- rc = i2c_ctrl_read (ctlr, base, offset);
+ rc = i2c_ctrl_read(ctlr, base, offset);
break;
default:
return -ENODEV;
return rc;
}
-static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 data)
+static u8 ctrl_write(struct controller *ctlr, void __iomem *base, u8 offset, u8 data)
{
u8 rc = 0;
switch (ctlr->ctlr_type) {
isa_ctrl_write(ctlr, offset, data);
break;
case 1:
- rc = pci_ctrl_write (ctlr, offset, data);
+ rc = pci_ctrl_write(ctlr, offset, data);
break;
case 2:
case 4:
*
* Return index, HPC_ERROR
*---------------------------------------------------------------------*/
-static u8 hpc_writecmdtoindex (u8 cmd, u8 index)
+static u8 hpc_writecmdtoindex(u8 cmd, u8 index)
{
u8 rc;
break;
default:
- err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd);
+ err("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd);
rc = HPC_ERROR;
}
*
* Return index, HPC_ERROR
*---------------------------------------------------------------------*/
-static u8 hpc_readcmdtoindex (u8 cmd, u8 index)
+static u8 hpc_readcmdtoindex(u8 cmd, u8 index)
{
u8 rc;
*
* Return 0 or error codes
*---------------------------------------------------------------------*/
-int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus)
+int ibmphp_hpc_readslot(struct slot *pslot, u8 cmd, u8 *pstatus)
{
void __iomem *wpg_bbar = NULL;
struct controller *ctlr_ptr;
- struct list_head *pslotlist;
u8 index, status;
int rc = 0;
int busindex;
- debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus);
+ debug_polling("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus);
if ((pslot == NULL)
|| ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) {
rc = -EINVAL;
- err ("%s - Error invalid pointer, rc[%d]\n", __func__, rc);
+ err("%s - Error invalid pointer, rc[%d]\n", __func__, rc);
return rc;
}
if (cmd == READ_BUSSTATUS) {
- busindex = ibmphp_get_bus_index (pslot->bus);
+ busindex = ibmphp_get_bus_index(pslot->bus);
if (busindex < 0) {
rc = -EINVAL;
- err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
+ err("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
return rc;
} else
index = (u8) busindex;
} else
index = pslot->ctlr_index;
- index = hpc_readcmdtoindex (cmd, index);
+ index = hpc_readcmdtoindex(cmd, index);
if (index == HPC_ERROR) {
rc = -EINVAL;
- err ("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc);
+ err("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc);
return rc;
}
ctlr_ptr = pslot->ctrl;
- get_hpc_access ();
+ get_hpc_access();
//--------------------------------------------------------------------
// map physical address to logical address
//--------------------------------------------------------------------
if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
- wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
+ wpg_bbar = ioremap(ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
//--------------------------------------------------------------------
// check controller status before reading
//--------------------------------------------------------------------
- rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
+ rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
if (!rc) {
switch (cmd) {
case READ_ALLSTAT:
// update the slot structure
pslot->ctrl->status = status;
- pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index);
- rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
+ pslot->status = ctrl_read(ctlr_ptr, wpg_bbar, index);
+ rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
&status);
if (!rc)
- pslot->ext_status = ctrl_read (ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX);
+ pslot->ext_status = ctrl_read(ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX);
break;
case READ_SLOTSTATUS:
// DO NOT update the slot structure
- *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
+ *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
break;
case READ_EXTSLOTSTATUS:
// DO NOT update the slot structure
- *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
+ *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
break;
case READ_CTLRSTATUS:
break;
case READ_BUSSTATUS:
- pslot->busstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
+ pslot->busstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
break;
case READ_REVLEVEL:
- *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
+ *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
break;
case READ_HPCOPTIONS:
- *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
+ *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
break;
case READ_SLOTLATCHLOWREG:
// DO NOT update the slot structure
- *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
+ *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
break;
// Not used
case READ_ALLSLOT:
- list_for_each (pslotlist, &ibmphp_slot_head) {
- pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
+ list_for_each_entry(pslot, &ibmphp_slot_head,
+ ibm_slot_list) {
index = pslot->ctlr_index;
- rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr,
+ rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr,
wpg_bbar, &status);
if (!rc) {
- pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index);
- rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT,
+ pslot->status = ctrl_read(ctlr_ptr, wpg_bbar, index);
+ rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT,
ctlr_ptr, wpg_bbar, &status);
if (!rc)
pslot->ext_status =
- ctrl_read (ctlr_ptr, wpg_bbar,
+ ctrl_read(ctlr_ptr, wpg_bbar,
index + WPG_1ST_EXTSLOT_INDEX);
} else {
- err ("%s - Error ctrl_read failed\n", __func__);
+ err("%s - Error ctrl_read failed\n", __func__);
rc = -EINVAL;
break;
}
// remove physical to logical address mapping
if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
- iounmap (wpg_bbar);
+ iounmap(wpg_bbar);
- free_hpc_access ();
+ free_hpc_access();
- debug_polling ("%s - Exit rc[%d]\n", __func__, rc);
+ debug_polling("%s - Exit rc[%d]\n", __func__, rc);
return rc;
}
*
* Action: issue a WRITE command to HPC
*---------------------------------------------------------------------*/
-int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd)
+int ibmphp_hpc_writeslot(struct slot *pslot, u8 cmd)
{
void __iomem *wpg_bbar = NULL;
struct controller *ctlr_ptr;
int rc = 0;
int timeout;
- debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd);
+ debug_polling("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd);
if (pslot == NULL) {
rc = -EINVAL;
- err ("%s - Error Exit rc[%d]\n", __func__, rc);
+ err("%s - Error Exit rc[%d]\n", __func__, rc);
return rc;
}
if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) ||
(cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) ||
(cmd == HPC_BUS_133PCIXMODE)) {
- busindex = ibmphp_get_bus_index (pslot->bus);
+ busindex = ibmphp_get_bus_index(pslot->bus);
if (busindex < 0) {
rc = -EINVAL;
- err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
+ err("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
return rc;
} else
index = (u8) busindex;
} else
index = pslot->ctlr_index;
- index = hpc_writecmdtoindex (cmd, index);
+ index = hpc_writecmdtoindex(cmd, index);
if (index == HPC_ERROR) {
rc = -EINVAL;
- err ("%s - Error Exit rc[%d]\n", __func__, rc);
+ err("%s - Error Exit rc[%d]\n", __func__, rc);
return rc;
}
ctlr_ptr = pslot->ctrl;
- get_hpc_access ();
+ get_hpc_access();
//--------------------------------------------------------------------
// map physical address to logical address
//--------------------------------------------------------------------
if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) {
- wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
+ wpg_bbar = ioremap(ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
- debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__,
+ debug("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__,
ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar,
ctlr_ptr->u.wpeg_ctlr.i2c_addr);
}
//--------------------------------------------------------------------
// check controller status before writing
//--------------------------------------------------------------------
- rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
+ rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
if (!rc) {
- ctrl_write (ctlr_ptr, wpg_bbar, index, cmd);
+ ctrl_write(ctlr_ptr, wpg_bbar, index, cmd);
//--------------------------------------------------------------------
// check controller is still not working on the command
timeout = CMD_COMPLETE_TOUT_SEC;
done = 0;
while (!done) {
- rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
+ rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
&status);
if (!rc) {
- if (NEEDTOCHECK_CMDSTATUS (cmd)) {
- if (CTLR_FINISHED (status) == HPC_CTLR_FINISHED_YES)
+ if (NEEDTOCHECK_CMDSTATUS(cmd)) {
+ if (CTLR_FINISHED(status) == HPC_CTLR_FINISHED_YES)
done = 1;
} else
done = 1;
msleep(1000);
if (timeout < 1) {
done = 1;
- err ("%s - Error command complete timeout\n", __func__);
+ err("%s - Error command complete timeout\n", __func__);
rc = -EFAULT;
} else
timeout--;
// remove physical to logical address mapping
if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
- iounmap (wpg_bbar);
- free_hpc_access ();
+ iounmap(wpg_bbar);
+ free_hpc_access();
- debug_polling ("%s - Exit rc[%d]\n", __func__, rc);
+ debug_polling("%s - Exit rc[%d]\n", __func__, rc);
return rc;
}
*
* Action: make sure only one process can access HPC at one time
*---------------------------------------------------------------------*/
-static void get_hpc_access (void)
+static void get_hpc_access(void)
{
mutex_lock(&sem_hpcaccess);
}
/*----------------------------------------------------------------------
* Name: free_hpc_access()
*---------------------------------------------------------------------*/
-void free_hpc_access (void)
+void free_hpc_access(void)
{
mutex_unlock(&sem_hpcaccess);
}
*
* Action: make sure only one process can change the data structure
*---------------------------------------------------------------------*/
-void ibmphp_lock_operations (void)
+void ibmphp_lock_operations(void)
{
- down (&semOperations);
+ down(&semOperations);
to_debug = 1;
}
/*----------------------------------------------------------------------
* Name: ibmphp_unlock_operations()
*---------------------------------------------------------------------*/
-void ibmphp_unlock_operations (void)
+void ibmphp_unlock_operations(void)
{
- debug ("%s - Entry\n", __func__);
- up (&semOperations);
+ debug("%s - Entry\n", __func__);
+ up(&semOperations);
to_debug = 0;
- debug ("%s - Exit\n", __func__);
+ debug("%s - Exit\n", __func__);
}
/*----------------------------------------------------------------------
{
struct slot myslot;
struct slot *pslot = NULL;
- struct list_head *pslotlist;
int rc;
int poll_state = POLL_LATCH_REGISTER;
u8 oldlatchlow = 0x00;
int poll_count = 0;
u8 ctrl_count = 0x00;
- debug ("%s - Entry\n", __func__);
+ debug("%s - Entry\n", __func__);
while (!kthread_should_stop()) {
/* try to get the lock to do some kind of hardware access */
- down (&semOperations);
+ down(&semOperations);
switch (poll_state) {
case POLL_LATCH_REGISTER:
oldlatchlow = curlatchlow;
ctrl_count = 0x00;
- list_for_each (pslotlist, &ibmphp_slot_head) {
+ list_for_each_entry(pslot, &ibmphp_slot_head,
+ ibm_slot_list) {
if (ctrl_count >= ibmphp_get_total_controllers())
break;
- pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
ctrl_count++;
- if (READ_SLOT_LATCH (pslot->ctrl)) {
- rc = ibmphp_hpc_readslot (pslot,
+ if (READ_SLOT_LATCH(pslot->ctrl)) {
+ rc = ibmphp_hpc_readslot(pslot,
READ_SLOTLATCHLOWREG,
&curlatchlow);
if (oldlatchlow != curlatchlow)
- process_changeinlatch (oldlatchlow,
+ process_changeinlatch(oldlatchlow,
curlatchlow,
pslot->ctrl);
}
poll_state = POLL_SLEEP;
break;
case POLL_SLOTS:
- list_for_each (pslotlist, &ibmphp_slot_head) {
- pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
+ list_for_each_entry(pslot, &ibmphp_slot_head,
+ ibm_slot_list) {
// make a copy of the old status
- memcpy ((void *) &myslot, (void *) pslot,
- sizeof (struct slot));
- rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
+ memcpy((void *) &myslot, (void *) pslot,
+ sizeof(struct slot));
+ rc = ibmphp_hpc_readslot(pslot, READ_ALLSTAT, NULL);
if ((myslot.status != pslot->status)
|| (myslot.ext_status != pslot->ext_status))
- process_changeinstatus (pslot, &myslot);
+ process_changeinstatus(pslot, &myslot);
}
ctrl_count = 0x00;
- list_for_each (pslotlist, &ibmphp_slot_head) {
+ list_for_each_entry(pslot, &ibmphp_slot_head,
+ ibm_slot_list) {
if (ctrl_count >= ibmphp_get_total_controllers())
break;
- pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
ctrl_count++;
- if (READ_SLOT_LATCH (pslot->ctrl))
- rc = ibmphp_hpc_readslot (pslot,
+ if (READ_SLOT_LATCH(pslot->ctrl))
+ rc = ibmphp_hpc_readslot(pslot,
READ_SLOTLATCHLOWREG,
&curlatchlow);
}
break;
case POLL_SLEEP:
/* don't sleep with a lock on the hardware */
- up (&semOperations);
+ up(&semOperations);
msleep(POLL_INTERVAL_SEC * 1000);
if (kthread_should_stop())
goto out_sleep;
- down (&semOperations);
+ down(&semOperations);
if (poll_count >= POLL_LATCH_CNT) {
poll_count = 0;
break;
}
/* give up the hardware semaphore */
- up (&semOperations);
+ up(&semOperations);
/* sleep for a short time just for good measure */
out_sleep:
msleep(100);
}
- up (&sem_exit);
- debug ("%s - Exit\n", __func__);
+ up(&sem_exit);
+ debug("%s - Exit\n", __func__);
return 0;
}
*
* Notes:
*---------------------------------------------------------------------*/
-static int process_changeinstatus (struct slot *pslot, struct slot *poldslot)
+static int process_changeinstatus(struct slot *pslot, struct slot *poldslot)
{
u8 status;
int rc = 0;
u8 disable = 0;
u8 update = 0;
- debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot);
+ debug("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot);
// bit 0 - HPC_SLOT_POWER
if ((pslot->status & 0x01) != (poldslot->status & 0x01))
// bit 5 - HPC_SLOT_PWRGD
if ((pslot->status & 0x20) != (poldslot->status & 0x20))
// OFF -> ON: ignore, ON -> OFF: disable slot
- if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status)))
+ if ((poldslot->status & 0x20) && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT(poldslot->status)))
disable = 1;
// bit 6 - HPC_SLOT_BUS_SPEED
update = 1;
// OPEN -> CLOSE
if (pslot->status & 0x80) {
- if (SLOT_PWRGD (pslot->status)) {
+ if (SLOT_PWRGD(pslot->status)) {
// power goes on and off after closing latch
// check again to make sure power is still ON
msleep(1000);
- rc = ibmphp_hpc_readslot (pslot, READ_SLOTSTATUS, &status);
- if (SLOT_PWRGD (status))
+ rc = ibmphp_hpc_readslot(pslot, READ_SLOTSTATUS, &status);
+ if (SLOT_PWRGD(status))
update = 1;
else // overwrite power in pslot to OFF
pslot->status &= ~HPC_SLOT_POWER;
}
}
// CLOSE -> OPEN
- else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD)
- && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) {
+ else if ((SLOT_PWRGD(poldslot->status) == HPC_SLOT_PWRGD_GOOD)
+ && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT(poldslot->status))) {
disable = 1;
}
// else - ignore
update = 1;
if (disable) {
- debug ("process_changeinstatus - disable slot\n");
+ debug("process_changeinstatus - disable slot\n");
pslot->flag = 0;
- rc = ibmphp_do_disable_slot (pslot);
+ rc = ibmphp_do_disable_slot(pslot);
}
if (update || disable)
- ibmphp_update_slot_info (pslot);
+ ibmphp_update_slot_info(pslot);
- debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update);
+ debug("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update);
return rc;
}
* Return 0 or error codes
* Value:
*---------------------------------------------------------------------*/
-static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl)
+static int process_changeinlatch(u8 old, u8 new, struct controller *ctrl)
{
struct slot myslot, *pslot;
u8 i;
u8 mask;
int rc = 0;
- debug ("%s - Entry old[%x], new[%x]\n", __func__, old, new);
+ debug("%s - Entry old[%x], new[%x]\n", __func__, old, new);
// bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots
for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) {
mask = 0x01 << i;
if ((mask & old) != (mask & new)) {
- pslot = ibmphp_get_slot_from_physical_num (i);
+ pslot = ibmphp_get_slot_from_physical_num(i);
if (pslot) {
- memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot));
- rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
- debug ("%s - call process_changeinstatus for slot[%d]\n", __func__, i);
- process_changeinstatus (pslot, &myslot);
+ memcpy((void *) &myslot, (void *) pslot, sizeof(struct slot));
+ rc = ibmphp_hpc_readslot(pslot, READ_ALLSTAT, NULL);
+ debug("%s - call process_changeinstatus for slot[%d]\n", __func__, i);
+ process_changeinstatus(pslot, &myslot);
} else {
rc = -EINVAL;
- err ("%s - Error bad pointer for slot[%d]\n", __func__, i);
+ err("%s - Error bad pointer for slot[%d]\n", __func__, i);
}
}
}
- debug ("%s - Exit rc[%d]\n", __func__, rc);
+ debug("%s - Exit rc[%d]\n", __func__, rc);
return rc;
}
*
* Action: start polling thread
*---------------------------------------------------------------------*/
-int __init ibmphp_hpc_start_poll_thread (void)
+int __init ibmphp_hpc_start_poll_thread(void)
{
- debug ("%s - Entry\n", __func__);
+ debug("%s - Entry\n", __func__);
ibmphp_poll_thread = kthread_run(poll_hpc, NULL, "hpc_poll");
if (IS_ERR(ibmphp_poll_thread)) {
- err ("%s - Error, thread not started\n", __func__);
+ err("%s - Error, thread not started\n", __func__);
return PTR_ERR(ibmphp_poll_thread);
}
return 0;
*
* Action: stop polling thread and cleanup
*---------------------------------------------------------------------*/
-void __exit ibmphp_hpc_stop_poll_thread (void)
+void __exit ibmphp_hpc_stop_poll_thread(void)
{
- debug ("%s - Entry\n", __func__);
+ debug("%s - Entry\n", __func__);
kthread_stop(ibmphp_poll_thread);
- debug ("before locking operations \n");
- ibmphp_lock_operations ();
- debug ("after locking operations \n");
+ debug("before locking operations\n");
+ ibmphp_lock_operations();
+ debug("after locking operations\n");
// wait for poll thread to exit
- debug ("before sem_exit down \n");
- down (&sem_exit);
- debug ("after sem_exit down \n");
+ debug("before sem_exit down\n");
+ down(&sem_exit);
+ debug("after sem_exit down\n");
// cleanup
- debug ("before free_hpc_access \n");
- free_hpc_access ();
- debug ("after free_hpc_access \n");
- ibmphp_unlock_operations ();
- debug ("after unlock operations \n");
- up (&sem_exit);
- debug ("after sem exit up\n");
-
- debug ("%s - Exit\n", __func__);
+ debug("before free_hpc_access\n");
+ free_hpc_access();
+ debug("after free_hpc_access\n");
+ ibmphp_unlock_operations();
+ debug("after unlock operations\n");
+ up(&sem_exit);
+ debug("after sem exit up\n");
+
+ debug("%s - Exit\n", __func__);
}
/*----------------------------------------------------------------------
* Return 0, HPC_ERROR
* Value:
*---------------------------------------------------------------------*/
-static int hpc_wait_ctlr_notworking (int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar,
+static int hpc_wait_ctlr_notworking(int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar,
u8 *pstatus)
{
int rc = 0;
u8 done = 0;
- debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout);
+ debug_polling("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout);
while (!done) {
- *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX);
+ *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX);
if (*pstatus == HPC_ERROR) {
rc = HPC_ERROR;
done = 1;
}
- if (CTLR_WORKING (*pstatus) == HPC_CTLR_WORKING_NO)
+ if (CTLR_WORKING(*pstatus) == HPC_CTLR_WORKING_NO)
done = 1;
if (!done) {
msleep(1000);
if (timeout < 1) {
done = 1;
- err ("HPCreadslot - Error ctlr timeout\n");
+ err("HPCreadslot - Error ctlr timeout\n");
rc = HPC_ERROR;
} else
timeout--;
}
}
- debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus);
+ debug_polling("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus);
return rc;
}
static int configure_device(struct pci_func *);
static int configure_bridge(struct pci_func **, u8);
static struct res_needed *scan_behind_bridge(struct pci_func *, u8);
-static int add_new_bus (struct bus_node *, struct resource_node *, struct resource_node *, struct resource_node *, u8);
-static u8 find_sec_number (u8 primary_busno, u8 slotno);
+static int add_new_bus(struct bus_node *, struct resource_node *, struct resource_node *, struct resource_node *, u8);
+static u8 find_sec_number(u8 primary_busno, u8 slotno);
/*
* NOTE..... If BIOS doesn't provide default routing, we assign:
* We also assign the same irq numbers for multi function devices.
* These are PIC mode, so shouldn't matter n.e.ways (hopefully)
*/
-static void assign_alt_irq (struct pci_func *cur_func, u8 class_code)
+static void assign_alt_irq(struct pci_func *cur_func, u8 class_code)
{
int j;
for (j = 0; j < 4; j++) {
* if there is an error, will need to go through all previous functions and
* unconfigure....or can add some code into unconfigure_card....
*/
-int ibmphp_configure_card (struct pci_func *func, u8 slotno)
+int ibmphp_configure_card(struct pci_func *func, u8 slotno)
{
u16 vendor_id;
u32 class;
u8 flag;
u8 valid_device = 0x00; /* to see if we are able to read from card any device info at all */
- debug ("inside configure_card, func->busno = %x\n", func->busno);
+ debug("inside configure_card, func->busno = %x\n", func->busno);
device = func->device;
cur_func = func;
cur_func->function = function;
- debug ("inside the loop, cur_func->busno = %x, cur_func->device = %x, cur_func->function = %x\n",
+ debug("inside the loop, cur_func->busno = %x, cur_func->device = %x, cur_func->function = %x\n",
cur_func->busno, cur_func->device, cur_func->function);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
- debug ("vendor_id is %x\n", vendor_id);
+ debug("vendor_id is %x\n", vendor_id);
if (vendor_id != PCI_VENDOR_ID_NOTVALID) {
/* found correct device!!! */
- debug ("found valid device, vendor_id = %x\n", vendor_id);
+ debug("found valid device, vendor_id = %x\n", vendor_id);
++valid_device;
* |_=> 0 = single function device, 1 = multi-function device
*/
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class);
class_code = class >> 24;
- debug ("hrd_type = %x, class = %x, class_code %x\n", hdr_type, class, class_code);
+ debug("hrd_type = %x, class = %x, class_code %x\n", hdr_type, class, class_code);
class >>= 8; /* to take revision out, class = class.subclass.prog i/f */
if (class == PCI_CLASS_NOT_DEFINED_VGA) {
- err ("The device %x is VGA compatible and as is not supported for hot plugging. "
+ err("The device %x is VGA compatible and as is not supported for hot plugging. "
"Please choose another device.\n", cur_func->device);
return -ENODEV;
} else if (class == PCI_CLASS_DISPLAY_VGA) {
- err ("The device %x is not supported for hot plugging. Please choose another device.\n",
+ err("The device %x is not supported for hot plugging. Please choose another device.\n",
cur_func->device);
return -ENODEV;
}
switch (hdr_type) {
case PCI_HEADER_TYPE_NORMAL:
- debug ("single device case.... vendor id = %x, hdr_type = %x, class = %x\n", vendor_id, hdr_type, class);
- assign_alt_irq (cur_func, class_code);
+ debug("single device case.... vendor id = %x, hdr_type = %x, class = %x\n", vendor_id, hdr_type, class);
+ assign_alt_irq(cur_func, class_code);
rc = configure_device(cur_func);
if (rc < 0) {
/* We need to do this in case some other BARs were properly inserted */
- err ("was not able to configure devfunc %x on bus %x.\n",
+ err("was not able to configure devfunc %x on bus %x.\n",
cur_func->device, cur_func->busno);
cleanup_count = 6;
goto error;
function = 0x8;
break;
case PCI_HEADER_TYPE_MULTIDEVICE:
- assign_alt_irq (cur_func, class_code);
+ assign_alt_irq(cur_func, class_code);
rc = configure_device(cur_func);
if (rc < 0) {
/* We need to do this in case some other BARs were properly inserted */
- err ("was not able to configure devfunc %x on bus %x...bailing out\n",
+ err("was not able to configure devfunc %x on bus %x...bailing out\n",
cur_func->device, cur_func->busno);
cleanup_count = 6;
goto error;
}
newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
if (!newfunc) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
newfunc->busno = cur_func->busno;
case PCI_HEADER_TYPE_MULTIBRIDGE:
class >>= 8;
if (class != PCI_CLASS_BRIDGE_PCI) {
- err ("This %x is not PCI-to-PCI bridge, and as is not supported for hot-plugging. Please insert another card.\n",
+ err("This %x is not PCI-to-PCI bridge, and as is not supported for hot-plugging. Please insert another card.\n",
cur_func->device);
return -ENODEV;
}
- assign_alt_irq (cur_func, class_code);
- rc = configure_bridge (&cur_func, slotno);
+ assign_alt_irq(cur_func, class_code);
+ rc = configure_bridge(&cur_func, slotno);
if (rc == -ENODEV) {
- err ("You chose to insert Single Bridge, or nested bridges, this is not supported...\n");
- err ("Bus %x, devfunc %x\n", cur_func->busno, cur_func->device);
+ err("You chose to insert Single Bridge, or nested bridges, this is not supported...\n");
+ err("Bus %x, devfunc %x\n", cur_func->busno, cur_func->device);
return rc;
}
if (rc) {
/* We need to do this in case some other BARs were properly inserted */
- err ("was not able to hot-add PPB properly.\n");
+ err("was not able to hot-add PPB properly.\n");
func->bus = 1; /* To indicate to the unconfigure function that this is a PPB */
cleanup_count = 2;
goto error;
}
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
flag = 0;
for (i = 0; i < 32; i++) {
if (func->devices[i]) {
newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
if (!newfunc) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
newfunc->busno = sec_number;
} else
cur_func->next = newfunc;
- rc = ibmphp_configure_card (newfunc, slotno);
+ rc = ibmphp_configure_card(newfunc, slotno);
/* This could only happen if kmalloc failed */
if (rc) {
/* We need to do this in case bridge itself got configured properly, but devices behind it failed */
newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
if (!newfunc) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
newfunc->busno = cur_func->busno;
newfunc->device = device;
for (j = 0; j < 4; j++)
newfunc->irq[j] = cur_func->irq[j];
- for (prev_func = cur_func; prev_func->next; prev_func = prev_func->next) ;
+ for (prev_func = cur_func; prev_func->next; prev_func = prev_func->next);
prev_func->next = newfunc;
cur_func = newfunc;
break;
case PCI_HEADER_TYPE_BRIDGE:
class >>= 8;
- debug ("class now is %x\n", class);
+ debug("class now is %x\n", class);
if (class != PCI_CLASS_BRIDGE_PCI) {
- err ("This %x is not PCI-to-PCI bridge, and as is not supported for hot-plugging. Please insert another card.\n",
+ err("This %x is not PCI-to-PCI bridge, and as is not supported for hot-plugging. Please insert another card.\n",
cur_func->device);
return -ENODEV;
}
- assign_alt_irq (cur_func, class_code);
+ assign_alt_irq(cur_func, class_code);
- debug ("cur_func->busno b4 configure_bridge is %x\n", cur_func->busno);
- rc = configure_bridge (&cur_func, slotno);
+ debug("cur_func->busno b4 configure_bridge is %x\n", cur_func->busno);
+ rc = configure_bridge(&cur_func, slotno);
if (rc == -ENODEV) {
- err ("You chose to insert Single Bridge, or nested bridges, this is not supported...\n");
- err ("Bus %x, devfunc %x\n", cur_func->busno, cur_func->device);
+ err("You chose to insert Single Bridge, or nested bridges, this is not supported...\n");
+ err("Bus %x, devfunc %x\n", cur_func->busno, cur_func->device);
return rc;
}
if (rc) {
/* We need to do this in case some other BARs were properly inserted */
func->bus = 1; /* To indicate to the unconfigure function that this is a PPB */
- err ("was not able to hot-add PPB properly.\n");
+ err("was not able to hot-add PPB properly.\n");
cleanup_count = 2;
goto error;
}
- debug ("cur_func->busno = %x, device = %x, function = %x\n",
+ debug("cur_func->busno = %x, device = %x, function = %x\n",
cur_func->busno, device, function);
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
- debug ("after configuring bridge..., sec_number = %x\n", sec_number);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
+ debug("after configuring bridge..., sec_number = %x\n", sec_number);
flag = 0;
for (i = 0; i < 32; i++) {
if (func->devices[i]) {
- debug ("inside for loop, device is %x\n", i);
+ debug("inside for loop, device is %x\n", i);
newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
if (!newfunc) {
- err (" out of system memory\n");
+ err(" out of system memory\n");
return -ENOMEM;
}
newfunc->busno = sec_number;
newfunc->irq[j] = cur_func->irq[j];
if (flag) {
- for (prev_func = cur_func; prev_func->next; prev_func = prev_func->next) ;
+ for (prev_func = cur_func; prev_func->next; prev_func = prev_func->next);
prev_func->next = newfunc;
} else
cur_func->next = newfunc;
- rc = ibmphp_configure_card (newfunc, slotno);
+ rc = ibmphp_configure_card(newfunc, slotno);
/* Again, this case should not happen... For complete paranoia, will need to call remove_bus */
if (rc) {
function = 0x8;
break;
default:
- err ("MAJOR PROBLEM!!!!, header type not supported? %x\n", hdr_type);
+ err("MAJOR PROBLEM!!!!, header type not supported? %x\n", hdr_type);
return -ENXIO;
break;
} /* end of switch */
} /* end of for */
if (!valid_device) {
- err ("Cannot find any valid devices on the card. Or unable to read from card.\n");
+ err("Cannot find any valid devices on the card. Or unable to read from card.\n");
return -ENODEV;
}
error:
for (i = 0; i < cleanup_count; i++) {
if (cur_func->io[i]) {
- ibmphp_remove_resource (cur_func->io[i]);
+ ibmphp_remove_resource(cur_func->io[i]);
cur_func->io[i] = NULL;
} else if (cur_func->pfmem[i]) {
- ibmphp_remove_resource (cur_func->pfmem[i]);
+ ibmphp_remove_resource(cur_func->pfmem[i]);
cur_func->pfmem[i] = NULL;
} else if (cur_func->mem[i]) {
- ibmphp_remove_resource (cur_func->mem[i]);
+ ibmphp_remove_resource(cur_func->mem[i]);
cur_func->mem[i] = NULL;
}
}
* Input: pointer to the pci_func
* Output: configured PCI, 0, or error
*/
-static int configure_device (struct pci_func *func)
+static int configure_device(struct pci_func *func)
{
u32 bar[6];
u32 address[] = {
struct resource_node *pfmem[6];
unsigned int devfn;
- debug ("%s - inside\n", __func__);
+ debug("%s - inside\n", __func__);
devfn = PCI_DEVFN(func->device, func->function);
ibmphp_pci_bus->number = func->busno;
pcibios_write_config_dword(cur_func->busno, cur_func->device,
PCI_BASE_ADDRESS_0 + 4 * count, 0xFFFFFFFF);
*/
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &bar[count]);
if (!bar[count]) /* This BAR is not implemented */
continue;
- debug ("Device %x BAR %d wants %x\n", func->device, count, bar[count]);
+ debug("Device %x BAR %d wants %x\n", func->device, count, bar[count]);
if (bar[count] & PCI_BASE_ADDRESS_SPACE_IO) {
/* This is IO */
- debug ("inside IO SPACE\n");
+ debug("inside IO SPACE\n");
len[count] = bar[count] & 0xFFFFFFFC;
len[count] = ~len[count] + 1;
- debug ("len[count] in IO %x, count %d\n", len[count], count);
+ debug("len[count] in IO %x, count %d\n", len[count], count);
io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!io[count]) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
io[count]->type = IO;
io[count]->devfunc = PCI_DEVFN(func->device, func->function);
io[count]->len = len[count];
if (ibmphp_check_resource(io[count], 0) == 0) {
- ibmphp_add_resource (io[count]);
+ ibmphp_add_resource(io[count]);
func->io[count] = io[count];
} else {
- err ("cannot allocate requested io for bus %x device %x function %x len %x\n",
+ err("cannot allocate requested io for bus %x device %x function %x len %x\n",
func->busno, func->device, func->function, len[count]);
- kfree (io[count]);
+ kfree(io[count]);
return -EIO;
}
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->io[count]->start);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], func->io[count]->start);
/* _______________This is for debugging purposes only_____________________ */
- debug ("b4 writing, the IO address is %x\n", func->io[count]->start);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]);
- debug ("after writing.... the start address is %x\n", bar[count]);
+ debug("b4 writing, the IO address is %x\n", func->io[count]->start);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &bar[count]);
+ debug("after writing.... the start address is %x\n", bar[count]);
/* _________________________________________________________________________*/
} else {
/* This is Memory */
if (bar[count] & PCI_BASE_ADDRESS_MEM_PREFETCH) {
/* pfmem */
- debug ("PFMEM SPACE\n");
+ debug("PFMEM SPACE\n");
len[count] = bar[count] & 0xFFFFFFF0;
len[count] = ~len[count] + 1;
- debug ("len[count] in PFMEM %x, count %d\n", len[count], count);
+ debug("len[count] in PFMEM %x, count %d\n", len[count], count);
pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!pfmem[count]) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
pfmem[count]->type = PFMEM;
func->function);
pfmem[count]->len = len[count];
pfmem[count]->fromMem = 0;
- if (ibmphp_check_resource (pfmem[count], 0) == 0) {
- ibmphp_add_resource (pfmem[count]);
+ if (ibmphp_check_resource(pfmem[count], 0) == 0) {
+ ibmphp_add_resource(pfmem[count]);
func->pfmem[count] = pfmem[count];
} else {
mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
if (!mem_tmp) {
- err ("out of system memory\n");
- kfree (pfmem[count]);
+ err("out of system memory\n");
+ kfree(pfmem[count]);
return -ENOMEM;
}
mem_tmp->type = MEM;
mem_tmp->busno = pfmem[count]->busno;
mem_tmp->devfunc = pfmem[count]->devfunc;
mem_tmp->len = pfmem[count]->len;
- debug ("there's no pfmem... going into mem.\n");
- if (ibmphp_check_resource (mem_tmp, 0) == 0) {
- ibmphp_add_resource (mem_tmp);
+ debug("there's no pfmem... going into mem.\n");
+ if (ibmphp_check_resource(mem_tmp, 0) == 0) {
+ ibmphp_add_resource(mem_tmp);
pfmem[count]->fromMem = 1;
pfmem[count]->rangeno = mem_tmp->rangeno;
pfmem[count]->start = mem_tmp->start;
pfmem[count]->end = mem_tmp->end;
- ibmphp_add_pfmem_from_mem (pfmem[count]);
+ ibmphp_add_pfmem_from_mem(pfmem[count]);
func->pfmem[count] = pfmem[count];
} else {
- err ("cannot allocate requested pfmem for bus %x, device %x, len %x\n",
+ err("cannot allocate requested pfmem for bus %x, device %x, len %x\n",
func->busno, func->device, len[count]);
- kfree (mem_tmp);
- kfree (pfmem[count]);
+ kfree(mem_tmp);
+ kfree(pfmem[count]);
return -EIO;
}
}
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->pfmem[count]->start);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], func->pfmem[count]->start);
/*_______________This is for debugging purposes only______________________________*/
- debug ("b4 writing, start address is %x\n", func->pfmem[count]->start);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]);
- debug ("after writing, start address is %x\n", bar[count]);
+ debug("b4 writing, start address is %x\n", func->pfmem[count]->start);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &bar[count]);
+ debug("after writing, start address is %x\n", bar[count]);
/*_________________________________________________________________________________*/
if (bar[count] & PCI_BASE_ADDRESS_MEM_TYPE_64) { /* takes up another dword */
- debug ("inside the mem 64 case, count %d\n", count);
+ debug("inside the mem 64 case, count %d\n", count);
count += 1;
/* on the 2nd dword, write all 0s, since we can't handle them n.e.ways */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0x00000000);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0x00000000);
}
} else {
/* regular memory */
- debug ("REGULAR MEM SPACE\n");
+ debug("REGULAR MEM SPACE\n");
len[count] = bar[count] & 0xFFFFFFF0;
len[count] = ~len[count] + 1;
- debug ("len[count] in Mem %x, count %d\n", len[count], count);
+ debug("len[count] in Mem %x, count %d\n", len[count], count);
mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!mem[count]) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
mem[count]->type = MEM;
mem[count]->devfunc = PCI_DEVFN(func->device,
func->function);
mem[count]->len = len[count];
- if (ibmphp_check_resource (mem[count], 0) == 0) {
- ibmphp_add_resource (mem[count]);
+ if (ibmphp_check_resource(mem[count], 0) == 0) {
+ ibmphp_add_resource(mem[count]);
func->mem[count] = mem[count];
} else {
- err ("cannot allocate requested mem for bus %x, device %x, len %x\n",
+ err("cannot allocate requested mem for bus %x, device %x, len %x\n",
func->busno, func->device, len[count]);
- kfree (mem[count]);
+ kfree(mem[count]);
return -EIO;
}
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->mem[count]->start);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], func->mem[count]->start);
/* _______________________This is for debugging purposes only _______________________*/
- debug ("b4 writing, start address is %x\n", func->mem[count]->start);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]);
- debug ("after writing, the address is %x\n", bar[count]);
+ debug("b4 writing, start address is %x\n", func->mem[count]->start);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &bar[count]);
+ debug("after writing, the address is %x\n", bar[count]);
/* __________________________________________________________________________________*/
if (bar[count] & PCI_BASE_ADDRESS_MEM_TYPE_64) {
/* takes up another dword */
- debug ("inside mem 64 case, reg. mem, count %d\n", count);
+ debug("inside mem 64 case, reg. mem, count %d\n", count);
count += 1;
/* on the 2nd dword, write all 0s, since we can't handle them n.e.ways */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0x00000000);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0x00000000);
}
}
} /* end of mem */
} /* end of for */
func->bus = 0; /* To indicate that this is not a PPB */
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_INTERRUPT_PIN, &irq);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_INTERRUPT_PIN, &irq);
if ((irq > 0x00) && (irq < 0x05))
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_CACHE_LINE_SIZE, CACHE);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_LATENCY_TIMER, LATENCY);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_CACHE_LINE_SIZE, CACHE);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_LATENCY_TIMER, LATENCY);
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, PCI_ROM_ADDRESS, 0x00L);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_COMMAND, DEVICEENABLE);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, PCI_ROM_ADDRESS, 0x00L);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_COMMAND, DEVICEENABLE);
return 0;
}
* Parameters: pci_func
* Returns:
******************************************************************************/
-static int configure_bridge (struct pci_func **func_passed, u8 slotno)
+static int configure_bridge(struct pci_func **func_passed, u8 slotno)
{
int count;
int i;
u8 irq;
int retval;
- debug ("%s - enter\n", __func__);
+ debug("%s - enter\n", __func__);
devfn = PCI_DEVFN(func->function, func->device);
ibmphp_pci_bus->number = func->busno;
* behind it
*/
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, func->busno);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, func->busno);
/* _____________________For debugging purposes only __________________________
- pci_bus_config_byte (ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, &pri_number);
- debug ("primary # written into the bridge is %x\n", pri_number);
+ pci_bus_config_byte(ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, &pri_number);
+ debug("primary # written into the bridge is %x\n", pri_number);
___________________________________________________________________________*/
/* in EBDA, only get allocated 1 additional bus # per slot */
- sec_number = find_sec_number (func->busno, slotno);
+ sec_number = find_sec_number(func->busno, slotno);
if (sec_number == 0xff) {
- err ("cannot allocate secondary bus number for the bridged device\n");
+ err("cannot allocate secondary bus number for the bridged device\n");
return -EINVAL;
}
- debug ("after find_sec_number, the number we got is %x\n", sec_number);
- debug ("AFTER FIND_SEC_NUMBER, func->busno IS %x\n", func->busno);
+ debug("after find_sec_number, the number we got is %x\n", sec_number);
+ debug("AFTER FIND_SEC_NUMBER, func->busno IS %x\n", func->busno);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, sec_number);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, sec_number);
/* __________________For debugging purposes only __________________________________
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
- debug ("sec_number after write/read is %x\n", sec_number);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
+ debug("sec_number after write/read is %x\n", sec_number);
________________________________________________________________________________*/
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_SUBORDINATE_BUS, sec_number);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_SUBORDINATE_BUS, sec_number);
/* __________________For debugging purposes only ____________________________________
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SUBORDINATE_BUS, &sec_number);
- debug ("subordinate number after write/read is %x\n", sec_number);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SUBORDINATE_BUS, &sec_number);
+ debug("subordinate number after write/read is %x\n", sec_number);
__________________________________________________________________________________*/
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_CACHE_LINE_SIZE, CACHE);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_LATENCY_TIMER, LATENCY);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_SEC_LATENCY_TIMER, LATENCY);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_CACHE_LINE_SIZE, CACHE);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_LATENCY_TIMER, LATENCY);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_SEC_LATENCY_TIMER, LATENCY);
- debug ("func->busno is %x\n", func->busno);
- debug ("sec_number after writing is %x\n", sec_number);
+ debug("func->busno is %x\n", func->busno);
+ debug("sec_number after writing is %x\n", sec_number);
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
/* First we need to allocate mem/io for the bridge itself in case it needs it */
for (count = 0; address[count]; count++) { /* for 2 BARs */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &bar[count]);
if (!bar[count]) {
/* This BAR is not implemented */
- debug ("so we come here then, eh?, count = %d\n", count);
+ debug("so we come here then, eh?, count = %d\n", count);
continue;
}
// tmp_bar = bar[count];
- debug ("Bar %d wants %x\n", count, bar[count]);
+ debug("Bar %d wants %x\n", count, bar[count]);
if (bar[count] & PCI_BASE_ADDRESS_SPACE_IO) {
/* This is IO */
len[count] = bar[count] & 0xFFFFFFFC;
len[count] = ~len[count] + 1;
- debug ("len[count] in IO = %x\n", len[count]);
+ debug("len[count] in IO = %x\n", len[count]);
bus_io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!bus_io[count]) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
bus_io[count]->devfunc = PCI_DEVFN(func->device,
func->function);
bus_io[count]->len = len[count];
- if (ibmphp_check_resource (bus_io[count], 0) == 0) {
- ibmphp_add_resource (bus_io[count]);
+ if (ibmphp_check_resource(bus_io[count], 0) == 0) {
+ ibmphp_add_resource(bus_io[count]);
func->io[count] = bus_io[count];
} else {
- err ("cannot allocate requested io for bus %x, device %x, len %x\n",
+ err("cannot allocate requested io for bus %x, device %x, len %x\n",
func->busno, func->device, len[count]);
- kfree (bus_io[count]);
+ kfree(bus_io[count]);
return -EIO;
}
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->io[count]->start);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], func->io[count]->start);
} else {
/* This is Memory */
len[count] = bar[count] & 0xFFFFFFF0;
len[count] = ~len[count] + 1;
- debug ("len[count] in PFMEM = %x\n", len[count]);
+ debug("len[count] in PFMEM = %x\n", len[count]);
bus_pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!bus_pfmem[count]) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
func->function);
bus_pfmem[count]->len = len[count];
bus_pfmem[count]->fromMem = 0;
- if (ibmphp_check_resource (bus_pfmem[count], 0) == 0) {
- ibmphp_add_resource (bus_pfmem[count]);
+ if (ibmphp_check_resource(bus_pfmem[count], 0) == 0) {
+ ibmphp_add_resource(bus_pfmem[count]);
func->pfmem[count] = bus_pfmem[count];
} else {
mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
if (!mem_tmp) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
mem_tmp->busno = bus_pfmem[count]->busno;
mem_tmp->devfunc = bus_pfmem[count]->devfunc;
mem_tmp->len = bus_pfmem[count]->len;
- if (ibmphp_check_resource (mem_tmp, 0) == 0) {
- ibmphp_add_resource (mem_tmp);
+ if (ibmphp_check_resource(mem_tmp, 0) == 0) {
+ ibmphp_add_resource(mem_tmp);
bus_pfmem[count]->fromMem = 1;
bus_pfmem[count]->rangeno = mem_tmp->rangeno;
- ibmphp_add_pfmem_from_mem (bus_pfmem[count]);
+ ibmphp_add_pfmem_from_mem(bus_pfmem[count]);
func->pfmem[count] = bus_pfmem[count];
} else {
- err ("cannot allocate requested pfmem for bus %x, device %x, len %x\n",
+ err("cannot allocate requested pfmem for bus %x, device %x, len %x\n",
func->busno, func->device, len[count]);
- kfree (mem_tmp);
- kfree (bus_pfmem[count]);
+ kfree(mem_tmp);
+ kfree(bus_pfmem[count]);
return -EIO;
}
}
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->pfmem[count]->start);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], func->pfmem[count]->start);
if (bar[count] & PCI_BASE_ADDRESS_MEM_TYPE_64) {
/* takes up another dword */
count += 1;
/* on the 2nd dword, write all 0s, since we can't handle them n.e.ways */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0x00000000);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0x00000000);
}
} else {
len[count] = bar[count] & 0xFFFFFFF0;
len[count] = ~len[count] + 1;
- debug ("len[count] in Memory is %x\n", len[count]);
+ debug("len[count] in Memory is %x\n", len[count]);
bus_mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!bus_mem[count]) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
bus_mem[count]->devfunc = PCI_DEVFN(func->device,
func->function);
bus_mem[count]->len = len[count];
- if (ibmphp_check_resource (bus_mem[count], 0) == 0) {
- ibmphp_add_resource (bus_mem[count]);
+ if (ibmphp_check_resource(bus_mem[count], 0) == 0) {
+ ibmphp_add_resource(bus_mem[count]);
func->mem[count] = bus_mem[count];
} else {
- err ("cannot allocate requested mem for bus %x, device %x, len %x\n",
+ err("cannot allocate requested mem for bus %x, device %x, len %x\n",
func->busno, func->device, len[count]);
- kfree (bus_mem[count]);
+ kfree(bus_mem[count]);
return -EIO;
}
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->mem[count]->start);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], func->mem[count]->start);
if (bar[count] & PCI_BASE_ADDRESS_MEM_TYPE_64) {
/* takes up another dword */
count += 1;
/* on the 2nd dword, write all 0s, since we can't handle them n.e.ways */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0x00000000);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0x00000000);
}
}
} /* end of for */
/* Now need to see how much space the devices behind the bridge needed */
- amount_needed = scan_behind_bridge (func, sec_number);
+ amount_needed = scan_behind_bridge(func, sec_number);
if (amount_needed == NULL)
return -ENOMEM;
ibmphp_pci_bus->number = func->busno;
- debug ("after coming back from scan_behind_bridge\n");
- debug ("amount_needed->not_correct = %x\n", amount_needed->not_correct);
- debug ("amount_needed->io = %x\n", amount_needed->io);
- debug ("amount_needed->mem = %x\n", amount_needed->mem);
- debug ("amount_needed->pfmem = %x\n", amount_needed->pfmem);
+ debug("after coming back from scan_behind_bridge\n");
+ debug("amount_needed->not_correct = %x\n", amount_needed->not_correct);
+ debug("amount_needed->io = %x\n", amount_needed->io);
+ debug("amount_needed->mem = %x\n", amount_needed->mem);
+ debug("amount_needed->pfmem = %x\n", amount_needed->pfmem);
if (amount_needed->not_correct) {
- debug ("amount_needed is not correct\n");
+ debug("amount_needed is not correct\n");
for (count = 0; address[count]; count++) {
/* for 2 BARs */
if (bus_io[count]) {
- ibmphp_remove_resource (bus_io[count]);
+ ibmphp_remove_resource(bus_io[count]);
func->io[count] = NULL;
} else if (bus_pfmem[count]) {
- ibmphp_remove_resource (bus_pfmem[count]);
+ ibmphp_remove_resource(bus_pfmem[count]);
func->pfmem[count] = NULL;
} else if (bus_mem[count]) {
- ibmphp_remove_resource (bus_mem[count]);
+ ibmphp_remove_resource(bus_mem[count]);
func->mem[count] = NULL;
}
}
- kfree (amount_needed);
+ kfree(amount_needed);
return -ENODEV;
}
if (!amount_needed->io) {
- debug ("it doesn't want IO?\n");
+ debug("it doesn't want IO?\n");
flag_io = 1;
} else {
- debug ("it wants %x IO behind the bridge\n", amount_needed->io);
+ debug("it wants %x IO behind the bridge\n", amount_needed->io);
io = kzalloc(sizeof(*io), GFP_KERNEL);
if (!io) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
io->busno = func->busno;
io->devfunc = PCI_DEVFN(func->device, func->function);
io->len = amount_needed->io;
- if (ibmphp_check_resource (io, 1) == 0) {
- debug ("were we able to add io\n");
- ibmphp_add_resource (io);
+ if (ibmphp_check_resource(io, 1) == 0) {
+ debug("were we able to add io\n");
+ ibmphp_add_resource(io);
flag_io = 1;
}
}
if (!amount_needed->mem) {
- debug ("it doesn't want n.e.memory?\n");
+ debug("it doesn't want n.e.memory?\n");
flag_mem = 1;
} else {
- debug ("it wants %x memory behind the bridge\n", amount_needed->mem);
+ debug("it wants %x memory behind the bridge\n", amount_needed->mem);
mem = kzalloc(sizeof(*mem), GFP_KERNEL);
if (!mem) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
mem->busno = func->busno;
mem->devfunc = PCI_DEVFN(func->device, func->function);
mem->len = amount_needed->mem;
- if (ibmphp_check_resource (mem, 1) == 0) {
- ibmphp_add_resource (mem);
+ if (ibmphp_check_resource(mem, 1) == 0) {
+ ibmphp_add_resource(mem);
flag_mem = 1;
- debug ("were we able to add mem\n");
+ debug("were we able to add mem\n");
}
}
if (!amount_needed->pfmem) {
- debug ("it doesn't want n.e.pfmem mem?\n");
+ debug("it doesn't want n.e.pfmem mem?\n");
flag_pfmem = 1;
} else {
- debug ("it wants %x pfmemory behind the bridge\n", amount_needed->pfmem);
+ debug("it wants %x pfmemory behind the bridge\n", amount_needed->pfmem);
pfmem = kzalloc(sizeof(*pfmem), GFP_KERNEL);
if (!pfmem) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
pfmem->devfunc = PCI_DEVFN(func->device, func->function);
pfmem->len = amount_needed->pfmem;
pfmem->fromMem = 0;
- if (ibmphp_check_resource (pfmem, 1) == 0) {
- ibmphp_add_resource (pfmem);
+ if (ibmphp_check_resource(pfmem, 1) == 0) {
+ ibmphp_add_resource(pfmem);
flag_pfmem = 1;
} else {
mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
if (!mem_tmp) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
mem_tmp->busno = pfmem->busno;
mem_tmp->devfunc = pfmem->devfunc;
mem_tmp->len = pfmem->len;
- if (ibmphp_check_resource (mem_tmp, 1) == 0) {
- ibmphp_add_resource (mem_tmp);
+ if (ibmphp_check_resource(mem_tmp, 1) == 0) {
+ ibmphp_add_resource(mem_tmp);
pfmem->fromMem = 1;
pfmem->rangeno = mem_tmp->rangeno;
- ibmphp_add_pfmem_from_mem (pfmem);
+ ibmphp_add_pfmem_from_mem(pfmem);
flag_pfmem = 1;
}
}
}
- debug ("b4 if (flag_io && flag_mem && flag_pfmem)\n");
- debug ("flag_io = %x, flag_mem = %x, flag_pfmem = %x\n", flag_io, flag_mem, flag_pfmem);
+ debug("b4 if (flag_io && flag_mem && flag_pfmem)\n");
+ debug("flag_io = %x, flag_mem = %x, flag_pfmem = %x\n", flag_io, flag_mem, flag_pfmem);
if (flag_io && flag_mem && flag_pfmem) {
/* If on bootup, there was a bridged card in this slot,
* back again, there's no way for us to remove the bus
* struct, so no need to kmalloc, can use existing node
*/
- bus = ibmphp_find_res_bus (sec_number);
+ bus = ibmphp_find_res_bus(sec_number);
if (!bus) {
bus = kzalloc(sizeof(*bus), GFP_KERNEL);
if (!bus) {
- err ("out of system memory\n");
+ err("out of system memory\n");
retval = -ENOMEM;
goto error;
}
bus->busno = sec_number;
- debug ("b4 adding new bus\n");
- rc = add_new_bus (bus, io, mem, pfmem, func->busno);
+ debug("b4 adding new bus\n");
+ rc = add_new_bus(bus, io, mem, pfmem, func->busno);
} else if (!(bus->rangeIO) && !(bus->rangeMem) && !(bus->rangePFMem))
- rc = add_new_bus (bus, io, mem, pfmem, 0xFF);
+ rc = add_new_bus(bus, io, mem, pfmem, 0xFF);
else {
- err ("expected bus structure not empty?\n");
+ err("expected bus structure not empty?\n");
retval = -EIO;
goto error;
}
if (rc) {
if (rc == -ENOMEM) {
- ibmphp_remove_bus (bus, func->busno);
- kfree (amount_needed);
+ ibmphp_remove_bus(bus, func->busno);
+ kfree(amount_needed);
return rc;
}
retval = rc;
goto error;
}
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, &io_base);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &pfmem_base);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_IO_BASE, &io_base);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &pfmem_base);
if ((io_base & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
- debug ("io 32\n");
+ debug("io 32\n");
need_io_upper = 1;
}
if ((pfmem_base & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
- debug ("pfmem 64\n");
+ debug("pfmem 64\n");
need_pfmem_upper = 1;
}
if (bus->noIORanges) {
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, 0x00 | bus->rangeIO->start >> 8);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_LIMIT, 0x00 | bus->rangeIO->end >> 8);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_IO_BASE, 0x00 | bus->rangeIO->start >> 8);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_IO_LIMIT, 0x00 | bus->rangeIO->end >> 8);
/* _______________This is for debugging purposes only ____________________
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, &temp);
- debug ("io_base = %x\n", (temp & PCI_IO_RANGE_TYPE_MASK) << 8);
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_IO_LIMIT, &temp);
- debug ("io_limit = %x\n", (temp & PCI_IO_RANGE_TYPE_MASK) << 8);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_IO_BASE, &temp);
+ debug("io_base = %x\n", (temp & PCI_IO_RANGE_TYPE_MASK) << 8);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_IO_LIMIT, &temp);
+ debug("io_limit = %x\n", (temp & PCI_IO_RANGE_TYPE_MASK) << 8);
________________________________________________________________________*/
if (need_io_upper) { /* since can't support n.e.ways */
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_IO_BASE_UPPER16, 0x0000);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_IO_LIMIT_UPPER16, 0x0000);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_IO_BASE_UPPER16, 0x0000);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_IO_LIMIT_UPPER16, 0x0000);
}
} else {
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, 0x00);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_LIMIT, 0x00);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_IO_BASE, 0x00);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_IO_LIMIT, 0x00);
}
if (bus->noMemRanges) {
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0x0000 | bus->rangeMem->start >> 16);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, 0x0000 | bus->rangeMem->end >> 16);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0x0000 | bus->rangeMem->start >> 16);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, 0x0000 | bus->rangeMem->end >> 16);
/* ____________________This is for debugging purposes only ________________________
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &temp);
- debug ("mem_base = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, &temp);
- debug ("mem_limit = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &temp);
+ debug("mem_base = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, &temp);
+ debug("mem_limit = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
__________________________________________________________________________________*/
} else {
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0xffff);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, 0x0000);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0xffff);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, 0x0000);
}
if (bus->noPFMemRanges) {
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, 0x0000 | bus->rangePFMem->start >> 16);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, 0x0000 | bus->rangePFMem->end >> 16);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, 0x0000 | bus->rangePFMem->start >> 16);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, 0x0000 | bus->rangePFMem->end >> 16);
/* __________________________This is for debugging purposes only _______________________
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &temp);
- debug ("pfmem_base = %x", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &temp);
- debug ("pfmem_limit = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &temp);
+ debug("pfmem_base = %x", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &temp);
+ debug("pfmem_limit = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16);
______________________________________________________________________________________*/
if (need_pfmem_upper) { /* since can't support n.e.ways */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, PCI_PREF_BASE_UPPER32, 0x00000000);
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, PCI_PREF_LIMIT_UPPER32, 0x00000000);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, PCI_PREF_BASE_UPPER32, 0x00000000);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, PCI_PREF_LIMIT_UPPER32, 0x00000000);
}
} else {
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, 0xffff);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, 0x0000);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, 0xffff);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, 0x0000);
}
- debug ("b4 writing control information\n");
+ debug("b4 writing control information\n");
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_INTERRUPT_PIN, &irq);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_INTERRUPT_PIN, &irq);
if ((irq > 0x00) && (irq < 0x05))
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]);
/*
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, ctrl);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_PARITY);
- pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_SERR);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, ctrl);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_PARITY);
+ pci_bus_write_config_byte(ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_SERR);
*/
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_COMMAND, DEVICEENABLE);
- pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, 0x07);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_COMMAND, DEVICEENABLE);
+ pci_bus_write_config_word(ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, 0x07);
for (i = 0; i < 32; i++) {
if (amount_needed->devices[i]) {
- debug ("device where devices[i] is 1 = %x\n", i);
+ debug("device where devices[i] is 1 = %x\n", i);
func->devices[i] = 1;
}
}
func->bus = 1; /* For unconfiguring, to indicate it's PPB */
func_passed = &func;
- debug ("func->busno b4 returning is %x\n", func->busno);
- debug ("func->busno b4 returning in the other structure is %x\n", (*func_passed)->busno);
- kfree (amount_needed);
+ debug("func->busno b4 returning is %x\n", func->busno);
+ debug("func->busno b4 returning in the other structure is %x\n", (*func_passed)->busno);
+ kfree(amount_needed);
return 0;
} else {
- err ("Configuring bridge was unsuccessful...\n");
+ err("Configuring bridge was unsuccessful...\n");
mem_tmp = NULL;
retval = -EIO;
goto error;
error:
kfree(amount_needed);
if (pfmem)
- ibmphp_remove_resource (pfmem);
+ ibmphp_remove_resource(pfmem);
if (io)
- ibmphp_remove_resource (io);
+ ibmphp_remove_resource(io);
if (mem)
- ibmphp_remove_resource (mem);
+ ibmphp_remove_resource(mem);
for (i = 0; i < 2; i++) { /* for 2 BARs */
if (bus_io[i]) {
- ibmphp_remove_resource (bus_io[i]);
+ ibmphp_remove_resource(bus_io[i]);
func->io[i] = NULL;
} else if (bus_pfmem[i]) {
- ibmphp_remove_resource (bus_pfmem[i]);
+ ibmphp_remove_resource(bus_pfmem[i]);
func->pfmem[i] = NULL;
} else if (bus_mem[i]) {
- ibmphp_remove_resource (bus_mem[i]);
+ ibmphp_remove_resource(bus_mem[i]);
func->mem[i] = NULL;
}
}
* Input: bridge function
* Output: amount of resources needed
*****************************************************************************/
-static struct res_needed *scan_behind_bridge (struct pci_func *func, u8 busno)
+static struct res_needed *scan_behind_bridge(struct pci_func *func, u8 busno)
{
int count, len[6];
u16 vendor_id;
ibmphp_pci_bus->number = busno;
- debug ("the bus_no behind the bridge is %x\n", busno);
- debug ("scanning devices behind the bridge...\n");
+ debug("the bus_no behind the bridge is %x\n", busno);
+ debug("scanning devices behind the bridge...\n");
for (device = 0; device < 32; device++) {
amount->devices[device] = 0;
for (function = 0; function < 8; function++) {
devfn = PCI_DEVFN(device, function);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
if (vendor_id != PCI_VENDOR_ID_NOTVALID) {
/* found correct device!!! */
howmany++;
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class);
- debug ("hdr_type behind the bridge is %x\n", hdr_type);
- if (hdr_type & PCI_HEADER_TYPE_BRIDGE) {
- err ("embedded bridges not supported for hot-plugging.\n");
+ debug("hdr_type behind the bridge is %x\n", hdr_type);
+ if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+ err("embedded bridges not supported for hot-plugging.\n");
amount->not_correct = 1;
return amount;
}
class >>= 8; /* to take revision out, class = class.subclass.prog i/f */
if (class == PCI_CLASS_NOT_DEFINED_VGA) {
- err ("The device %x is VGA compatible and as is not supported for hot plugging. Please choose another device.\n", device);
+ err("The device %x is VGA compatible and as is not supported for hot plugging. Please choose another device.\n", device);
amount->not_correct = 1;
return amount;
} else if (class == PCI_CLASS_DISPLAY_VGA) {
- err ("The device %x is not supported for hot plugging. Please choose another device.\n", device);
+ err("The device %x is not supported for hot plugging. Please choose another device.\n", device);
amount->not_correct = 1;
return amount;
}
for (count = 0; address[count]; count++) {
/* for 6 BARs */
/*
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, address[count], &tmp);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, address[count], &tmp);
if (tmp & 0x01) // IO
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFD);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFD);
else // MEMORY
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
*/
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &bar[count]);
- debug ("what is bar[count]? %x, count = %d\n", bar[count], count);
+ debug("what is bar[count]? %x, count = %d\n", bar[count], count);
if (!bar[count]) /* This BAR is not implemented */
continue;
//tmp_bar = bar[count];
- debug ("count %d device %x function %x wants %x resources\n", count, device, function, bar[count]);
+ debug("count %d device %x function %x wants %x resources\n", count, device, function, bar[count]);
if (bar[count] & PCI_BASE_ADDRESS_SPACE_IO) {
/* This is IO */
* Change: we also call these functions even if we configured the card ourselves (i.e., not
* the bootup case), since it should work same way
*/
-static int unconfigure_boot_device (u8 busno, u8 device, u8 function)
+static int unconfigure_boot_device(u8 busno, u8 device, u8 function)
{
u32 start_address;
u32 address[] = {
u32 tmp_address;
unsigned int devfn;
- debug ("%s - enter\n", __func__);
+ debug("%s - enter\n", __func__);
- bus = ibmphp_find_res_bus (busno);
+ bus = ibmphp_find_res_bus(busno);
if (!bus) {
- debug ("cannot find corresponding bus.\n");
+ debug("cannot find corresponding bus.\n");
return -EINVAL;
}
devfn = PCI_DEVFN(device, function);
ibmphp_pci_bus->number = busno;
for (count = 0; address[count]; count++) { /* for 6 BARs */
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &start_address);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &start_address);
/* We can do this here, b/c by that time the device driver of the card has been stopped */
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &size);
- pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], start_address);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &size);
+ pci_bus_write_config_dword(ibmphp_pci_bus, devfn, address[count], start_address);
- debug ("start_address is %x\n", start_address);
- debug ("busno, device, function %x %x %x\n", busno, device, function);
+ debug("start_address is %x\n", start_address);
+ debug("busno, device, function %x %x %x\n", busno, device, function);
if (!size) {
/* This BAR is not implemented */
- debug ("is this bar no implemented?, count = %d\n", count);
+ debug("is this bar no implemented?, count = %d\n", count);
continue;
}
tmp_address = start_address;
size = size & 0xFFFFFFFC;
size = ~size + 1;
end_address = start_address + size - 1;
- if (ibmphp_find_resource (bus, start_address, &io, IO) < 0) {
- err ("cannot find corresponding IO resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &io, IO) < 0) {
+ err("cannot find corresponding IO resource to remove\n");
return -EIO;
}
- debug ("io->start = %x\n", io->start);
+ debug("io->start = %x\n", io->start);
temp_end = io->end;
start_address = io->end + 1;
- ibmphp_remove_resource (io);
+ ibmphp_remove_resource(io);
/* This is needed b/c of the old I/O restrictions in the BIOS */
while (temp_end < end_address) {
- if (ibmphp_find_resource (bus, start_address, &io, IO) < 0) {
- err ("cannot find corresponding IO resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &io, IO) < 0) {
+ err("cannot find corresponding IO resource to remove\n");
return -EIO;
}
- debug ("io->start = %x\n", io->start);
+ debug("io->start = %x\n", io->start);
temp_end = io->end;
start_address = io->end + 1;
- ibmphp_remove_resource (io);
+ ibmphp_remove_resource(io);
}
/* ????????? DO WE NEED TO WRITE ANYTHING INTO THE PCI CONFIG SPACE BACK ?????????? */
/* This is Memory */
if (start_address & PCI_BASE_ADDRESS_MEM_PREFETCH) {
/* pfmem */
- debug ("start address of pfmem is %x\n", start_address);
+ debug("start address of pfmem is %x\n", start_address);
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
- if (ibmphp_find_resource (bus, start_address, &pfmem, PFMEM) < 0) {
- err ("cannot find corresponding PFMEM resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &pfmem, PFMEM) < 0) {
+ err("cannot find corresponding PFMEM resource to remove\n");
return -EIO;
}
if (pfmem) {
- debug ("pfmem->start = %x\n", pfmem->start);
+ debug("pfmem->start = %x\n", pfmem->start);
ibmphp_remove_resource(pfmem);
}
} else {
/* regular memory */
- debug ("start address of mem is %x\n", start_address);
+ debug("start address of mem is %x\n", start_address);
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
- if (ibmphp_find_resource (bus, start_address, &mem, MEM) < 0) {
- err ("cannot find corresponding MEM resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &mem, MEM) < 0) {
+ err("cannot find corresponding MEM resource to remove\n");
return -EIO;
}
if (mem) {
- debug ("mem->start = %x\n", mem->start);
+ debug("mem->start = %x\n", mem->start);
ibmphp_remove_resource(mem);
}
return 0;
}
-static int unconfigure_boot_bridge (u8 busno, u8 device, u8 function)
+static int unconfigure_boot_bridge(u8 busno, u8 device, u8 function)
{
int count;
int bus_no, pri_no, sub_no, sec_no = 0;
devfn = PCI_DEVFN(device, function);
ibmphp_pci_bus->number = busno;
bus_no = (int) busno;
- debug ("busno is %x\n", busno);
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, &pri_number);
- debug ("%s - busno = %x, primary_number = %x\n", __func__, busno, pri_number);
+ debug("busno is %x\n", busno);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, &pri_number);
+ debug("%s - busno = %x, primary_number = %x\n", __func__, busno, pri_number);
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
- debug ("sec_number is %x\n", sec_number);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
+ debug("sec_number is %x\n", sec_number);
sec_no = (int) sec_number;
pri_no = (int) pri_number;
if (pri_no != bus_no) {
- err ("primary numbers in our structures and pci config space don't match.\n");
+ err("primary numbers in our structures and pci config space don't match.\n");
return -EINVAL;
}
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SUBORDINATE_BUS, &sub_number);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SUBORDINATE_BUS, &sub_number);
sub_no = (int) sub_number;
- debug ("sub_no is %d, sec_no is %d\n", sub_no, sec_no);
+ debug("sub_no is %d, sec_no is %d\n", sub_no, sec_no);
if (sec_no != sub_number) {
- err ("there're more buses behind this bridge. Hot removal is not supported. Please choose another card\n");
+ err("there're more buses behind this bridge. Hot removal is not supported. Please choose another card\n");
return -ENODEV;
}
- bus = ibmphp_find_res_bus (sec_number);
+ bus = ibmphp_find_res_bus(sec_number);
if (!bus) {
- err ("cannot find Bus structure for the bridged device\n");
+ err("cannot find Bus structure for the bridged device\n");
return -EINVAL;
}
debug("bus->busno is %x\n", bus->busno);
debug("sec_number is %x\n", sec_number);
- ibmphp_remove_bus (bus, busno);
+ ibmphp_remove_bus(bus, busno);
for (count = 0; address[count]; count++) {
/* for 2 BARs */
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &start_address);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, address[count], &start_address);
if (!start_address) {
/* This BAR is not implemented */
if (start_address & PCI_BASE_ADDRESS_SPACE_IO) {
/* This is IO */
start_address &= PCI_BASE_ADDRESS_IO_MASK;
- if (ibmphp_find_resource (bus, start_address, &io, IO) < 0) {
- err ("cannot find corresponding IO resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &io, IO) < 0) {
+ err("cannot find corresponding IO resource to remove\n");
return -EIO;
}
if (io)
- debug ("io->start = %x\n", io->start);
+ debug("io->start = %x\n", io->start);
- ibmphp_remove_resource (io);
+ ibmphp_remove_resource(io);
/* ????????? DO WE NEED TO WRITE ANYTHING INTO THE PCI CONFIG SPACE BACK ?????????? */
} else {
if (start_address & PCI_BASE_ADDRESS_MEM_PREFETCH) {
/* pfmem */
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
- if (ibmphp_find_resource (bus, start_address, &pfmem, PFMEM) < 0) {
- err ("cannot find corresponding PFMEM resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &pfmem, PFMEM) < 0) {
+ err("cannot find corresponding PFMEM resource to remove\n");
return -EINVAL;
}
if (pfmem) {
- debug ("pfmem->start = %x\n", pfmem->start);
+ debug("pfmem->start = %x\n", pfmem->start);
ibmphp_remove_resource(pfmem);
}
} else {
/* regular memory */
start_address &= PCI_BASE_ADDRESS_MEM_MASK;
- if (ibmphp_find_resource (bus, start_address, &mem, MEM) < 0) {
- err ("cannot find corresponding MEM resource to remove\n");
+ if (ibmphp_find_resource(bus, start_address, &mem, MEM) < 0) {
+ err("cannot find corresponding MEM resource to remove\n");
return -EINVAL;
}
if (mem) {
- debug ("mem->start = %x\n", mem->start);
+ debug("mem->start = %x\n", mem->start);
ibmphp_remove_resource(mem);
}
}
} /* end of mem */
} /* end of for */
- debug ("%s - exiting, returning success\n", __func__);
+ debug("%s - exiting, returning success\n", __func__);
return 0;
}
-static int unconfigure_boot_card (struct slot *slot_cur)
+static int unconfigure_boot_card(struct slot *slot_cur)
{
u16 vendor_id;
u32 class;
unsigned int devfn;
u8 valid_device = 0x00; /* To see if we are ever able to find valid device and read it */
- debug ("%s - enter\n", __func__);
+ debug("%s - enter\n", __func__);
device = slot_cur->device;
busno = slot_cur->bus;
- debug ("b4 for loop, device is %x\n", device);
+ debug("b4 for loop, device is %x\n", device);
/* For every function on the card */
for (function = 0x0; function < 0x08; function++) {
devfn = PCI_DEVFN(device, function);
ibmphp_pci_bus->number = busno;
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
if (vendor_id != PCI_VENDOR_ID_NOTVALID) {
/* found correct device!!! */
++valid_device;
- debug ("%s - found correct device\n", __func__);
+ debug("%s - found correct device\n", __func__);
/* header: x x x x x x x x
* | |___________|=> 1=PPB bridge, 0=normal device, 2=CardBus Bridge
* |_=> 0 = single function device, 1 = multi-function device
*/
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, PCI_CLASS_REVISION, &class);
- debug ("hdr_type %x, class %x\n", hdr_type, class);
+ debug("hdr_type %x, class %x\n", hdr_type, class);
class >>= 8; /* to take revision out, class = class.subclass.prog i/f */
if (class == PCI_CLASS_NOT_DEFINED_VGA) {
- err ("The device %x function %x is VGA compatible and is not supported for hot removing. Please choose another device.\n", device, function);
+ err("The device %x function %x is VGA compatible and is not supported for hot removing. Please choose another device.\n", device, function);
return -ENODEV;
} else if (class == PCI_CLASS_DISPLAY_VGA) {
- err ("The device %x function %x is not supported for hot removing. Please choose another device.\n", device, function);
+ err("The device %x function %x is not supported for hot removing. Please choose another device.\n", device, function);
return -ENODEV;
}
switch (hdr_type) {
case PCI_HEADER_TYPE_NORMAL:
- rc = unconfigure_boot_device (busno, device, function);
+ rc = unconfigure_boot_device(busno, device, function);
if (rc) {
- err ("was not able to unconfigure device %x func %x on bus %x. bailing out...\n",
+ err("was not able to unconfigure device %x func %x on bus %x. bailing out...\n",
device, function, busno);
return rc;
}
function = 0x8;
break;
case PCI_HEADER_TYPE_MULTIDEVICE:
- rc = unconfigure_boot_device (busno, device, function);
+ rc = unconfigure_boot_device(busno, device, function);
if (rc) {
- err ("was not able to unconfigure device %x func %x on bus %x. bailing out...\n",
+ err("was not able to unconfigure device %x func %x on bus %x. bailing out...\n",
device, function, busno);
return rc;
}
case PCI_HEADER_TYPE_BRIDGE:
class >>= 8;
if (class != PCI_CLASS_BRIDGE_PCI) {
- err ("This device %x function %x is not PCI-to-PCI bridge, and is not supported for hot-removing. Please try another card.\n", device, function);
+ err("This device %x function %x is not PCI-to-PCI bridge, and is not supported for hot-removing. Please try another card.\n", device, function);
return -ENODEV;
}
- rc = unconfigure_boot_bridge (busno, device, function);
+ rc = unconfigure_boot_bridge(busno, device, function);
if (rc != 0) {
- err ("was not able to hot-remove PPB properly.\n");
+ err("was not able to hot-remove PPB properly.\n");
return rc;
}
case PCI_HEADER_TYPE_MULTIBRIDGE:
class >>= 8;
if (class != PCI_CLASS_BRIDGE_PCI) {
- err ("This device %x function %x is not PCI-to-PCI bridge, and is not supported for hot-removing. Please try another card.\n", device, function);
+ err("This device %x function %x is not PCI-to-PCI bridge, and is not supported for hot-removing. Please try another card.\n", device, function);
return -ENODEV;
}
- rc = unconfigure_boot_bridge (busno, device, function);
+ rc = unconfigure_boot_bridge(busno, device, function);
if (rc != 0) {
- err ("was not able to hot-remove PPB properly.\n");
+ err("was not able to hot-remove PPB properly.\n");
return rc;
}
break;
default:
- err ("MAJOR PROBLEM!!!! Cannot read device's header\n");
+ err("MAJOR PROBLEM!!!! Cannot read device's header\n");
return -1;
break;
} /* end of switch */
} /* end of for */
if (!valid_device) {
- err ("Could not find device to unconfigure. Or could not read the card.\n");
+ err("Could not find device to unconfigure. Or could not read the card.\n");
return -1;
}
return 0;
* !!!!!!!!!!!!!!!!!!!!!!!!!FOR BUSES!!!!!!!!!!!!
* Returns: 0, -1, -ENODEV
*/
-int ibmphp_unconfigure_card (struct slot **slot_cur, int the_end)
+int ibmphp_unconfigure_card(struct slot **slot_cur, int the_end)
{
int i;
int count;
struct pci_func *cur_func = NULL;
struct pci_func *temp_func;
- debug ("%s - enter\n", __func__);
+ debug("%s - enter\n", __func__);
if (!the_end) {
/* Need to unconfigure the card */
- rc = unconfigure_boot_card (sl);
+ rc = unconfigure_boot_card(sl);
if ((rc == -ENODEV) || (rc == -EIO) || (rc == -EINVAL)) {
/* In all other cases, will still need to get rid of func structure if it exists */
return rc;
for (i = 0; i < count; i++) {
if (cur_func->io[i]) {
- debug ("io[%d] exists\n", i);
+ debug("io[%d] exists\n", i);
if (the_end > 0)
- ibmphp_remove_resource (cur_func->io[i]);
+ ibmphp_remove_resource(cur_func->io[i]);
cur_func->io[i] = NULL;
}
if (cur_func->mem[i]) {
- debug ("mem[%d] exists\n", i);
+ debug("mem[%d] exists\n", i);
if (the_end > 0)
- ibmphp_remove_resource (cur_func->mem[i]);
+ ibmphp_remove_resource(cur_func->mem[i]);
cur_func->mem[i] = NULL;
}
if (cur_func->pfmem[i]) {
- debug ("pfmem[%d] exists\n", i);
+ debug("pfmem[%d] exists\n", i);
if (the_end > 0)
- ibmphp_remove_resource (cur_func->pfmem[i]);
+ ibmphp_remove_resource(cur_func->pfmem[i]);
cur_func->pfmem[i] = NULL;
}
}
temp_func = cur_func->next;
- kfree (cur_func);
+ kfree(cur_func);
cur_func = temp_func;
}
}
sl->func = NULL;
*slot_cur = sl;
- debug ("%s - exit\n", __func__);
+ debug("%s - exit\n", __func__);
return 0;
}
* Output: bus added to the correct spot
* 0, -1, error
*/
-static int add_new_bus (struct bus_node *bus, struct resource_node *io, struct resource_node *mem, struct resource_node *pfmem, u8 parent_busno)
+static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct resource_node *mem, struct resource_node *pfmem, u8 parent_busno)
{
struct range_node *io_range = NULL;
struct range_node *mem_range = NULL;
/* Trying to find the parent bus number */
if (parent_busno != 0xFF) {
- cur_bus = ibmphp_find_res_bus (parent_busno);
+ cur_bus = ibmphp_find_res_bus(parent_busno);
if (!cur_bus) {
- err ("strange, cannot find bus which is supposed to be at the system... something is terribly wrong...\n");
+ err("strange, cannot find bus which is supposed to be at the system... something is terribly wrong...\n");
return -ENODEV;
}
- list_add (&bus->bus_list, &cur_bus->bus_list);
+ list_add(&bus->bus_list, &cur_bus->bus_list);
}
if (io) {
io_range = kzalloc(sizeof(*io_range), GFP_KERNEL);
if (!io_range) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
io_range->start = io->start;
if (mem) {
mem_range = kzalloc(sizeof(*mem_range), GFP_KERNEL);
if (!mem_range) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
mem_range->start = mem->start;
if (pfmem) {
pfmem_range = kzalloc(sizeof(*pfmem_range), GFP_KERNEL);
if (!pfmem_range) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
pfmem_range->start = pfmem->start;
* Parameters: bus_number of the primary bus
* Returns: bus_number of the secondary bus or 0xff in case of failure
*/
-static u8 find_sec_number (u8 primary_busno, u8 slotno)
+static u8 find_sec_number(u8 primary_busno, u8 slotno)
{
int min, max;
u8 busno;
struct bus_info *bus;
struct bus_node *bus_cur;
- bus = ibmphp_find_same_bus_num (primary_busno);
+ bus = ibmphp_find_same_bus_num(primary_busno);
if (!bus) {
- err ("cannot get slot range of the bus from the BIOS\n");
+ err("cannot get slot range of the bus from the BIOS\n");
return 0xff;
}
max = bus->slot_max;
min = bus->slot_min;
if ((slotno > max) || (slotno < min)) {
- err ("got the wrong range\n");
+ err("got the wrong range\n");
return 0xff;
}
busno = (u8) (slotno - (u8) min);
busno += primary_busno + 0x01;
- bus_cur = ibmphp_find_res_bus (busno);
+ bus_cur = ibmphp_find_res_bus(busno);
/* either there is no such bus number, or there are no ranges, which
* can only happen if we removed the bridged device in previous load
* of the driver, and now only have the skeleton bus struct
static int flags = 0; /* for testing */
-static void update_resources (struct bus_node *bus_cur, int type, int rangeno);
-static int once_over (void);
-static int remove_ranges (struct bus_node *, struct bus_node *);
-static int update_bridge_ranges (struct bus_node **);
-static int add_bus_range (int type, struct range_node *, struct bus_node *);
-static void fix_resources (struct bus_node *);
-static struct bus_node *find_bus_wprev (u8, struct bus_node **, u8);
+static void update_resources(struct bus_node *bus_cur, int type, int rangeno);
+static int once_over(void);
+static int remove_ranges(struct bus_node *, struct bus_node *);
+static int update_bridge_ranges(struct bus_node **);
+static int add_bus_range(int type, struct range_node *, struct bus_node *);
+static void fix_resources(struct bus_node *);
+static struct bus_node *find_bus_wprev(u8, struct bus_node **, u8);
static LIST_HEAD(gbuses);
-static struct bus_node * __init alloc_error_bus (struct ebda_pci_rsrc *curr, u8 busno, int flag)
+static struct bus_node * __init alloc_error_bus(struct ebda_pci_rsrc *curr, u8 busno, int flag)
{
struct bus_node *newbus;
if (!(curr) && !(flag)) {
- err ("NULL pointer passed\n");
+ err("NULL pointer passed\n");
return NULL;
}
newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL);
if (!newbus) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return NULL;
}
newbus->busno = busno;
else
newbus->busno = curr->bus_num;
- list_add_tail (&newbus->bus_list, &gbuses);
+ list_add_tail(&newbus->bus_list, &gbuses);
return newbus;
}
-static struct resource_node * __init alloc_resources (struct ebda_pci_rsrc *curr)
+static struct resource_node * __init alloc_resources(struct ebda_pci_rsrc *curr)
{
struct resource_node *rs;
if (!curr) {
- err ("NULL passed to allocate\n");
+ err("NULL passed to allocate\n");
return NULL;
}
rs = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!rs) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return NULL;
}
rs->busno = curr->bus_num;
return rs;
}
-static int __init alloc_bus_range (struct bus_node **new_bus, struct range_node **new_range, struct ebda_pci_rsrc *curr, int flag, u8 first_bus)
+static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node **new_range, struct ebda_pci_rsrc *curr, int flag, u8 first_bus)
{
struct bus_node *newbus;
struct range_node *newrange;
if (first_bus) {
newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL);
if (!newbus) {
- err ("out of system memory.\n");
+ err("out of system memory.\n");
return -ENOMEM;
}
newbus->busno = curr->bus_num;
newrange = kzalloc(sizeof(struct range_node), GFP_KERNEL);
if (!newrange) {
if (first_bus)
- kfree (newbus);
- err ("out of system memory\n");
+ kfree(newbus);
+ err("out of system memory\n");
return -ENOMEM;
}
newrange->start = curr->start_addr;
newrange->rangeno = 1;
else {
/* need to insert our range */
- add_bus_range (flag, newrange, newbus);
- debug ("%d resource Primary Bus inserted on bus %x [%x - %x]\n", flag, newbus->busno, newrange->start, newrange->end);
+ add_bus_range(flag, newrange, newbus);
+ debug("%d resource Primary Bus inserted on bus %x [%x - %x]\n", flag, newbus->busno, newrange->start, newrange->end);
}
switch (flag) {
if (first_bus)
newbus->noMemRanges = 1;
else {
- debug ("First Memory Primary on bus %x, [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ debug("First Memory Primary on bus %x, [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
++newbus->noMemRanges;
- fix_resources (newbus);
+ fix_resources(newbus);
}
break;
case IO:
if (first_bus)
newbus->noIORanges = 1;
else {
- debug ("First IO Primary on bus %x, [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ debug("First IO Primary on bus %x, [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
++newbus->noIORanges;
- fix_resources (newbus);
+ fix_resources(newbus);
}
break;
case PFMEM:
if (first_bus)
newbus->noPFMemRanges = 1;
else {
- debug ("1st PFMemory Primary on Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ debug("1st PFMemory Primary on Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
++newbus->noPFMemRanges;
- fix_resources (newbus);
+ fix_resources(newbus);
}
break;
* 2. If cannot allocate out of PFMem range, allocate from Mem ranges. PFmemFromMem
* are not sorted. (no need since use mem node). To not change the entire code, we
* also add mem node whenever this case happens so as not to change
- * ibmphp_check_mem_resource etc (and since it really is taking Mem resource)
+ * ibmphp_check_mem_resource etc(and since it really is taking Mem resource)
*/
/*****************************************************************************
* Input: ptr to the head of the resource list from EBDA
* Output: 0, -1 or error codes
***************************************************************************/
-int __init ibmphp_rsrc_init (void)
+int __init ibmphp_rsrc_init(void)
{
struct ebda_pci_rsrc *curr;
struct range_node *newrange = NULL;
struct bus_node *newbus = NULL;
struct bus_node *bus_cur;
struct bus_node *bus_prev;
- struct list_head *tmp;
struct resource_node *new_io = NULL;
struct resource_node *new_mem = NULL;
struct resource_node *new_pfmem = NULL;
int rc;
- struct list_head *tmp_ebda;
- list_for_each (tmp_ebda, &ibmphp_ebda_pci_rsrc_head) {
- curr = list_entry (tmp_ebda, struct ebda_pci_rsrc, ebda_pci_rsrc_list);
+ list_for_each_entry(curr, &ibmphp_ebda_pci_rsrc_head,
+ ebda_pci_rsrc_list) {
if (!(curr->rsrc_type & PCIDEVMASK)) {
/* EBDA still lists non PCI devices, so ignore... */
- debug ("this is not a PCI DEVICE in rsrc_init, please take care\n");
+ debug("this is not a PCI DEVICE in rsrc_init, please take care\n");
// continue;
}
/* memory */
if ((curr->rsrc_type & RESTYPE) == MMASK) {
/* no bus structure exists in place yet */
- if (list_empty (&gbuses)) {
+ if (list_empty(&gbuses)) {
rc = alloc_bus_range(&newbus, &newrange, curr, MEM, 1);
if (rc)
return rc;
- list_add_tail (&newbus->bus_list, &gbuses);
- debug ("gbuses = NULL, Memory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ list_add_tail(&newbus->bus_list, &gbuses);
+ debug("gbuses = NULL, Memory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
} else {
- bus_cur = find_bus_wprev (curr->bus_num, &bus_prev, 1);
+ bus_cur = find_bus_wprev(curr->bus_num, &bus_prev, 1);
/* found our bus */
if (bus_cur) {
- rc = alloc_bus_range (&bus_cur, &newrange, curr, MEM, 0);
+ rc = alloc_bus_range(&bus_cur, &newrange, curr, MEM, 0);
if (rc)
return rc;
} else {
if (rc)
return rc;
- list_add_tail (&newbus->bus_list, &gbuses);
- debug ("New Bus, Memory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ list_add_tail(&newbus->bus_list, &gbuses);
+ debug("New Bus, Memory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
}
}
} else if ((curr->rsrc_type & RESTYPE) == PFMASK) {
/* prefetchable memory */
- if (list_empty (&gbuses)) {
+ if (list_empty(&gbuses)) {
/* no bus structure exists in place yet */
rc = alloc_bus_range(&newbus, &newrange, curr, PFMEM, 1);
if (rc)
return rc;
- list_add_tail (&newbus->bus_list, &gbuses);
- debug ("gbuses = NULL, PFMemory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ list_add_tail(&newbus->bus_list, &gbuses);
+ debug("gbuses = NULL, PFMemory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
} else {
- bus_cur = find_bus_wprev (curr->bus_num, &bus_prev, 1);
+ bus_cur = find_bus_wprev(curr->bus_num, &bus_prev, 1);
if (bus_cur) {
/* found our bus */
- rc = alloc_bus_range (&bus_cur, &newrange, curr, PFMEM, 0);
+ rc = alloc_bus_range(&bus_cur, &newrange, curr, PFMEM, 0);
if (rc)
return rc;
} else {
rc = alloc_bus_range(&newbus, &newrange, curr, PFMEM, 1);
if (rc)
return rc;
- list_add_tail (&newbus->bus_list, &gbuses);
- debug ("1st Bus, PFMemory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ list_add_tail(&newbus->bus_list, &gbuses);
+ debug("1st Bus, PFMemory Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
}
}
} else if ((curr->rsrc_type & RESTYPE) == IOMASK) {
/* IO */
- if (list_empty (&gbuses)) {
+ if (list_empty(&gbuses)) {
/* no bus structure exists in place yet */
rc = alloc_bus_range(&newbus, &newrange, curr, IO, 1);
if (rc)
return rc;
- list_add_tail (&newbus->bus_list, &gbuses);
- debug ("gbuses = NULL, IO Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ list_add_tail(&newbus->bus_list, &gbuses);
+ debug("gbuses = NULL, IO Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
} else {
- bus_cur = find_bus_wprev (curr->bus_num, &bus_prev, 1);
+ bus_cur = find_bus_wprev(curr->bus_num, &bus_prev, 1);
if (bus_cur) {
- rc = alloc_bus_range (&bus_cur, &newrange, curr, IO, 0);
+ rc = alloc_bus_range(&bus_cur, &newrange, curr, IO, 0);
if (rc)
return rc;
} else {
rc = alloc_bus_range(&newbus, &newrange, curr, IO, 1);
if (rc)
return rc;
- list_add_tail (&newbus->bus_list, &gbuses);
- debug ("1st Bus, IO Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
+ list_add_tail(&newbus->bus_list, &gbuses);
+ debug("1st Bus, IO Primary Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end);
}
}
/* regular pci device resource */
if ((curr->rsrc_type & RESTYPE) == MMASK) {
/* Memory resource */
- new_mem = alloc_resources (curr);
+ new_mem = alloc_resources(curr);
if (!new_mem)
return -ENOMEM;
new_mem->type = MEM;
* assign a -1 and then update once the range
* actually appears...
*/
- if (ibmphp_add_resource (new_mem) < 0) {
- newbus = alloc_error_bus (curr, 0, 0);
+ if (ibmphp_add_resource(new_mem) < 0) {
+ newbus = alloc_error_bus(curr, 0, 0);
if (!newbus)
return -ENOMEM;
newbus->firstMem = new_mem;
++newbus->needMemUpdate;
new_mem->rangeno = -1;
}
- debug ("Memory resource for device %x, bus %x, [%x - %x]\n", new_mem->devfunc, new_mem->busno, new_mem->start, new_mem->end);
+ debug("Memory resource for device %x, bus %x, [%x - %x]\n", new_mem->devfunc, new_mem->busno, new_mem->start, new_mem->end);
} else if ((curr->rsrc_type & RESTYPE) == PFMASK) {
/* PFMemory resource */
- new_pfmem = alloc_resources (curr);
+ new_pfmem = alloc_resources(curr);
if (!new_pfmem)
return -ENOMEM;
new_pfmem->type = PFMEM;
new_pfmem->fromMem = 0;
- if (ibmphp_add_resource (new_pfmem) < 0) {
- newbus = alloc_error_bus (curr, 0, 0);
+ if (ibmphp_add_resource(new_pfmem) < 0) {
+ newbus = alloc_error_bus(curr, 0, 0);
if (!newbus)
return -ENOMEM;
newbus->firstPFMem = new_pfmem;
new_pfmem->rangeno = -1;
}
- debug ("PFMemory resource for device %x, bus %x, [%x - %x]\n", new_pfmem->devfunc, new_pfmem->busno, new_pfmem->start, new_pfmem->end);
+ debug("PFMemory resource for device %x, bus %x, [%x - %x]\n", new_pfmem->devfunc, new_pfmem->busno, new_pfmem->start, new_pfmem->end);
} else if ((curr->rsrc_type & RESTYPE) == IOMASK) {
/* IO resource */
- new_io = alloc_resources (curr);
+ new_io = alloc_resources(curr);
if (!new_io)
return -ENOMEM;
new_io->type = IO;
* Can assign a -1 and then update once the
* range actually appears...
*/
- if (ibmphp_add_resource (new_io) < 0) {
- newbus = alloc_error_bus (curr, 0, 0);
+ if (ibmphp_add_resource(new_io) < 0) {
+ newbus = alloc_error_bus(curr, 0, 0);
if (!newbus)
return -ENOMEM;
newbus->firstIO = new_io;
++newbus->needIOUpdate;
new_io->rangeno = -1;
}
- debug ("IO resource for device %x, bus %x, [%x - %x]\n", new_io->devfunc, new_io->busno, new_io->start, new_io->end);
+ debug("IO resource for device %x, bus %x, [%x - %x]\n", new_io->devfunc, new_io->busno, new_io->start, new_io->end);
}
}
}
- list_for_each (tmp, &gbuses) {
- bus_cur = list_entry (tmp, struct bus_node, bus_list);
+ list_for_each_entry(bus_cur, &gbuses, bus_list) {
/* This is to get info about PPB resources, since EBDA doesn't put this info into the primary bus info */
- rc = update_bridge_ranges (&bus_cur);
+ rc = update_bridge_ranges(&bus_cur);
if (rc)
return rc;
}
- return once_over (); /* This is to align ranges (so no -1) */
+ return once_over(); /* This is to align ranges (so no -1) */
}
/********************************************************************************
* Input: type of the resource, range to add, current bus
* Output: 0 or -1, bus and range ptrs
********************************************************************************/
-static int add_bus_range (int type, struct range_node *range, struct bus_node *bus_cur)
+static int add_bus_range(int type, struct range_node *range, struct bus_node *bus_cur)
{
struct range_node *range_cur = NULL;
struct range_node *range_prev;
range_cur = range_cur->next;
}
- update_resources (bus_cur, type, i_init + 1);
+ update_resources(bus_cur, type, i_init + 1);
return 0;
}
*
* Input: bus, type of the resource, the rangeno starting from which to update
******************************************************************************/
-static void update_resources (struct bus_node *bus_cur, int type, int rangeno)
+static void update_resources(struct bus_node *bus_cur, int type, int rangeno)
{
struct resource_node *res = NULL;
u8 eol = 0; /* end of list indicator */
}
}
-static void fix_me (struct resource_node *res, struct bus_node *bus_cur, struct range_node *range)
+static void fix_me(struct resource_node *res, struct bus_node *bus_cur, struct range_node *range)
{
- char * str = "";
+ char *str = "";
switch (res->type) {
case IO:
str = "io";
while (range) {
if ((res->start >= range->start) && (res->end <= range->end)) {
res->rangeno = range->rangeno;
- debug ("%s->rangeno in fix_resources is %d\n", str, res->rangeno);
+ debug("%s->rangeno in fix_resources is %d\n", str, res->rangeno);
switch (res->type) {
case IO:
--bus_cur->needIOUpdate;
* Input: current bus
* Output: none, list of resources for that bus are fixed if can be
*******************************************************************************/
-static void fix_resources (struct bus_node *bus_cur)
+static void fix_resources(struct bus_node *bus_cur)
{
struct range_node *range;
struct resource_node *res;
- debug ("%s - bus_cur->busno = %d\n", __func__, bus_cur->busno);
+ debug("%s - bus_cur->busno = %d\n", __func__, bus_cur->busno);
if (bus_cur->needIOUpdate) {
res = bus_cur->firstIO;
range = bus_cur->rangeIO;
- fix_me (res, bus_cur, range);
+ fix_me(res, bus_cur, range);
}
if (bus_cur->needMemUpdate) {
res = bus_cur->firstMem;
range = bus_cur->rangeMem;
- fix_me (res, bus_cur, range);
+ fix_me(res, bus_cur, range);
}
if (bus_cur->needPFMemUpdate) {
res = bus_cur->firstPFMem;
range = bus_cur->rangePFMem;
- fix_me (res, bus_cur, range);
+ fix_me(res, bus_cur, range);
}
}
* Output: ptrs assigned (to the node)
* 0 or -1
*******************************************************************************/
-int ibmphp_add_resource (struct resource_node *res)
+int ibmphp_add_resource(struct resource_node *res)
{
struct resource_node *res_cur;
struct resource_node *res_prev;
struct range_node *range_cur = NULL;
struct resource_node *res_start = NULL;
- debug ("%s - enter\n", __func__);
+ debug("%s - enter\n", __func__);
if (!res) {
- err ("NULL passed to add\n");
+ err("NULL passed to add\n");
return -ENODEV;
}
- bus_cur = find_bus_wprev (res->busno, NULL, 0);
+ bus_cur = find_bus_wprev(res->busno, NULL, 0);
if (!bus_cur) {
/* didn't find a bus, something's wrong!!! */
- debug ("no bus in the system, either pci_dev's wrong or allocation failed\n");
+ debug("no bus in the system, either pci_dev's wrong or allocation failed\n");
return -ENODEV;
}
res_start = bus_cur->firstPFMem;
break;
default:
- err ("cannot read the type of the resource to add... problem\n");
+ err("cannot read the type of the resource to add... problem\n");
return -EINVAL;
}
while (range_cur) {
res->rangeno = -1;
}
- debug ("The range is %d\n", res->rangeno);
+ debug("The range is %d\n", res->rangeno);
if (!res_start) {
/* no first{IO,Mem,Pfmem} on the bus, 1st IO/Mem/Pfmem resource ever */
switch (res->type) {
res_cur = res_start;
res_prev = NULL;
- debug ("res_cur->rangeno is %d\n", res_cur->rangeno);
+ debug("res_cur->rangeno is %d\n", res_cur->rangeno);
while (res_cur) {
if (res_cur->rangeno >= res->rangeno)
if (!res_cur) {
/* at the end of the resource list */
- debug ("i should be here, [%x - %x]\n", res->start, res->end);
+ debug("i should be here, [%x - %x]\n", res->start, res->end);
res_prev->nextRange = res;
res->next = NULL;
res->nextRange = NULL;
}
}
- debug ("%s - exit\n", __func__);
+ debug("%s - exit\n", __func__);
return 0;
}
* Output: modified resource list
* 0 or error code
****************************************************************************/
-int ibmphp_remove_resource (struct resource_node *res)
+int ibmphp_remove_resource(struct resource_node *res)
{
struct bus_node *bus_cur;
struct resource_node *res_cur = NULL;
struct resource_node *res_prev;
struct resource_node *mem_cur;
- char * type = "";
+ char *type = "";
if (!res) {
- err ("resource to remove is NULL\n");
+ err("resource to remove is NULL\n");
return -ENODEV;
}
- bus_cur = find_bus_wprev (res->busno, NULL, 0);
+ bus_cur = find_bus_wprev(res->busno, NULL, 0);
if (!bus_cur) {
- err ("cannot find corresponding bus of the io resource to remove bailing out...\n");
+ err("cannot find corresponding bus of the io resource to remove bailing out...\n");
return -ENODEV;
}
type = "pfmem";
break;
default:
- err ("unknown type for resource to remove\n");
+ err("unknown type for resource to remove\n");
return -EINVAL;
}
res_prev = NULL;
mem_cur = mem_cur->nextRange;
}
if (!mem_cur) {
- err ("cannot find corresponding mem node for pfmem...\n");
+ err("cannot find corresponding mem node for pfmem...\n");
return -EINVAL;
}
- ibmphp_remove_resource (mem_cur);
+ ibmphp_remove_resource(mem_cur);
if (!res_prev)
bus_cur->firstPFMemFromMem = res_cur->next;
else
res_prev->next = res_cur->next;
- kfree (res_cur);
+ kfree(res_cur);
return 0;
}
res_prev = res_cur;
res_cur = res_cur->nextRange;
}
if (!res_cur) {
- err ("cannot find pfmem to delete...\n");
+ err("cannot find pfmem to delete...\n");
return -EINVAL;
}
} else {
- err ("the %s resource is not in the list to be deleted...\n", type);
+ err("the %s resource is not in the list to be deleted...\n", type);
return -EINVAL;
}
}
break;
}
}
- kfree (res_cur);
+ kfree(res_cur);
return 0;
} else {
if (res_cur->next) {
res_prev->next = NULL;
res_prev->nextRange = NULL;
}
- kfree (res_cur);
+ kfree(res_cur);
return 0;
}
return 0;
}
-static struct range_node *find_range (struct bus_node *bus_cur, struct resource_node *res)
+static struct range_node *find_range(struct bus_node *bus_cur, struct resource_node *res)
{
struct range_node *range = NULL;
range = bus_cur->rangePFMem;
break;
default:
- err ("cannot read resource type in find_range\n");
+ err("cannot read resource type in find_range\n");
}
while (range) {
* Output: the correct start and end address are inputted into the resource node,
* 0 or -EINVAL
*****************************************************************************/
-int ibmphp_check_resource (struct resource_node *res, u8 bridge)
+int ibmphp_check_resource(struct resource_node *res, u8 bridge)
{
struct bus_node *bus_cur;
struct range_node *range = NULL;
} else
tmp_divide = res->len;
- bus_cur = find_bus_wprev (res->busno, NULL, 0);
+ bus_cur = find_bus_wprev(res->busno, NULL, 0);
if (!bus_cur) {
/* didn't find a bus, something's wrong!!! */
- debug ("no bus in the system, either pci_dev's wrong or allocation failed\n");
+ debug("no bus in the system, either pci_dev's wrong or allocation failed\n");
return -EINVAL;
}
- debug ("%s - enter\n", __func__);
- debug ("bus_cur->busno is %d\n", bus_cur->busno);
+ debug("%s - enter\n", __func__);
+ debug("bus_cur->busno is %d\n", bus_cur->busno);
/* This is a quick fix to not mess up with the code very much. i.e.,
* 2000-2fff, len = 1000, but when we compare, we need it to be fff */
noranges = bus_cur->noPFMemRanges;
break;
default:
- err ("wrong type of resource to check\n");
+ err("wrong type of resource to check\n");
return -EINVAL;
}
res_prev = NULL;
while (res_cur) {
- range = find_range (bus_cur, res_cur);
- debug ("%s - rangeno = %d\n", __func__, res_cur->rangeno);
+ range = find_range(bus_cur, res_cur);
+ debug("%s - rangeno = %d\n", __func__, res_cur->rangeno);
if (!range) {
- err ("no range for the device exists... bailing out...\n");
+ err("no range for the device exists... bailing out...\n");
return -EINVAL;
}
len_tmp = res_cur->start - 1 - range->start;
if ((res_cur->start != range->start) && (len_tmp >= res->len)) {
- debug ("len_tmp = %x\n", len_tmp);
+ debug("len_tmp = %x\n", len_tmp);
if ((len_tmp < len_cur) || (len_cur == 0)) {
}
if (flag && len_cur == res->len) {
- debug ("but we are not here, right?\n");
+ debug("but we are not here, right?\n");
res->start = start_cur;
res->len += 1; /* To restore the balance */
res->end = res->start + res->len - 1;
len_tmp = range->end - (res_cur->end + 1);
if ((range->end != res_cur->end) && (len_tmp >= res->len)) {
- debug ("len_tmp = %x\n", len_tmp);
+ debug("len_tmp = %x\n", len_tmp);
if ((len_tmp < len_cur) || (len_cur == 0)) {
if (((res_cur->end + 1) % tmp_divide) == 0) {
if ((!range) && (len_cur == 0)) {
/* have gone through the list of devices and ranges and haven't found n.e.thing */
- err ("no appropriate range.. bailing out...\n");
+ err("no appropriate range.. bailing out...\n");
return -EINVAL;
} else if (len_cur) {
res->start = start_cur;
}
if (!res_cur) {
- debug ("prev->rangeno = %d, noranges = %d\n", res_prev->rangeno, noranges);
+ debug("prev->rangeno = %d, noranges = %d\n", res_prev->rangeno, noranges);
if (res_prev->rangeno < noranges) {
/* if there're more ranges out there to check */
switch (res->type) {
if ((!range) && (len_cur == 0)) {
/* have gone through the list of devices and ranges and haven't found n.e.thing */
- err ("no appropriate range.. bailing out...\n");
+ err("no appropriate range.. bailing out...\n");
return -EINVAL;
} else if (len_cur) {
res->start = start_cur;
return 0;
} else {
/* have gone through the list of devices and haven't found n.e.thing */
- err ("no appropriate range.. bailing out...\n");
+ err("no appropriate range.. bailing out...\n");
return -EINVAL;
}
}
* Input: Bus
* Output: 0, -ENODEV
********************************************************************************/
-int ibmphp_remove_bus (struct bus_node *bus, u8 parent_busno)
+int ibmphp_remove_bus(struct bus_node *bus, u8 parent_busno)
{
struct resource_node *res_cur;
struct resource_node *res_tmp;
struct bus_node *prev_bus;
int rc;
- prev_bus = find_bus_wprev (parent_busno, NULL, 0);
+ prev_bus = find_bus_wprev(parent_busno, NULL, 0);
if (!prev_bus) {
- debug ("something terribly wrong. Cannot find parent bus to the one to remove\n");
+ debug("something terribly wrong. Cannot find parent bus to the one to remove\n");
return -ENODEV;
}
- debug ("In ibmphp_remove_bus... prev_bus->busno is %x\n", prev_bus->busno);
+ debug("In ibmphp_remove_bus... prev_bus->busno is %x\n", prev_bus->busno);
- rc = remove_ranges (bus, prev_bus);
+ rc = remove_ranges(bus, prev_bus);
if (rc)
return rc;
res_cur = res_cur->next;
else
res_cur = res_cur->nextRange;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus->firstIO = NULL;
res_cur = res_cur->next;
else
res_cur = res_cur->nextRange;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus->firstMem = NULL;
res_cur = res_cur->next;
else
res_cur = res_cur->nextRange;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus->firstPFMem = NULL;
res_tmp = res_cur;
res_cur = res_cur->next;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus->firstPFMemFromMem = NULL;
}
- list_del (&bus->bus_list);
- kfree (bus);
+ list_del(&bus->bus_list);
+ kfree(bus);
return 0;
}
* Input: current bus, previous bus
* Output: 0, -EINVAL
******************************************************************************/
-static int remove_ranges (struct bus_node *bus_cur, struct bus_node *bus_prev)
+static int remove_ranges(struct bus_node *bus_cur, struct bus_node *bus_prev)
{
struct range_node *range_cur;
struct range_node *range_tmp;
if (bus_cur->noIORanges) {
range_cur = bus_cur->rangeIO;
for (i = 0; i < bus_cur->noIORanges; i++) {
- if (ibmphp_find_resource (bus_prev, range_cur->start, &res, IO) < 0)
+ if (ibmphp_find_resource(bus_prev, range_cur->start, &res, IO) < 0)
return -EINVAL;
- ibmphp_remove_resource (res);
+ ibmphp_remove_resource(res);
range_tmp = range_cur;
range_cur = range_cur->next;
- kfree (range_tmp);
+ kfree(range_tmp);
range_tmp = NULL;
}
bus_cur->rangeIO = NULL;
if (bus_cur->noMemRanges) {
range_cur = bus_cur->rangeMem;
for (i = 0; i < bus_cur->noMemRanges; i++) {
- if (ibmphp_find_resource (bus_prev, range_cur->start, &res, MEM) < 0)
+ if (ibmphp_find_resource(bus_prev, range_cur->start, &res, MEM) < 0)
return -EINVAL;
- ibmphp_remove_resource (res);
+ ibmphp_remove_resource(res);
range_tmp = range_cur;
range_cur = range_cur->next;
- kfree (range_tmp);
+ kfree(range_tmp);
range_tmp = NULL;
}
bus_cur->rangeMem = NULL;
if (bus_cur->noPFMemRanges) {
range_cur = bus_cur->rangePFMem;
for (i = 0; i < bus_cur->noPFMemRanges; i++) {
- if (ibmphp_find_resource (bus_prev, range_cur->start, &res, PFMEM) < 0)
+ if (ibmphp_find_resource(bus_prev, range_cur->start, &res, PFMEM) < 0)
return -EINVAL;
- ibmphp_remove_resource (res);
+ ibmphp_remove_resource(res);
range_tmp = range_cur;
range_cur = range_cur->next;
- kfree (range_tmp);
+ kfree(range_tmp);
range_tmp = NULL;
}
bus_cur->rangePFMem = NULL;
* find the resource node in the bus
* Input: Resource needed, start address of the resource, type of resource
*/
-int ibmphp_find_resource (struct bus_node *bus, u32 start_address, struct resource_node **res, int flag)
+int ibmphp_find_resource(struct bus_node *bus, u32 start_address, struct resource_node **res, int flag)
{
struct resource_node *res_cur = NULL;
- char * type = "";
+ char *type = "";
if (!bus) {
- err ("The bus passed in NULL to find resource\n");
+ err("The bus passed in NULL to find resource\n");
return -ENODEV;
}
type = "pfmem";
break;
default:
- err ("wrong type of flag\n");
+ err("wrong type of flag\n");
return -EINVAL;
}
res_cur = res_cur->next;
}
if (!res_cur) {
- debug ("SOS...cannot find %s resource in the bus.\n", type);
+ debug("SOS...cannot find %s resource in the bus.\n", type);
return -EINVAL;
}
} else {
- debug ("SOS... cannot find %s resource in the bus.\n", type);
+ debug("SOS... cannot find %s resource in the bus.\n", type);
return -EINVAL;
}
}
if (*res)
- debug ("*res->start = %x\n", (*res)->start);
+ debug("*res->start = %x\n", (*res)->start);
return 0;
}
* Parameters: none
* Returns: none
***********************************************************************/
-void ibmphp_free_resources (void)
+void ibmphp_free_resources(void)
{
- struct bus_node *bus_cur = NULL;
+ struct bus_node *bus_cur = NULL, *next;
struct bus_node *bus_tmp;
struct range_node *range_cur;
struct range_node *range_tmp;
struct resource_node *res_cur;
struct resource_node *res_tmp;
- struct list_head *tmp;
- struct list_head *next;
int i = 0;
flags = 1;
- list_for_each_safe (tmp, next, &gbuses) {
- bus_cur = list_entry (tmp, struct bus_node, bus_list);
+ list_for_each_entry_safe(bus_cur, next, &gbuses, bus_list) {
if (bus_cur->noIORanges) {
range_cur = bus_cur->rangeIO;
for (i = 0; i < bus_cur->noIORanges; i++) {
break;
range_tmp = range_cur;
range_cur = range_cur->next;
- kfree (range_tmp);
+ kfree(range_tmp);
range_tmp = NULL;
}
}
break;
range_tmp = range_cur;
range_cur = range_cur->next;
- kfree (range_tmp);
+ kfree(range_tmp);
range_tmp = NULL;
}
}
break;
range_tmp = range_cur;
range_cur = range_cur->next;
- kfree (range_tmp);
+ kfree(range_tmp);
range_tmp = NULL;
}
}
res_cur = res_cur->next;
else
res_cur = res_cur->nextRange;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus_cur->firstIO = NULL;
res_cur = res_cur->next;
else
res_cur = res_cur->nextRange;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus_cur->firstMem = NULL;
res_cur = res_cur->next;
else
res_cur = res_cur->nextRange;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus_cur->firstPFMem = NULL;
res_tmp = res_cur;
res_cur = res_cur->next;
- kfree (res_tmp);
+ kfree(res_tmp);
res_tmp = NULL;
}
bus_cur->firstPFMemFromMem = NULL;
}
bus_tmp = bus_cur;
- list_del (&bus_cur->bus_list);
- kfree (bus_tmp);
+ list_del(&bus_cur->bus_list);
+ kfree(bus_tmp);
bus_tmp = NULL;
}
}
* a new Mem node
* This routine is called right after initialization
*******************************************************************************/
-static int __init once_over (void)
+static int __init once_over(void)
{
struct resource_node *pfmem_cur;
struct resource_node *pfmem_prev;
struct resource_node *mem;
struct bus_node *bus_cur;
- struct list_head *tmp;
- list_for_each (tmp, &gbuses) {
- bus_cur = list_entry (tmp, struct bus_node, bus_list);
+ list_for_each_entry(bus_cur, &gbuses, bus_list) {
if ((!bus_cur->rangePFMem) && (bus_cur->firstPFMem)) {
for (pfmem_cur = bus_cur->firstPFMem, pfmem_prev = NULL; pfmem_cur; pfmem_prev = pfmem_cur, pfmem_cur = pfmem_cur->next) {
pfmem_cur->fromMem = 1;
mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!mem) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
mem->type = MEM;
mem->start = pfmem_cur->start;
mem->end = pfmem_cur->end;
mem->len = pfmem_cur->len;
- if (ibmphp_add_resource (mem) < 0)
- err ("Trouble...trouble... EBDA allocated pfmem from mem, but system doesn't display it has this space... unless not PCI device...\n");
+ if (ibmphp_add_resource(mem) < 0)
+ err("Trouble...trouble... EBDA allocated pfmem from mem, but system doesn't display it has this space... unless not PCI device...\n");
pfmem_cur->rangeno = mem->rangeno;
} /* end for pfmem */
} /* end if */
return 0;
}
-int ibmphp_add_pfmem_from_mem (struct resource_node *pfmem)
+int ibmphp_add_pfmem_from_mem(struct resource_node *pfmem)
{
- struct bus_node *bus_cur = find_bus_wprev (pfmem->busno, NULL, 0);
+ struct bus_node *bus_cur = find_bus_wprev(pfmem->busno, NULL, 0);
if (!bus_cur) {
- err ("cannot find bus of pfmem to add...\n");
+ err("cannot find bus of pfmem to add...\n");
return -ENODEV;
}
* Parameters: bus_number
* Returns: Bus pointer or NULL
*/
-struct bus_node *ibmphp_find_res_bus (u8 bus_number)
+struct bus_node *ibmphp_find_res_bus(u8 bus_number)
{
- return find_bus_wprev (bus_number, NULL, 0);
+ return find_bus_wprev(bus_number, NULL, 0);
}
-static struct bus_node *find_bus_wprev (u8 bus_number, struct bus_node **prev, u8 flag)
+static struct bus_node *find_bus_wprev(u8 bus_number, struct bus_node **prev, u8 flag)
{
struct bus_node *bus_cur;
- struct list_head *tmp;
- struct list_head *tmp_prev;
- list_for_each (tmp, &gbuses) {
- tmp_prev = tmp->prev;
- bus_cur = list_entry (tmp, struct bus_node, bus_list);
+ list_for_each_entry(bus_cur, &gbuses, bus_list) {
if (flag)
- *prev = list_entry (tmp_prev, struct bus_node, bus_list);
+ *prev = list_prev_entry(bus_cur, bus_list);
if (bus_cur->busno == bus_number)
return bus_cur;
}
return NULL;
}
-void ibmphp_print_test (void)
+void ibmphp_print_test(void)
{
int i = 0;
struct bus_node *bus_cur = NULL;
struct range_node *range;
struct resource_node *res;
- struct list_head *tmp;
- debug_pci ("*****************START**********************\n");
+ debug_pci("*****************START**********************\n");
if ((!list_empty(&gbuses)) && flags) {
- err ("The GBUSES is not NULL?!?!?!?!?\n");
+ err("The GBUSES is not NULL?!?!?!?!?\n");
return;
}
- list_for_each (tmp, &gbuses) {
- bus_cur = list_entry (tmp, struct bus_node, bus_list);
+ list_for_each_entry(bus_cur, &gbuses, bus_list) {
debug_pci ("This is bus # %d. There are\n", bus_cur->busno);
debug_pci ("IORanges = %d\t", bus_cur->noIORanges);
debug_pci ("MemRanges = %d\t", bus_cur->noMemRanges);
if (bus_cur->rangeIO) {
range = bus_cur->rangeIO;
for (i = 0; i < bus_cur->noIORanges; i++) {
- debug_pci ("rangeno is %d\n", range->rangeno);
- debug_pci ("[%x - %x]\n", range->start, range->end);
+ debug_pci("rangeno is %d\n", range->rangeno);
+ debug_pci("[%x - %x]\n", range->start, range->end);
range = range->next;
}
}
- debug_pci ("The Mem Ranges are as follows:\n");
+ debug_pci("The Mem Ranges are as follows:\n");
if (bus_cur->rangeMem) {
range = bus_cur->rangeMem;
for (i = 0; i < bus_cur->noMemRanges; i++) {
- debug_pci ("rangeno is %d\n", range->rangeno);
- debug_pci ("[%x - %x]\n", range->start, range->end);
+ debug_pci("rangeno is %d\n", range->rangeno);
+ debug_pci("[%x - %x]\n", range->start, range->end);
range = range->next;
}
}
- debug_pci ("The PFMem Ranges are as follows:\n");
+ debug_pci("The PFMem Ranges are as follows:\n");
if (bus_cur->rangePFMem) {
range = bus_cur->rangePFMem;
for (i = 0; i < bus_cur->noPFMemRanges; i++) {
- debug_pci ("rangeno is %d\n", range->rangeno);
- debug_pci ("[%x - %x]\n", range->start, range->end);
+ debug_pci("rangeno is %d\n", range->rangeno);
+ debug_pci("[%x - %x]\n", range->start, range->end);
range = range->next;
}
}
- debug_pci ("The resources on this bus are as follows\n");
+ debug_pci("The resources on this bus are as follows\n");
- debug_pci ("IO...\n");
+ debug_pci("IO...\n");
if (bus_cur->firstIO) {
res = bus_cur->firstIO;
while (res) {
- debug_pci ("The range # is %d\n", res->rangeno);
- debug_pci ("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
- debug_pci ("[%x - %x], len=%x\n", res->start, res->end, res->len);
+ debug_pci("The range # is %d\n", res->rangeno);
+ debug_pci("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
+ debug_pci("[%x - %x], len=%x\n", res->start, res->end, res->len);
if (res->next)
res = res->next;
else if (res->nextRange)
break;
}
}
- debug_pci ("Mem...\n");
+ debug_pci("Mem...\n");
if (bus_cur->firstMem) {
res = bus_cur->firstMem;
while (res) {
- debug_pci ("The range # is %d\n", res->rangeno);
- debug_pci ("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
- debug_pci ("[%x - %x], len=%x\n", res->start, res->end, res->len);
+ debug_pci("The range # is %d\n", res->rangeno);
+ debug_pci("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
+ debug_pci("[%x - %x], len=%x\n", res->start, res->end, res->len);
if (res->next)
res = res->next;
else if (res->nextRange)
break;
}
}
- debug_pci ("PFMem...\n");
+ debug_pci("PFMem...\n");
if (bus_cur->firstPFMem) {
res = bus_cur->firstPFMem;
while (res) {
- debug_pci ("The range # is %d\n", res->rangeno);
- debug_pci ("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
- debug_pci ("[%x - %x], len=%x\n", res->start, res->end, res->len);
+ debug_pci("The range # is %d\n", res->rangeno);
+ debug_pci("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
+ debug_pci("[%x - %x], len=%x\n", res->start, res->end, res->len);
if (res->next)
res = res->next;
else if (res->nextRange)
}
}
- debug_pci ("PFMemFromMem...\n");
+ debug_pci("PFMemFromMem...\n");
if (bus_cur->firstPFMemFromMem) {
res = bus_cur->firstPFMemFromMem;
while (res) {
- debug_pci ("The range # is %d\n", res->rangeno);
- debug_pci ("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
- debug_pci ("[%x - %x], len=%x\n", res->start, res->end, res->len);
+ debug_pci("The range # is %d\n", res->rangeno);
+ debug_pci("The bus, devfnc is %d, %x\n", res->busno, res->devfunc);
+ debug_pci("[%x - %x], len=%x\n", res->start, res->end, res->len);
res = res->next;
}
}
}
- debug_pci ("***********************END***********************\n");
+ debug_pci("***********************END***********************\n");
}
-static int range_exists_already (struct range_node * range, struct bus_node * bus_cur, u8 type)
+static int range_exists_already(struct range_node *range, struct bus_node *bus_cur, u8 type)
{
- struct range_node * range_cur = NULL;
+ struct range_node *range_cur = NULL;
switch (type) {
case IO:
range_cur = bus_cur->rangeIO;
range_cur = bus_cur->rangePFMem;
break;
default:
- err ("wrong type passed to find out if range already exists\n");
+ err("wrong type passed to find out if range already exists\n");
return -ENODEV;
}
* behind them All these are TO DO.
* Also need to add more error checkings... (from fnc returns etc)
*/
-static int __init update_bridge_ranges (struct bus_node **bus)
+static int __init update_bridge_ranges(struct bus_node **bus)
{
u8 sec_busno, device, function, hdr_type, start_io_address, end_io_address;
u16 vendor_id, upper_io_start, upper_io_end, start_mem_address, end_mem_address;
return -ENODEV;
ibmphp_pci_bus->number = bus_cur->busno;
- debug ("inside %s\n", __func__);
- debug ("bus_cur->busno = %x\n", bus_cur->busno);
+ debug("inside %s\n", __func__);
+ debug("bus_cur->busno = %x\n", bus_cur->busno);
for (device = 0; device < 32; device++) {
for (function = 0x00; function < 0x08; function++) {
devfn = PCI_DEVFN(device, function);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_VENDOR_ID, &vendor_id);
if (vendor_id != PCI_VENDOR_ID_NOTVALID) {
/* found correct device!!! */
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_HEADER_TYPE, &hdr_type);
switch (hdr_type) {
case PCI_HEADER_TYPE_NORMAL:
temp++;
}
*/
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_busno);
- bus_sec = find_bus_wprev (sec_busno, NULL, 0);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_busno);
+ bus_sec = find_bus_wprev(sec_busno, NULL, 0);
/* this bus structure doesn't exist yet, PPB was configured during previous loading of ibmphp */
if (!bus_sec) {
- bus_sec = alloc_error_bus (NULL, sec_busno, 1);
+ bus_sec = alloc_error_bus(NULL, sec_busno, 1);
/* the rest will be populated during NVRAM call */
return 0;
}
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, &start_io_address);
- pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_IO_LIMIT, &end_io_address);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_IO_BASE_UPPER16, &upper_io_start);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_IO_LIMIT_UPPER16, &upper_io_end);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_IO_BASE, &start_io_address);
+ pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_IO_LIMIT, &end_io_address);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_IO_BASE_UPPER16, &upper_io_start);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_IO_LIMIT_UPPER16, &upper_io_end);
start_address = (start_io_address & PCI_IO_RANGE_MASK) << 8;
start_address |= (upper_io_start << 16);
end_address = (end_io_address & PCI_IO_RANGE_MASK) << 8;
if ((start_address) && (start_address <= end_address)) {
range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
if (!range) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
range->start = start_address;
range->end = end_address + 0xfff;
if (bus_sec->noIORanges > 0) {
- if (!range_exists_already (range, bus_sec, IO)) {
- add_bus_range (IO, range, bus_sec);
+ if (!range_exists_already(range, bus_sec, IO)) {
+ add_bus_range(IO, range, bus_sec);
++bus_sec->noIORanges;
} else {
- kfree (range);
+ kfree(range);
range = NULL;
}
} else {
bus_sec->rangeIO = range;
++bus_sec->noIORanges;
}
- fix_resources (bus_sec);
+ fix_resources(bus_sec);
- if (ibmphp_find_resource (bus_cur, start_address, &io, IO)) {
+ if (ibmphp_find_resource(bus_cur, start_address, &io, IO)) {
io = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!io) {
- kfree (range);
- err ("out of system memory\n");
+ kfree(range);
+ err("out of system memory\n");
return -ENOMEM;
}
io->type = IO;
io->start = start_address;
io->end = end_address + 0xfff;
io->len = io->end - io->start + 1;
- ibmphp_add_resource (io);
+ ibmphp_add_resource(io);
}
}
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &start_mem_address);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, &end_mem_address);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &start_mem_address);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, &end_mem_address);
start_address = 0x00000000 | (start_mem_address & PCI_MEMORY_RANGE_MASK) << 16;
end_address = 0x00000000 | (end_mem_address & PCI_MEMORY_RANGE_MASK) << 16;
range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
if (!range) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
range->start = start_address;
range->end = end_address + 0xfffff;
if (bus_sec->noMemRanges > 0) {
- if (!range_exists_already (range, bus_sec, MEM)) {
- add_bus_range (MEM, range, bus_sec);
+ if (!range_exists_already(range, bus_sec, MEM)) {
+ add_bus_range(MEM, range, bus_sec);
++bus_sec->noMemRanges;
} else {
- kfree (range);
+ kfree(range);
range = NULL;
}
} else {
++bus_sec->noMemRanges;
}
- fix_resources (bus_sec);
+ fix_resources(bus_sec);
- if (ibmphp_find_resource (bus_cur, start_address, &mem, MEM)) {
+ if (ibmphp_find_resource(bus_cur, start_address, &mem, MEM)) {
mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!mem) {
- kfree (range);
- err ("out of system memory\n");
+ kfree(range);
+ err("out of system memory\n");
return -ENOMEM;
}
mem->type = MEM;
mem->start = start_address;
mem->end = end_address + 0xfffff;
mem->len = mem->end - mem->start + 1;
- ibmphp_add_resource (mem);
+ ibmphp_add_resource(mem);
}
}
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &start_mem_address);
- pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &end_mem_address);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, PCI_PREF_BASE_UPPER32, &upper_start);
- pci_bus_read_config_dword (ibmphp_pci_bus, devfn, PCI_PREF_LIMIT_UPPER32, &upper_end);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_BASE, &start_mem_address);
+ pci_bus_read_config_word(ibmphp_pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &end_mem_address);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, PCI_PREF_BASE_UPPER32, &upper_start);
+ pci_bus_read_config_dword(ibmphp_pci_bus, devfn, PCI_PREF_LIMIT_UPPER32, &upper_end);
start_address = 0x00000000 | (start_mem_address & PCI_MEMORY_RANGE_MASK) << 16;
end_address = 0x00000000 | (end_mem_address & PCI_MEMORY_RANGE_MASK) << 16;
#if BITS_PER_LONG == 64
range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
if (!range) {
- err ("out of system memory\n");
+ err("out of system memory\n");
return -ENOMEM;
}
range->start = start_address;
range->end = end_address + 0xfffff;
if (bus_sec->noPFMemRanges > 0) {
- if (!range_exists_already (range, bus_sec, PFMEM)) {
- add_bus_range (PFMEM, range, bus_sec);
+ if (!range_exists_already(range, bus_sec, PFMEM)) {
+ add_bus_range(PFMEM, range, bus_sec);
++bus_sec->noPFMemRanges;
} else {
- kfree (range);
+ kfree(range);
range = NULL;
}
} else {
++bus_sec->noPFMemRanges;
}
- fix_resources (bus_sec);
- if (ibmphp_find_resource (bus_cur, start_address, &pfmem, PFMEM)) {
+ fix_resources(bus_sec);
+ if (ibmphp_find_resource(bus_cur, start_address, &pfmem, PFMEM)) {
pfmem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
if (!pfmem) {
- kfree (range);
- err ("out of system memory\n");
+ kfree(range);
+ err("out of system memory\n");
return -ENOMEM;
}
pfmem->type = PFMEM;
pfmem->len = pfmem->end - pfmem->start + 1;
pfmem->fromMem = 0;
- ibmphp_add_resource (pfmem);
+ ibmphp_add_resource(pfmem);
}
}
break;
#define MY_NAME "pci_hotplug"
-#define dbg(fmt, arg...) do { if (debug) printk(KERN_DEBUG "%s: %s: " fmt , MY_NAME , __func__ , ## arg); } while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
+#define dbg(fmt, arg...) do { if (debug) printk(KERN_DEBUG "%s: %s: " fmt, MY_NAME, __func__, ## arg); } while (0)
+#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
/* local variables */
u32 test;
int retval = 0;
- ltest = simple_strtoul (buf, NULL, 10);
+ ltest = simple_strtoul(buf, NULL, 10);
test = (u32)(ltest & 0xffffffff);
dbg("test = %d\n", test);
static struct hotplug_slot *get_slot_from_name(const char *name)
{
struct hotplug_slot *slot;
- struct list_head *tmp;
- list_for_each(tmp, &pci_hotplug_slot_list) {
- slot = list_entry(tmp, struct hotplug_slot, slot_list);
+ list_for_each_entry(slot, &pci_hotplug_slot_list, slot_list) {
if (strcmp(hotplug_slot_name(slot), name) == 0)
return slot;
}
#define dbg(format, arg...) \
do { \
if (pciehp_debug) \
- printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \
+ printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
} while (0)
#define err(format, arg...) \
- printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
+ printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
#define info(format, arg...) \
- printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
+ printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
#define warn(format, arg...) \
- printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
+ printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
#define ctrl_dbg(ctrl, format, arg...) \
do { \
#define PCIE_MODULE_NAME "pciehp"
-static int set_attention_status (struct hotplug_slot *slot, u8 value);
-static int enable_slot (struct hotplug_slot *slot);
-static int disable_slot (struct hotplug_slot *slot);
-static int get_power_status (struct hotplug_slot *slot, u8 *value);
-static int get_attention_status (struct hotplug_slot *slot, u8 *value);
-static int get_latch_status (struct hotplug_slot *slot, u8 *value);
-static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
-static int reset_slot (struct hotplug_slot *slot, int probe);
+static int set_attention_status(struct hotplug_slot *slot, u8 value);
+static int enable_slot(struct hotplug_slot *slot);
+static int disable_slot(struct hotplug_slot *slot);
+static int get_power_status(struct hotplug_slot *slot, u8 *value);
+static int get_attention_status(struct hotplug_slot *slot, u8 *value);
+static int get_latch_status(struct hotplug_slot *slot, u8 *value);
+static int get_adapter_status(struct hotplug_slot *slot, u8 *value);
+static int reset_slot(struct hotplug_slot *slot, int probe);
/**
* release_slot - free up the memory used by a slot
case STATIC_STATE:
p_slot->state = POWEROFF_STATE;
mutex_unlock(&p_slot->lock);
+ mutex_lock(&p_slot->hotplug_lock);
retval = pciehp_disable_slot(p_slot);
+ mutex_unlock(&p_slot->hotplug_lock);
mutex_lock(&p_slot->lock);
p_slot->state = STATIC_STATE;
break;
do { \
if (debug) \
printk(KERN_DEBUG "%s: " format "\n", \
- MY_NAME , ## arg); \
+ MY_NAME, ## arg); \
} while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
/* local variables */
static bool debug;
module_param(debug, bool, 0644);
MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
-static int enable_slot (struct hotplug_slot *slot);
-static int disable_slot (struct hotplug_slot *slot);
-static int set_attention_status (struct hotplug_slot *slot, u8 value);
-static int hardware_test (struct hotplug_slot *slot, u32 value);
-static int get_power_status (struct hotplug_slot *slot, u8 *value);
-static int get_attention_status (struct hotplug_slot *slot, u8 *value);
-static int get_latch_status (struct hotplug_slot *slot, u8 *value);
-static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
+static int enable_slot(struct hotplug_slot *slot);
+static int disable_slot(struct hotplug_slot *slot);
+static int set_attention_status(struct hotplug_slot *slot, u8 value);
+static int hardware_test(struct hotplug_slot *slot, u32 value);
+static int get_power_status(struct hotplug_slot *slot, u8 *value);
+static int get_attention_status(struct hotplug_slot *slot, u8 *value);
+static int get_latch_status(struct hotplug_slot *slot, u8 *value);
+static int get_adapter_status(struct hotplug_slot *slot, u8 *value);
static struct hotplug_slot_ops skel_hotplug_slot_ops = {
.enable_slot = enable_slot,
static void __exit cleanup_slots(void)
{
- struct list_head *tmp;
- struct list_head *next;
- struct slot *slot;
+ struct slot *slot, *next;
/*
* Unregister all of our slots with the pci_hotplug subsystem.
* Memory will be freed in release_slot() callback after slot's
* lifespan is finished.
*/
- list_for_each_safe(tmp, next, &slot_list) {
- slot = list_entry(tmp, struct slot, slot_list);
+ list_for_each_entry_safe(slot, next, &slot_list, slot_list) {
list_del(&slot->slot_list);
pci_hp_deregister(slot->hotplug_slot);
}
*/
static struct slot *find_php_slot(struct device_node *dn)
{
- struct list_head *tmp, *n;
- struct slot *slot;
+ struct slot *slot, *next;
- list_for_each_safe(tmp, n, &rpaphp_slot_head) {
- slot = list_entry(tmp, struct slot, rpaphp_slot_list);
+ list_for_each_entry_safe(slot, next, &rpaphp_slot_head,
+ rpaphp_slot_list) {
if (slot->dn == dn)
return slot;
}
do { \
if (rpaphp_debug) \
printk(KERN_DEBUG "%s: " format, \
- MY_NAME , ## arg); \
+ MY_NAME, ## arg); \
} while (0)
-#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
-#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
+#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
+#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
+#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
/* slot states */
int retval, level;
struct slot *slot = (struct slot *)hotplug_slot->private;
- retval = rtas_get_power_level (slot->power_domain, &level);
+ retval = rtas_get_power_level(slot->power_domain, &level);
if (!retval)
*value = level;
return retval;
static void __exit cleanup_slots(void)
{
- struct list_head *tmp, *n;
- struct slot *slot;
+ struct slot *slot, *next;
/*
* Unregister all of our slots with the pci_hotplug subsystem,
* memory will be freed in release_slot callback.
*/
- list_for_each_safe(tmp, n, &rpaphp_slot_head) {
- slot = list_entry(tmp, struct slot, rpaphp_slot_list);
+ list_for_each_entry_safe(slot, next, &rpaphp_slot_head,
+ rpaphp_slot_list) {
list_del(&slot->rpaphp_slot_list);
pci_hp_deregister(slot->hotplug_slot);
}
if (rpaphp_debug) {
struct pci_dev *dev;
dbg("%s: pci_devs of slot[%s]\n", __func__, slot->dn->full_name);
- list_for_each_entry (dev, &bus->devices, bus_list)
+ list_for_each_entry(dev, &bus->devices, bus_list)
dbg("\t%s\n", pci_name(dev));
}
}
}
struct slot *alloc_slot_struct(struct device_node *dn,
- int drc_index, char *drc_name, int power_domain)
+ int drc_index, char *drc_name, int power_domain)
{
struct slot *slot;
void zpci_exit_slot(struct zpci_dev *zdev)
{
- struct list_head *tmp, *n;
- struct slot *slot;
+ struct slot *slot, *next;
- list_for_each_safe(tmp, n, &s390_hotplug_slot_list) {
- slot = list_entry(tmp, struct slot, slot_list);
+ list_for_each_entry_safe(slot, next, &s390_hotplug_slot_list,
+ slot_list) {
if (slot->zdev != zdev)
continue;
list_del(&slot->slot_list);
if (!slot)
return retval;
- retval = sprintf (buf, "%s\n", slot->physical_path);
+ retval = sprintf(buf, "%s\n", slot->physical_path);
return retval;
}
}
if ((action == PCI_REQ_SLOT_DISABLE) && rc) {
- dev_dbg(&slot->pci_bus->self->dev,"remove failed rc = %d\n", rc);
+ dev_dbg(&slot->pci_bus->self->dev, "remove failed rc = %d\n", rc);
}
return rc;
/* free the ACPI resources for the slot */
if (SN_ACPI_BASE_SUPPORT() &&
- PCI_CONTROLLER(slot->pci_bus)->companion) {
+ PCI_CONTROLLER(slot->pci_bus)->companion) {
unsigned long long adr;
struct acpi_device *device;
acpi_handle phandle;
#define dbg(format, arg...) \
do { \
if (shpchp_debug) \
- printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \
+ printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
} while (0)
#define err(format, arg...) \
- printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
+ printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
#define info(format, arg...) \
- printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
+ printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
#define warn(format, arg...) \
- printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
+ printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
#define ctrl_dbg(ctrl, format, arg...) \
do { \
u8 presence_save;
u8 pwr_save;
struct controller *ctrl;
- struct hpc_ops *hpc_ops;
+ const struct hpc_ops *hpc_ops;
struct hotplug_slot *hotplug_slot;
struct list_head slot_list;
struct delayed_work work; /* work for button event */
int slot_num_inc; /* 1 or -1 */
struct pci_dev *pci_dev;
struct list_head slot_list;
- struct hpc_ops *hpc_ops;
+ const struct hpc_ops *hpc_ops;
wait_queue_head_t queue; /* sleep & wake process */
u8 slot_device_offset;
u32 pcix_misc2_reg; /* for amd pogo errata */
pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
}
/* restore MiscII register */
- pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
+ pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
pcix_misc2_temp |= SERRFATALENABLE_MASK;
#define SHPC_MODULE_NAME "shpchp"
-static int set_attention_status (struct hotplug_slot *slot, u8 value);
-static int enable_slot (struct hotplug_slot *slot);
-static int disable_slot (struct hotplug_slot *slot);
-static int get_power_status (struct hotplug_slot *slot, u8 *value);
-static int get_attention_status (struct hotplug_slot *slot, u8 *value);
-static int get_latch_status (struct hotplug_slot *slot, u8 *value);
-static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
+static int set_attention_status(struct hotplug_slot *slot, u8 value);
+static int enable_slot(struct hotplug_slot *slot);
+static int disable_slot(struct hotplug_slot *slot);
+static int get_power_status(struct hotplug_slot *slot, u8 *value);
+static int get_attention_status(struct hotplug_slot *slot, u8 *value);
+static int get_latch_status(struct hotplug_slot *slot, u8 *value);
+static int get_adapter_status(struct hotplug_slot *slot, u8 *value);
static struct hotplug_slot_ops shpchp_hotplug_slot_ops = {
.set_attention_status = set_attention_status,
void cleanup_slots(struct controller *ctrl)
{
- struct list_head *tmp;
- struct list_head *next;
- struct slot *slot;
+ struct slot *slot, *next;
- list_for_each_safe(tmp, next, &ctrl->slot_list) {
- slot = list_entry(tmp, struct slot, slot_list);
+ list_for_each_entry_safe(slot, next, &ctrl->slot_list, slot_list) {
list_del(&slot->slot_list);
cancel_delayed_work(&slot->work);
destroy_workqueue(slot->wq);
/*
* set_attention_status - Turns the Amber LED for a slot on, off or blink
*/
-static int set_attention_status (struct hotplug_slot *hotplug_slot, u8 status)
+static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status)
{
struct slot *slot = get_slot(hotplug_slot);
return 0;
}
-static int enable_slot (struct hotplug_slot *hotplug_slot)
+static int enable_slot(struct hotplug_slot *hotplug_slot)
{
struct slot *slot = get_slot(hotplug_slot);
return shpchp_sysfs_enable_slot(slot);
}
-static int disable_slot (struct hotplug_slot *hotplug_slot)
+static int disable_slot(struct hotplug_slot *hotplug_slot)
{
struct slot *slot = get_slot(hotplug_slot);
return shpchp_sysfs_disable_slot(slot);
}
-static int get_power_status (struct hotplug_slot *hotplug_slot, u8 *value)
+static int get_power_status(struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
return 0;
}
-static int get_attention_status (struct hotplug_slot *hotplug_slot, u8 *value)
+static int get_attention_status(struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
return 0;
}
-static int get_latch_status (struct hotplug_slot *hotplug_slot, u8 *value)
+static int get_latch_status(struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
return 0;
}
-static int get_adapter_status (struct hotplug_slot *hotplug_slot, u8 *value)
+static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
u8 slot_cmd = 0;
switch (value) {
- case 0 :
+ case 0:
slot_cmd = SET_ATTN_OFF; /* OFF */
break;
case 1:
return retval;
}
-static struct hpc_ops shpchp_hpc_ops = {
+static const struct hpc_ops shpchp_hpc_ops = {
.power_on_slot = hpc_power_on_slot,
.slot_enable = hpc_slot_enable,
.slot_disable = hpc_slot_disable,
/* A few routines that create sysfs entries for the hot plug controller */
-static ssize_t show_ctrl (struct device *dev, struct device_attribute *attr, char *buf)
+static ssize_t show_ctrl(struct device *dev, struct device_attribute *attr, char *buf)
{
struct pci_dev *pdev;
char *out = buf;
struct resource *res;
struct pci_bus *bus;
- pdev = container_of (dev, struct pci_dev, dev);
+ pdev = to_pci_dev(dev);
bus = pdev->subordinate;
out += sprintf(buf, "Free resources: memory\n");
return out - buf;
}
-static DEVICE_ATTR (ctrl, S_IRUGO, show_ctrl, NULL);
+static DEVICE_ATTR(ctrl, S_IRUGO, show_ctrl, NULL);
-int shpchp_create_ctrl_files (struct controller *ctrl)
+int shpchp_create_ctrl_files(struct controller *ctrl)
{
- return device_create_file (&ctrl->pci_dev->dev, &dev_attr_ctrl);
+ return device_create_file(&ctrl->pci_dev->dev, &dev_attr_ctrl);
}
void shpchp_remove_ctrl_files(struct controller *ctrl)
}
EXPORT_SYMBOL(pci_msi_enabled);
-void pci_msi_init_pci_dev(struct pci_dev *dev)
-{
-}
-
/**
* pci_enable_msi_range - configure device's MSI capability structure
* @dev: device to configure
struct device *dev;
struct pci_dev *pdev;
- dev = container_of(kobj, struct device, kobj);
+ dev = kobj_to_dev(kobj);
pdev = to_pci_dev(dev);
return find_smbios_instance_string(pdev, NULL, SMBIOS_ATTR_NONE) ?
{
struct device *dev;
- dev = container_of(kobj, struct device, kobj);
+ dev = kobj_to_dev(kobj);
if (device_has_dsm(dev))
return S_IRUGO;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_dev *dev = to_pci_dev(container_of(kobj, struct device,
- kobj));
+ struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
unsigned int size = 64;
loff_t init_off = off;
u8 *data = (u8 *) buf;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_dev *dev = to_pci_dev(container_of(kobj, struct device,
- kobj));
+ struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
unsigned int size = count;
loff_t init_off = off;
u8 *data = (u8 *) buf;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_dev *dev =
- to_pci_dev(container_of(kobj, struct device, kobj));
+ struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
if (off > bin_attr->size)
count = 0;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_dev *dev =
- to_pci_dev(container_of(kobj, struct device, kobj));
+ struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
if (off > bin_attr->size)
count = 0;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_bus *bus = to_pci_bus(container_of(kobj, struct device,
- kobj));
+ struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
/* Only support 1, 2 or 4 byte accesses */
if (count != 1 && count != 2 && count != 4)
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_bus *bus = to_pci_bus(container_of(kobj, struct device,
- kobj));
+ struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
/* Only support 1, 2 or 4 byte accesses */
if (count != 1 && count != 2 && count != 4)
struct bin_attribute *attr,
struct vm_area_struct *vma)
{
- struct pci_bus *bus = to_pci_bus(container_of(kobj, struct device,
- kobj));
+ struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
return pci_mmap_legacy_page_range(bus, vma, pci_mmap_mem);
}
struct bin_attribute *attr,
struct vm_area_struct *vma)
{
- struct pci_bus *bus = to_pci_bus(container_of(kobj, struct device,
- kobj));
+ struct pci_bus *bus = to_pci_bus(kobj_to_dev(kobj));
return pci_mmap_legacy_page_range(bus, vma, pci_mmap_io);
}
static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
struct vm_area_struct *vma, int write_combine)
{
- struct pci_dev *pdev = to_pci_dev(container_of(kobj,
- struct device, kobj));
+ struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
struct resource *res = attr->private;
enum pci_mmap_state mmap_type;
resource_size_t start, end;
struct bin_attribute *attr, char *buf,
loff_t off, size_t count, bool write)
{
- struct pci_dev *pdev = to_pci_dev(container_of(kobj,
- struct device, kobj));
+ struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
struct resource *res = attr->private;
unsigned long port = off;
int i;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_dev *pdev = to_pci_dev(container_of(kobj, struct device, kobj));
+ struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
if ((off == 0) && (*buf == '0') && (count == 2))
pdev->rom_attr_enabled = 0;
struct bin_attribute *bin_attr, char *buf,
loff_t off, size_t count)
{
- struct pci_dev *pdev = to_pci_dev(container_of(kobj, struct device, kobj));
+ struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
void __iomem *rom;
size_t size;
if (!sysfs_initialized)
return -EACCES;
- if (pdev->cfg_size < PCI_CFG_SPACE_EXP_SIZE)
- retval = sysfs_create_bin_file(&pdev->dev.kobj, &pci_config_attr);
- else
+ if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
retval = sysfs_create_bin_file(&pdev->dev.kobj, &pcie_config_attr);
+ else
+ retval = sysfs_create_bin_file(&pdev->dev.kobj, &pci_config_attr);
if (retval)
goto err;
err_resource_files:
pci_remove_resource_files(pdev);
err_config_file:
- if (pdev->cfg_size < PCI_CFG_SPACE_EXP_SIZE)
- sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
- else
+ if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
sysfs_remove_bin_file(&pdev->dev.kobj, &pcie_config_attr);
+ else
+ sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
err:
return retval;
}
pci_remove_capabilities_sysfs(pdev);
- if (pdev->cfg_size < PCI_CFG_SPACE_EXP_SIZE)
- sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
- else
+ if (pdev->cfg_size > PCI_CFG_SPACE_SIZE)
sysfs_remove_bin_file(&pdev->dev.kobj, &pcie_config_attr);
+ else
+ sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
pci_remove_resource_files(pdev);
static umode_t pci_dev_attrs_are_visible(struct kobject *kobj,
struct attribute *a, int n)
{
- struct device *dev = container_of(kobj, struct device, kobj);
+ struct device *dev = kobj_to_dev(kobj);
struct pci_dev *pdev = to_pci_dev(dev);
if (a == &vga_attr.attr)
static umode_t pci_dev_hp_attrs_are_visible(struct kobject *kobj,
struct attribute *a, int n)
{
- struct device *dev = container_of(kobj, struct device, kobj);
+ struct device *dev = kobj_to_dev(kobj);
struct pci_dev *pdev = to_pci_dev(dev);
if (pdev->is_virtfn)
static umode_t sriov_attrs_are_visible(struct kobject *kobj,
struct attribute *a, int n)
{
- struct device *dev = container_of(kobj, struct device, kobj);
+ struct device *dev = kobj_to_dev(kobj);
if (!dev_is_pf(dev))
return 0;
static void pcim_release(struct device *gendev, void *res)
{
- struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
+ struct pci_dev *dev = to_pci_dev(gendev);
struct pci_devres *this = res;
int i;
* is the default implementation. Architecture implementations can
* override this.
*/
-void __weak pcibios_disable_device (struct pci_dev *dev) {}
+void __weak pcibios_disable_device(struct pci_dev *dev) {}
/**
* pcibios_penalize_isa_irq - penalize an ISA IRQ
#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
-void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
-static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif
static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
u32 header_log1;
u32 header_log2;
u32 header_log3;
- u16 domain;
+ u32 domain;
};
struct aer_error {
struct list_head list;
- u16 domain;
+ u32 domain;
unsigned int bus;
unsigned int devfn;
int pos_cap_err;
/* Protect einjected and pci_bus_ops_list */
static DEFINE_SPINLOCK(inject_lock);
-static void aer_error_init(struct aer_error *err, u16 domain,
+static void aer_error_init(struct aer_error *err, u32 domain,
unsigned int bus, unsigned int devfn,
int pos_cap_err)
{
}
/* inject_lock must be held before calling */
-static struct aer_error *__find_aer_error(u16 domain, unsigned int bus,
+static struct aer_error *__find_aer_error(u32 domain, unsigned int bus,
unsigned int devfn)
{
struct aer_error *err;
int domain = pci_domain_nr(dev->bus);
if (domain < 0)
return NULL;
- return __find_aer_error((u16)domain, dev->bus->number, dev->devfn);
+ return __find_aer_error(domain, dev->bus->number, dev->devfn);
}
/* inject_lock must be held before calling */
domain = pci_domain_nr(bus);
if (domain < 0)
goto out;
- err = __find_aer_error((u16)domain, bus->number, devfn);
+ err = __find_aer_error(domain, bus->number, devfn);
if (!err)
goto out;
domain = pci_domain_nr(bus);
if (domain < 0)
goto out;
- err = __find_aer_error((u16)domain, bus->number, devfn);
+ err = __find_aer_error(domain, bus->number, devfn);
if (!err)
goto out;
u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
int ret = 0;
- dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn);
+ dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
if (!dev)
return -ENODEV;
rpdev = pcie_find_root_port(dev);
!dev->driver->err_handler ||
!dev->driver->err_handler->error_detected) {
if (result_data->state == pci_channel_io_frozen &&
- !(dev->hdr_type & PCI_HEADER_TYPE_BRIDGE)) {
+ dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
/*
* In case of fatal recovery, if one of down-
* stream device has no driver. We might be
* without recovery.
*/
- if (!(dev->hdr_type & PCI_HEADER_TYPE_BRIDGE))
+ if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
vote = PCI_ERS_RESULT_NO_AER_DRIVER;
else
vote = PCI_ERS_RESULT_NONE;
else
result_data.result = PCI_ERS_RESULT_RECOVERED;
- if (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE) {
+ if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
/*
* If the error is reported by a bridge, we think this error
* is related to the downstream link of the bridge, so we
pci_ers_result_t status;
struct pcie_port_service_driver *driver;
- if (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE) {
+ if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
/* Reset this port for all subordinates */
udev = dev;
} else {
&info->mask);
if (!(info->status & ~info->mask))
return 0;
- } else if (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE ||
+ } else if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
info->severity == AER_NONFATAL) {
/* Link is still healthy for IO reads */
{
struct pci_dev *pdev = to_pci_dev(dev);
struct pcie_link_state *link, *root = pdev->link_state->root;
- u32 val, state = 0;
-
- if (kstrtouint(buf, 10, &val))
- return -EINVAL;
+ u32 state;
if (aspm_disabled)
return -EPERM;
- if (n < 1 || val > 3)
- return -EINVAL;
- /* Convert requested state to ASPM state */
- if (val & PCIE_LINK_STATE_L0S)
- state |= ASPM_STATE_L0S;
- if (val & PCIE_LINK_STATE_L1)
- state |= ASPM_STATE_L1;
+ if (kstrtouint(buf, 10, &state))
+ return -EINVAL;
+ if ((state & ~ASPM_STATE_ALL) != 0)
+ return -EINVAL;
down_read(&pci_bus_sem);
mutex_lock(&aspm_lock);
int pos = PCI_CFG_SPACE_SIZE;
if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
- goto fail;
+ return PCI_CFG_SPACE_SIZE;
if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
- goto fail;
+ return PCI_CFG_SPACE_SIZE;
return PCI_CFG_SPACE_EXP_SIZE;
-
- fail:
- return PCI_CFG_SPACE_SIZE;
}
int pci_cfg_space_size(struct pci_dev *dev)
if (class == PCI_CLASS_BRIDGE_HOST)
return pci_cfg_space_size_ext(dev);
- if (!pci_is_pcie(dev)) {
- pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
- if (!pos)
- goto fail;
+ if (pci_is_pcie(dev))
+ return pci_cfg_space_size_ext(dev);
- pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
- if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
- goto fail;
- }
+ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+ if (!pos)
+ return PCI_CFG_SPACE_SIZE;
- return pci_cfg_space_size_ext(dev);
+ pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
+ if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
+ return pci_cfg_space_size_ext(dev);
- fail:
return PCI_CFG_SPACE_SIZE;
}
#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
-void pci_msi_setup_pci_dev(struct pci_dev *dev)
+static void pci_msi_setup_pci_dev(struct pci_dev *dev)
{
/*
* Disable the MSI hardware to avoid screaming interrupts
/* "Unknown power state" */
dev->current_state = PCI_UNKNOWN;
- pci_msi_setup_pci_dev(dev);
-
/* Early fixups, before probing the BARs */
pci_fixup_device(pci_fixup_early, dev);
/* device class may be changed after fixup */
/* Enhanced Allocation */
pci_ea_init(dev);
- /* MSI/MSI-X list */
- pci_msi_init_pci_dev(dev);
+ /* Setup MSI caps & disable MSI/MSI-X interrupts */
+ pci_msi_setup_pci_dev(dev);
/* Buffers for saving PCIe and PCI-X capabilities */
pci_allocate_cap_save_buffers(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
+/*
+ * This chip can cause bus lockups if config addresses above 0x600
+ * are read or written.
+ */
+static void quirk_nfp6000(struct pci_dev *dev)
+{
+ dev->cfg_size = 0x600;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
+
/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
static void quirk_extend_bar_to_page(struct pci_dev *dev)
{
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
PCI_DEVICE_ID_JMICRON_JMB388_ESD,
quirk_dma_func1_alias);
+/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
+DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
+ 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
+ quirk_dma_func1_alias);
/*
* Some devices DMA with the wrong devfn, not just the wrong function.
do {
void __iomem *pds;
/* Standard PCI ROMs start out with these bytes 55 AA */
- if (readb(image) != 0x55) {
- dev_err(&pdev->dev, "Invalid ROM contents\n");
+ if (readw(image) != 0xAA55) {
+ dev_err(&pdev->dev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n",
+ readw(image));
break;
}
- if (readb(image + 1) != 0xAA)
- break;
- /* get the PCI data structure and check its signature */
+ /* get the PCI data structure and check its "PCIR" signature */
pds = image + readw(image + 24);
- if (readb(pds) != 'P')
- break;
- if (readb(pds + 1) != 'C')
- break;
- if (readb(pds + 2) != 'I')
- break;
- if (readb(pds + 3) != 'R')
+ if (readl(pds) != 0x52494350) {
+ dev_err(&pdev->dev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n",
+ readl(pds));
break;
+ }
last_image = readb(pds + 21) & 0x80;
length = readw(pds + 16);
image += length * 512;
+ /* Avoid iterating through memory outside the resource window */
+ if (image > rom + size)
+ break;
} while (length && !last_image);
/* never return a size larger than the PCI resource window */
* @msi_free: Domain specific function to free a MSI interrupts
* @msi_check: Callback for verification of the domain/info/dev data
* @msi_prepare: Prepare the allocation of the interrupts in the domain
- * @msi_finish: Optional callbacl to finalize the allocation
+ * @msi_finish: Optional callback to finalize the allocation
* @set_desc: Set the msi descriptor for an interrupt
* @handle_error: Optional error handler if the allocation fails
*
* msi_create_irq_domain() and related interfaces
*
* @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error
- * are callbacks used by msi_irq_domain_alloc_irqs() and related
+ * are callbacks used by msi_domain_alloc_irqs() and related
* interfaces which are based on msi_desc.
*/
struct msi_domain_ops {
int of_pci_get_host_bridge_resources(struct device_node *dev,
unsigned char busno, unsigned char bus_max,
struct list_head *resources, resource_size_t *io_base);
+#else
+static inline int of_pci_get_host_bridge_resources(struct device_node *dev,
+ unsigned char busno, unsigned char bus_max,
+ struct list_head *resources, resource_size_t *io_base)
+{
+ return -EINVAL;
+}
#endif
#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
u16 entry; /* driver uses to specify entry, OS writes */
};
-void pci_msi_setup_pci_dev(struct pci_dev *dev);
-
#ifdef CONFIG_PCI_MSI
int pci_msi_vec_count(struct pci_dev *dev);
void pci_msi_shutdown(struct pci_dev *dev);
#define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff
#define PCI_VENDOR_ID_NETRONOME 0x19ee
+#define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200
+#define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
+#define PCI_DEVICE_ID_NETRONOME_NFP4000 0x4000
+#define PCI_DEVICE_ID_NETRONOME_NFP6000 0x6000
+#define PCI_DEVICE_ID_NETRONOME_NFP6000_VF 0x6003
#define PCI_VENDOR_ID_QMI 0x1a32
__irq_set_handler(virq, handler, 0, handler_name);
irq_set_handler_data(virq, handler_data);
}
+EXPORT_SYMBOL(irq_domain_set_info);
/**
* irq_domain_reset_irq_data - Clear hwirq, chip and chip_data in @irq_data
if (irq_find_mapping(domain, hwirq) > 0)
return -EEXIST;
- ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
- if (ret < 0)
- return ret;
+ if (domain->parent) {
+ ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
+ if (ret < 0)
+ return ret;
+ }
for (i = 0; i < nr_irqs; i++) {
ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
projects / cascardo / linux.git / commitdiff