RDMA/ocrdma: The kernel has a perfectly good BIT() macro - use it

No need to re-invent the wheel here

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>

diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
index 0ac34cb..638bff1 100644 (file)
--- a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
@@ -561,8 +561,8 @@ static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
        cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
        cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 
-       cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
-       cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
+       cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
+       cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
 
        cmd->async_cqid_ringsize = cq->id;
        cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<

diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_sli.h b/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
index 904989e..c521261 100644 (file)
--- a/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
@@ -28,8 +28,6 @@
 #ifndef __OCRDMA_SLI_H__
 #define __OCRDMA_SLI_H__
 
-#define Bit(_b) (1 << (_b))
-
 enum {
        OCRDMA_ASIC_GEN_SKH_R = 0x04,
        OCRDMA_ASIC_GEN_LANCER = 0x0B
@@ -238,7 +236,7 @@ struct ocrdma_mqe_sge {
 
 enum {
        OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
-       OCRDMA_MQE_HDR_EMB_MASK         = Bit(0),
+       OCRDMA_MQE_HDR_EMB_MASK         = BIT(0),
        OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
        OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
        OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
@@ -304,7 +302,7 @@ struct ocrdma_create_eq_req {
 };
 
 enum {
-       OCRDMA_CREATE_EQ_VALID  = Bit(29),
+       OCRDMA_CREATE_EQ_VALID  = BIT(29),
        OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
        OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 };
@@ -322,13 +320,13 @@ enum {
        OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
        OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
        OCRDMA_MCQE_CONS_SHIFT          = 27,
-       OCRDMA_MCQE_CONS_MASK           = Bit(27),
+       OCRDMA_MCQE_CONS_MASK           = BIT(27),
        OCRDMA_MCQE_CMPL_SHIFT          = 28,
-       OCRDMA_MCQE_CMPL_MASK           = Bit(28),
+       OCRDMA_MCQE_CMPL_MASK           = BIT(28),
        OCRDMA_MCQE_AE_SHIFT            = 30,
-       OCRDMA_MCQE_AE_MASK             = Bit(30),
+       OCRDMA_MCQE_AE_MASK             = BIT(30),
        OCRDMA_MCQE_VALID_SHIFT         = 31,
-       OCRDMA_MCQE_VALID_MASK          = Bit(31)
+       OCRDMA_MCQE_VALID_MASK          = BIT(31)
 };
 
 struct ocrdma_mcqe {
@@ -339,13 +337,13 @@ struct ocrdma_mcqe {
 };
 
 enum {
-       OCRDMA_AE_MCQE_QPVALID          = Bit(31),
+       OCRDMA_AE_MCQE_QPVALID          = BIT(31),
        OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 
-       OCRDMA_AE_MCQE_CQVALID          = Bit(31),
+       OCRDMA_AE_MCQE_CQVALID          = BIT(31),
        OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
-       OCRDMA_AE_MCQE_VALID            = Bit(31),
-       OCRDMA_AE_MCQE_AE               = Bit(30),
+       OCRDMA_AE_MCQE_VALID            = BIT(31),
+       OCRDMA_AE_MCQE_AE               = BIT(30),
        OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
        OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
                                        0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
@@ -386,9 +384,9 @@ enum {
        OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
                                        OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
        OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
-       OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = Bit(30),
+       OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = BIT(30),
        OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
-       OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = Bit(31)
+       OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = BIT(31)
 };
 
 struct ocrdma_ae_mpa_mcqe {
@@ -412,9 +410,9 @@ enum {
        OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
                                OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
        OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
-       OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = Bit(30),
+       OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = BIT(30),
        OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
-       OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = Bit(31)
+       OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = BIT(31)
 };
 
 struct ocrdma_ae_qp_mcqe {
@@ -449,9 +447,9 @@ enum OCRDMA_ASYNC_EVENT_TYPE {
 /* mailbox command request and responses */
 enum {
        OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
-       OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = Bit(2),
+       OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = BIT(2),
        OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
-       OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = Bit(3),
+       OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = BIT(3),
        OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
        OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
                                OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
@@ -672,9 +670,9 @@ enum {
        OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 
        OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
-       OCRDMA_CREATE_CQ_COALESCWM_MASK         = Bit(13) | Bit(12),
-       OCRDMA_CREATE_CQ_FLAGS_NODELAY          = Bit(14),
-       OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = Bit(15),
+       OCRDMA_CREATE_CQ_COALESCWM_MASK         = BIT(13) | BIT(12),
+       OCRDMA_CREATE_CQ_FLAGS_NODELAY          = BIT(14),
+       OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = BIT(15),
 
        OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
        OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
@@ -687,8 +685,8 @@ enum {
        OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 
        OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
-       OCRDMA_CREATE_CQ_FLAGS_VALID            = Bit(29),
-       OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = Bit(31),
+       OCRDMA_CREATE_CQ_FLAGS_VALID            = BIT(29),
+       OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = BIT(31),
        OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
                                        OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
                                        OCRDMA_CREATE_CQ_FLAGS_NODELAY
@@ -731,8 +729,8 @@ enum {
        OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
        OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
        OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
-       OCRDMA_CREATE_MQ_VALID                  = Bit(31),
-       OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = Bit(0)
+       OCRDMA_CREATE_MQ_VALID                  = BIT(31),
+       OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = BIT(0)
 };
 
 struct ocrdma_create_mq_req {
@@ -783,7 +781,7 @@ enum {
        OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
        OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
        OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
-       OCRDMA_CREATE_QP_REQ_QPT_MASK           = Bit(31) | Bit(30) | Bit(29),
+       OCRDMA_CREATE_QP_REQ_QPT_MASK           = BIT(31) | BIT(30) | BIT(29),
 
        OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
        OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
@@ -798,23 +796,23 @@ enum {
                                        OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 
        OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
-       OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = Bit(0),
+       OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = BIT(0),
        OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
-       OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = Bit(1),
+       OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = BIT(1),
        OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
-       OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = Bit(2),
+       OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = BIT(2),
        OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
-       OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = Bit(3),
+       OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = BIT(3),
        OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
-       OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = Bit(4),
+       OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = BIT(4),
        OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
-       OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = Bit(5),
+       OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = BIT(5),
        OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
-       OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = Bit(6),
+       OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = BIT(6),
        OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
-       OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = Bit(7),
+       OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = BIT(7),
        OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
-       OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = Bit(8),
+       OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = BIT(8),
        OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
        OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
                                OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
@@ -927,7 +925,7 @@ enum {
        OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
                                OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
 
-       OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = Bit(0),
+       OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = BIT(0),
        OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
        OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
                                OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
@@ -964,38 +962,38 @@ enum {
        OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
        OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
 
-       OCRDMA_QP_PARA_QPS_VALID        = Bit(0),
-       OCRDMA_QP_PARA_SQD_ASYNC_VALID  = Bit(1),
-       OCRDMA_QP_PARA_PKEY_VALID       = Bit(2),
-       OCRDMA_QP_PARA_QKEY_VALID       = Bit(3),
-       OCRDMA_QP_PARA_PMTU_VALID       = Bit(4),
-       OCRDMA_QP_PARA_ACK_TO_VALID     = Bit(5),
-       OCRDMA_QP_PARA_RETRY_CNT_VALID  = Bit(6),
-       OCRDMA_QP_PARA_RRC_VALID        = Bit(7),
-       OCRDMA_QP_PARA_RQPSN_VALID      = Bit(8),
-       OCRDMA_QP_PARA_MAX_IRD_VALID    = Bit(9),
-       OCRDMA_QP_PARA_MAX_ORD_VALID    = Bit(10),
-       OCRDMA_QP_PARA_RNT_VALID        = Bit(11),
-       OCRDMA_QP_PARA_SQPSN_VALID      = Bit(12),
-       OCRDMA_QP_PARA_DST_QPN_VALID    = Bit(13),
-       OCRDMA_QP_PARA_MAX_WQE_VALID    = Bit(14),
-       OCRDMA_QP_PARA_MAX_RQE_VALID    = Bit(15),
-       OCRDMA_QP_PARA_SGE_SEND_VALID   = Bit(16),
-       OCRDMA_QP_PARA_SGE_RECV_VALID   = Bit(17),
-       OCRDMA_QP_PARA_SGE_WR_VALID     = Bit(18),
-       OCRDMA_QP_PARA_INB_RDEN_VALID   = Bit(19),
-       OCRDMA_QP_PARA_INB_WREN_VALID   = Bit(20),
-       OCRDMA_QP_PARA_FLOW_LBL_VALID   = Bit(21),
-       OCRDMA_QP_PARA_BIND_EN_VALID    = Bit(22),
-       OCRDMA_QP_PARA_ZLKEY_EN_VALID   = Bit(23),
-       OCRDMA_QP_PARA_FMR_EN_VALID     = Bit(24),
-       OCRDMA_QP_PARA_INBAT_EN_VALID   = Bit(25),
-       OCRDMA_QP_PARA_VLAN_EN_VALID    = Bit(26),
-
-       OCRDMA_MODIFY_QP_FLAGS_RD       = Bit(0),
-       OCRDMA_MODIFY_QP_FLAGS_WR       = Bit(1),
-       OCRDMA_MODIFY_QP_FLAGS_SEND     = Bit(2),
-       OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = Bit(3)
+       OCRDMA_QP_PARA_QPS_VALID        = BIT(0),
+       OCRDMA_QP_PARA_SQD_ASYNC_VALID  = BIT(1),
+       OCRDMA_QP_PARA_PKEY_VALID       = BIT(2),
+       OCRDMA_QP_PARA_QKEY_VALID       = BIT(3),
+       OCRDMA_QP_PARA_PMTU_VALID       = BIT(4),
+       OCRDMA_QP_PARA_ACK_TO_VALID     = BIT(5),
+       OCRDMA_QP_PARA_RETRY_CNT_VALID  = BIT(6),
+       OCRDMA_QP_PARA_RRC_VALID        = BIT(7),
+       OCRDMA_QP_PARA_RQPSN_VALID      = BIT(8),
+       OCRDMA_QP_PARA_MAX_IRD_VALID    = BIT(9),
+       OCRDMA_QP_PARA_MAX_ORD_VALID    = BIT(10),
+       OCRDMA_QP_PARA_RNT_VALID        = BIT(11),
+       OCRDMA_QP_PARA_SQPSN_VALID      = BIT(12),
+       OCRDMA_QP_PARA_DST_QPN_VALID    = BIT(13),
+       OCRDMA_QP_PARA_MAX_WQE_VALID    = BIT(14),
+       OCRDMA_QP_PARA_MAX_RQE_VALID    = BIT(15),
+       OCRDMA_QP_PARA_SGE_SEND_VALID   = BIT(16),
+       OCRDMA_QP_PARA_SGE_RECV_VALID   = BIT(17),
+       OCRDMA_QP_PARA_SGE_WR_VALID     = BIT(18),
+       OCRDMA_QP_PARA_INB_RDEN_VALID   = BIT(19),
+       OCRDMA_QP_PARA_INB_WREN_VALID   = BIT(20),
+       OCRDMA_QP_PARA_FLOW_LBL_VALID   = BIT(21),
+       OCRDMA_QP_PARA_BIND_EN_VALID    = BIT(22),
+       OCRDMA_QP_PARA_ZLKEY_EN_VALID   = BIT(23),
+       OCRDMA_QP_PARA_FMR_EN_VALID     = BIT(24),
+       OCRDMA_QP_PARA_INBAT_EN_VALID   = BIT(25),
+       OCRDMA_QP_PARA_VLAN_EN_VALID    = BIT(26),
+
+       OCRDMA_MODIFY_QP_FLAGS_RD       = BIT(0),
+       OCRDMA_MODIFY_QP_FLAGS_WR       = BIT(1),
+       OCRDMA_MODIFY_QP_FLAGS_SEND     = BIT(2),
+       OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = BIT(3)
 };
 
 enum {
@@ -1014,15 +1012,15 @@ enum {
        OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
                                        OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
 
-       OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = Bit(0),
-       OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = Bit(1),
-       OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = Bit(2),
-       OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = Bit(3),
-       OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = Bit(4),
+       OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = BIT(0),
+       OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = BIT(1),
+       OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = BIT(2),
+       OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = BIT(3),
+       OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = BIT(4),
        OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
-       OCRDMA_QP_PARAMS_STATE_MASK             = Bit(5) | Bit(6) | Bit(7),
-       OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = Bit(8),
-       OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = Bit(9),
+       OCRDMA_QP_PARAMS_STATE_MASK             = BIT(5) | BIT(6) | BIT(7),
+       OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = BIT(8),
+       OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = BIT(9),
        OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
        OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
                                        OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
@@ -1277,7 +1275,7 @@ struct ocrdma_alloc_pd {
 };
 
 enum {
-       OCRDMA_ALLOC_PD_RSP_DPP                 = Bit(16),
+       OCRDMA_ALLOC_PD_RSP_DPP                 = BIT(16),
        OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
        OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
 };
@@ -1309,18 +1307,18 @@ enum {
        OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
 
        OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
-       OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = Bit(0),
+       OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = BIT(0),
        OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
-       OCRDMA_ALLOC_LKEY_FMR_MASK              = Bit(1),
+       OCRDMA_ALLOC_LKEY_FMR_MASK              = BIT(1),
        OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
-       OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = Bit(2),
+       OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = BIT(2),
        OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
-       OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = Bit(3),
+       OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = BIT(3),
        OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
-       OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = Bit(4),
+       OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = BIT(4),
        OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
-       OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = Bit(5),
-       OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = Bit(6),
+       OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = BIT(5),
+       OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = BIT(6),
        OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
        OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
        OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
@@ -1379,21 +1377,21 @@ enum {
        OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
                                        OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
        OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
-       OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = Bit(24),
+       OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = BIT(24),
        OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
-       OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = Bit(25),
+       OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = BIT(25),
        OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
-       OCRDMA_REG_NSMR_REMOTE_INV_MASK         = Bit(26),
+       OCRDMA_REG_NSMR_REMOTE_INV_MASK         = BIT(26),
        OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
-       OCRDMA_REG_NSMR_REMOTE_WR_MASK          = Bit(27),
+       OCRDMA_REG_NSMR_REMOTE_WR_MASK          = BIT(27),
        OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
-       OCRDMA_REG_NSMR_REMOTE_RD_MASK          = Bit(28),
+       OCRDMA_REG_NSMR_REMOTE_RD_MASK          = BIT(28),
        OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
-       OCRDMA_REG_NSMR_LOCAL_WR_MASK           = Bit(29),
+       OCRDMA_REG_NSMR_LOCAL_WR_MASK           = BIT(29),
        OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
-       OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = Bit(30),
+       OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = BIT(30),
        OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
-       OCRDMA_REG_NSMR_LAST_MASK               = Bit(31)
+       OCRDMA_REG_NSMR_LAST_MASK               = BIT(31)
 };
 
 struct ocrdma_reg_nsmr {
@@ -1420,7 +1418,7 @@ enum {
                                        OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
 
        OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
-       OCRDMA_REG_NSMR_CONT_LAST_MASK          = Bit(31)
+       OCRDMA_REG_NSMR_CONT_LAST_MASK          = BIT(31)
 };
 
 struct ocrdma_reg_nsmr_cont {
@@ -1566,7 +1564,7 @@ struct ocrdma_delete_ah_tbl_rsp {
 
 enum {
        OCRDMA_EQE_VALID_SHIFT          = 0,
-       OCRDMA_EQE_VALID_MASK           = Bit(0),
+       OCRDMA_EQE_VALID_MASK           = BIT(0),
        OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
        OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
        OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
@@ -1624,11 +1622,11 @@ enum {
        OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
        OCRDMA_CQE_STATUS_SHIFT         = 16,
        OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
-       OCRDMA_CQE_VALID                = Bit(31),
-       OCRDMA_CQE_INVALIDATE           = Bit(30),
-       OCRDMA_CQE_QTYPE                = Bit(29),
-       OCRDMA_CQE_IMM                  = Bit(28),
-       OCRDMA_CQE_WRITE_IMM            = Bit(27),
+       OCRDMA_CQE_VALID                = BIT(31),
+       OCRDMA_CQE_INVALIDATE           = BIT(30),
+       OCRDMA_CQE_QTYPE                = BIT(29),
+       OCRDMA_CQE_IMM                  = BIT(28),
+       OCRDMA_CQE_WRITE_IMM            = BIT(27),
        OCRDMA_CQE_QTYPE_SQ             = 0,
        OCRDMA_CQE_QTYPE_RQ             = 1,
        OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
@@ -1772,8 +1770,8 @@ struct ocrdma_grh {
        u16     rsvd;
 } __packed;
 
-#define OCRDMA_AV_VALID                Bit(7)
-#define OCRDMA_AV_VLAN_VALID   Bit(1)
+#define OCRDMA_AV_VALID                BIT(7)
+#define OCRDMA_AV_VLAN_VALID   BIT(1)
 
 struct ocrdma_av {
        struct ocrdma_eth_vlan eth_hdr;