crypto: caam - ensure descriptor buffers are cacheline aligned
authorRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 8 Aug 2016 17:04:36 +0000 (18:04 +0100)
committerHerbert Xu <herbert@gondor.apana.org.au>
Tue, 9 Aug 2016 10:47:24 +0000 (18:47 +0800)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/caam/caamhash.c

index 24acd52..ff91efd 100644 (file)
@@ -99,17 +99,17 @@ static struct list_head hash_list;
 
 /* ahash per-session context */
 struct caam_hash_ctx {
-       struct device *jrdev;
-       u32 sh_desc_update[DESC_HASH_MAX_USED_LEN];
-       u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN];
-       u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN];
-       u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN];
-       u32 sh_desc_finup[DESC_HASH_MAX_USED_LEN];
-       dma_addr_t sh_desc_update_dma;
+       u32 sh_desc_update[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+       u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+       u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+       u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+       u32 sh_desc_finup[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+       dma_addr_t sh_desc_update_dma ____cacheline_aligned;
        dma_addr_t sh_desc_update_first_dma;
        dma_addr_t sh_desc_fin_dma;
        dma_addr_t sh_desc_digest_dma;
        dma_addr_t sh_desc_finup_dma;
+       struct device *jrdev;
        u32 alg_type;
        u32 alg_op;
        u8 key[CAAM_MAX_HASH_KEY_SIZE];