CHROMIUM: ARM: Exynos5: Manually configure the chip select gpio for spidev.

The kernel should not depend on firmware to configure the chip select pin
with function 1 (gpio) for us.

BUG=chrome-os-partner:10755
TEST=Confirm flashrom -p linux_spi:dev=/dev/spidev1.0 --get-size works.

Change-Id: I77c7e5134fa323a82e6f5308566ff05493e493cd
Signed-off-by: Bryan Freed <bfreed@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(dianders resolved trivial merge conflicts)
Reviewed-on: https://gerrit-int.chromium.org/20625
Tested-by: Doug Anderson <dianders@google.com>
Commit-Ready: Doug Anderson <dianders@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Reviewed-by: Olof Johansson <olofj@google.com>

diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1b796f8..84a2b19 100644 (file)
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -829,7 +829,15 @@ static void __init exynos5250_dt_machine_init(void)
         */
        enable_xclkout();
 
-       spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
+       if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
+               printk(KERN_ERR "Spidev ChipSelect unavailable\n");
+       } else {
+               s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
+               s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
+               s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
+               spi_register_board_info(spi1_board_info,
+                                       ARRAY_SIZE(spi1_board_info));
+       }
 
        of_platform_populate(NULL, of_default_bus_match_table,
                                exynos5250_auxdata_lookup, NULL);