ASoC: Intel: Fix naming of HMDC register macros.
authorLiam Girdwood <liam.r.girdwood@linux.intel.com>
Wed, 30 Jul 2014 12:05:44 +0000 (20:05 +0800)
committerMark Brown <broonie@linaro.org>
Wed, 30 Jul 2014 12:16:58 +0000 (13:16 +0100)
HMDC is the correct naming for this register.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
sound/soc/intel/sst-dsp.h
sound/soc/intel/sst-haswell-dsp.c

index 967fb32..21a85eb 100644 (file)
@@ -52,7 +52,7 @@
 #define SST_CLKCTL             0x78
 #define SST_CSR2               0x80
 #define SST_LTRC               0xE0
-#define SST_HDMC               0xE8
+#define SST_HMDC               0xE8
 
 #define SST_SHIM_BEGIN         SST_CSR
 #define SST_SHIM_END           SST_HDMC
 /* LTRC */
 #define SST_LTRC_VAL(x)                (x << 0)
 
-/* HDMC */
-#define SST_HDMC_HDDA0(x)      (x << 0)
-#define SST_HDMC_HDDA1(x)      (x << 7)
+/* HMDC */
+#define SST_HMDC_HDDA0(x)      (x << 0)
+#define SST_HMDC_HDDA1(x)      (x << 7)
 
 
 /* SST Vendor Defined Registers and bits */
index 7b8ad99..0e1dde8 100644 (file)
@@ -269,9 +269,9 @@ static void hsw_boot(struct sst_dsp *sst)
                SST_CSR2_SDFD_SSP1);
 
        /* enable DMA engine 0,1 all channels to access host memory */
-       sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC,
-               SST_HDMC_HDDA1(0xff)  | SST_HDMC_HDDA0(0xff),
-               SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff));
+       sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
+               SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff),
+               SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff));
 
        /* disable all clock gating */
        writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);