From: Sameer Nanda Date: Wed, 16 Jan 2013 22:27:37 +0000 (-0800) Subject: drm/i915: Honor i915_min_freq post resume X-Git-Url: http://git.cascardo.eti.br/?a=commitdiff_plain;h=b57da6083079196f955b8217517afd0e1e4a0e21;p=cascardo%2Flinux.git drm/i915: Honor i915_min_freq post resume The i915_min_freq setting was not getting honored on the resume path. Fixed it. BUG=chrome-os-partner:16439 TEST="cat /sys/kernel/debug/dri/0/i915_min_freq" and remember the value returned. Do a suspend/resume cycle. cat the i915_min_freq file again, it must return the same value as read earlier. Change-Id: Ie3cc8e8794a59c154b511e24e468daef94a44765 Signed-off-by: Sameer Nanda Reviewed-on: https://gerrit.chromium.org/gerrit/41461 --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 55a40334c27a..b76f2920020b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8302,7 +8302,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); u32 pcu_mbox, rc6_mask = 0; u32 gtfifodbg; - int cur_freq, min_freq, max_freq; + u8 cur_delay, min_delay, max_delay; int rc6_mode; int i; @@ -8361,13 +8361,6 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) GEN6_RC_CTL_EI_MODE(1) | GEN6_RC_CTL_HW_ENABLE); - I915_WRITE(GEN6_RPNSWREQ, - GEN6_FREQUENCY(10) | - GEN6_OFFSET(0) | - GEN6_AGGRESSIVE_TURBO); - I915_WRITE(GEN6_RC_VIDEO_FREQ, - GEN6_FREQUENCY(12)); - I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 10000); I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 18 << 24 | @@ -8403,9 +8396,9 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) 500)) DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); - min_freq = (rp_state_cap & 0xff0000) >> 16; - max_freq = rp_state_cap & 0xff; - cur_freq = (gt_perf_status & 0xff00) >> 8; + min_delay = (rp_state_cap & 0xff0000) >> 16; + max_delay = rp_state_cap & 0xff; + cur_delay = (gt_perf_status & 0xff00) >> 8; /* Check for overclock support */ if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, @@ -8417,14 +8410,21 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) 500)) DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); if (pcu_mbox & (1<<31)) { /* OC supported */ - max_freq = pcu_mbox & 0xff; + max_delay = pcu_mbox & 0xff; DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); } /* In units of 100MHz */ - dev_priv->max_delay = max_freq; - dev_priv->min_delay = min_freq; - dev_priv->cur_delay = cur_freq; + dev_priv->min_delay = max(min_delay, dev_priv->min_delay); + dev_priv->max_delay = max_delay; + dev_priv->cur_delay = max(dev_priv->min_delay, (u8)10); + + I915_WRITE(GEN6_RPNSWREQ, + GEN6_FREQUENCY(dev_priv->cur_delay) | + GEN6_OFFSET(0) | + GEN6_AGGRESSIVE_TURBO); + I915_WRITE(GEN6_RC_VIDEO_FREQ, + GEN6_FREQUENCY(12)); /* requires MSI enabled */ I915_WRITE(GEN6_PMIER,