From: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
Date: Wed, 6 Feb 2019 18:35:22 +0000 (-0200)
Subject: A small RISC-V SBI demo.
X-Git-Url: http://git.cascardo.eti.br/?p=cascardo%2Fblix.git;a=commitdiff_plain;h=aa0088e95594524ed016356ba5c2f0c6c0eb8904

A small RISC-V SBI demo.

A small code running as S-mode on top of an SEE, using the SBI to print to the
console. It may also be slightly changed to bump into an illegal instruction in
order to test exception handling.
---

aa0088e95594524ed016356ba5c2f0c6c0eb8904
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..f4fadfb
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,13 @@
+all: blix.bin
+
+blix: blix.S
+	riscv64-linux-gnu-gcc -o blix blix.S -nostdinc -nostdlib -march=rv64imafd
+
+blix.bin: blix
+	riscv64-linux-gnu-objcopy --only-section=.text  -O binary blix blix.bin
+
+clean:
+	rm -f blix.bin blix
+
+run: blix.bin
+	qemu-system-riscv64 -M virt -kernel ../opensbi/build/platform/qemu/virt/firmware/fw_jump.elf -serial stdio -device loader,file=blix.bin,addr=0x80200000 -d in_asm -D log
diff --git a/blix.S b/blix.S
new file mode 100644
index 0000000..2eb42b8
--- /dev/null
+++ b/blix.S
@@ -0,0 +1,54 @@
+.global _start
+_start:
+	li a1, 2
+	csrs sstatus, a1
+	la a1, _vec
+	csrw stvec, a1
+	li a7, 1
+	la a1, _hello
+	jal puts
+	csrr a2, stvec
+	jal putl
+halt:
+	j halt
+
+putl:
+	andi a0, a2, 0xf
+	addi a0, a0, 0x30
+	slti a1, a0, 0x3A
+	bne a1, zero, _next
+	addi a0, a0, 7
+_next:
+	ecall
+	srli a2, a2, 4
+	beq a2, zero, exit2
+	j putl
+exit2:
+	li a0, 0xa
+	ecall
+	ret
+
+puts:
+	lb a0, (a1)
+	beq a0, zero, exit
+	ecall
+	addi a1, a1, 1
+	j puts
+exit:
+	ret
+
+_hello:
+.ascii "Hello, world!\n"
+.byte 0
+
+.align 8
+_vec:
+	li a7, 1
+	la a1, _exception
+	jal puts
+loop2:
+	j loop2
+
+_exception:
+.ascii "exception\n"
+.byte 0