#define AUX_BUSY 0x10
#define SP_TX_BUF_DATA_COUNT_REG 0x70E4
+#define BUF_CLR 0x80
#define SP_TX_AUX_CTRL_REG 0x70E5
#define SP_TX_AUX_ADDR_7_0_REG 0x70E6
#define SPECIFIC_INTERRUPT_1 0x00510
#define SPECIFIC_INTERRUPT_2 0x00511
#define DOWN_STREAM_STATUS_1 0x00518
+#define DOWN_R_TERM_DET 0x40
+#define SRAM_EEPROM_LOAD_DONE 0x20
+#define SRAM_CRC_CHK_DONE 0x10
+#define SRAM_CRC_CHK_PASS 0x08
+#define DOWN_STRM_ENC 0x04
+#define DOWN_STRM_AUTH 0x02
+#define DOWN_STRM_HPD 0x20
+
#define DOWN_STREAM_STATUS_2 0x00519
#define US_COMM_TX_INT 0x00520
#define US_COMM_RX_INT 0x00521