net/mlx4_en: Use PTYS register to query ethtool settings

[cascardo/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_port.h

diff --git a/drivers/net/ethernet/mellanox/mlx4/en_port.h b/drivers/net/ethernet/mellanox/mlx4/en_port.h
index a5fc93b..040da4b 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx4/en_port.h
+++ b/drivers/net/ethernet/mellanox/mlx4/en_port.h
@@ -53,6 +53,28 @@ enum {
        MLX4_MCAST_ENABLE       = 2,
 };
 
+enum mlx4_link_mode {
+       MLX4_1000BASE_CX_SGMII   = 0,
+       MLX4_1000BASE_KX         = 1,
+       MLX4_10GBASE_CX4         = 2,
+       MLX4_10GBASE_KX4         = 3,
+       MLX4_10GBASE_KR          = 4,
+       MLX4_20GBASE_KR2         = 5,
+       MLX4_40GBASE_CR4         = 6,
+       MLX4_40GBASE_KR4         = 7,
+       MLX4_56GBASE_KR4         = 8,
+       MLX4_10GBASE_CR          = 12,
+       MLX4_10GBASE_SR          = 13,
+       MLX4_40GBASE_SR4         = 15,
+       MLX4_56GBASE_CR4         = 17,
+       MLX4_56GBASE_SR4         = 18,
+       MLX4_100BASE_TX          = 24,
+       MLX4_1000BASE_T          = 25,
+       MLX4_10GBASE_T           = 26,
+};
+
+#define MLX4_PROT_MASK(link_mode) (1<<link_mode)
+
 enum {
        MLX4_EN_100M_SPEED      = 0x04,
        MLX4_EN_10G_SPEED_XAUI  = 0x00,
@@ -67,7 +89,9 @@ enum {
 struct mlx4_en_query_port_context {
        u8 link_up;
 #define MLX4_EN_LINK_UP_MASK   0x80
-       u8 reserved;
+#define MLX4_EN_ANC_MASK       0x40
+       u8 autoneg;
+#define MLX4_EN_AUTONEG_MASK   0x80
        __be16 mtu;
        u8 reserved2;
        u8 link_speed;