};
enum mlx4_port_type {
- MLX4_PORT_TYPE_IB = 1 << 0,
- MLX4_PORT_TYPE_ETH = 1 << 1,
+ MLX4_PORT_TYPE_IB = 1,
+ MLX4_PORT_TYPE_ETH = 2,
+ MLX4_PORT_TYPE_AUTO = 3
};
enum mlx4_special_vlan_idx {
int reserved_cqs;
int num_eqs;
int reserved_eqs;
+ int num_comp_vectors;
int num_mpts;
int num_mtt_segs;
int fmr_reserved_mtts;
enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
u8 supported_type[MLX4_MAX_PORTS + 1];
u32 port_mask;
+ enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
};
struct mlx4_buf_list {
int arm_sn;
int cqn;
+ unsigned vector;
atomic_t refcount;
struct completion free;
int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
- int collapsed);
+ unsigned vector, int collapsed);
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);