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[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.
authorRalf Baechle <ralf@linux-mips.org>
Thu, 5 Jul 2007 07:14:21 +0000 (08:14 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 6 Jul 2007 15:17:11 +0000 (16:17 +0100)
commit075c733e19ce7530b53b78151cc4d303c8f64548
treec4f3e9a373b924794c97f5964cd55b121918ab41tree | snapshot
parent9349075a15a876f8e82f433ec84f99d19d3e77f9commit | diff
[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.

The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
opposes it being called that) where invalid instructions in the same
I-cache line worth of instructions being fetched may case spurious
exceptions.

The workaround for this was only enabled for E9000 cores; enable it also
for all RM7000-based platforms.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
include/asm-mips/war.h diff | blob | history
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