From: Roger Quadros <rogerq@ti.com>
Date: Thu, 7 Apr 2016 10:25:40 +0000 (+0300)
Subject: ARM: dts: omap3-beagle: Provide NAND ready pin
X-Git-Tag: v4.7-rc1~136^2~13^2~21
X-Git-Url: http://git.cascardo.eti.br/?p=cascardo%2Flinux.git;a=commitdiff_plain;h=4cb53a2308a96d97854b166780dace58737446ed

ARM: dts: omap3-beagle: Provide NAND ready pin

On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.

Read speed increases from 13212 KiB/ to 15753 KiB/s
and write speed was unchanged at 4404 KiB/s.

Measured using mtd_speedtest.ko on omap3-beagle-c4.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 4602866792be..a4deff0e2d52 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -390,6 +390,7 @@
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		ti,nand-ecc-opt = "ham1";
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		nand-bus-width = <16>;
 		#address-cells = <1>;
 		#size-cells = <1>;