drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  19  */
  20
  21 #include "pch_gbe.h"
  22 #include "pch_gbe_api.h"
  23 #include <linux/module.h>
  24 #include <linux/net_tstamp.h>
  25 #include <linux/ptp_classify.h>
  26
  27 #define DRV_VERSION     "1.01"
  28 const char pch_driver_version[] = DRV_VERSION;
  29
  30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  31 #define PCH_GBE_MAR_ENTRIES             16
  32 #define PCH_GBE_SHORT_PKT               64
  33 #define DSC_INIT16                      0xC000
  34 #define PCH_GBE_DMA_ALIGN               0
  35 #define PCH_GBE_DMA_PADDING             2
  36 #define PCH_GBE_WATCHDOG_PERIOD         (5 * HZ)        /* watchdog time */
  37 #define PCH_GBE_COPYBREAK_DEFAULT       256
  38 #define PCH_GBE_PCI_BAR                 1
  39 #define PCH_GBE_RESERVE_MEMORY          0x200000        /* 2MB */
  40
  41 /* Macros for ML7223 */
  42 #define PCI_VENDOR_ID_ROHM                      0x10db
  43 #define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  44
  45 /* Macros for ML7831 */
  46 #define PCI_DEVICE_ID_ROHM_ML7831_GBE           0x8802
  47
  48 #define PCH_GBE_TX_WEIGHT         64
  49 #define PCH_GBE_RX_WEIGHT         64
  50 #define PCH_GBE_RX_BUFFER_WRITE   16
  51
  52 /* Initialize the wake-on-LAN settings */
  53 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  54
  55 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  56         PCH_GBE_CHIP_TYPE_INTERNAL | \
  57         PCH_GBE_RGMII_MODE_RGMII     \
  58         )
  59
  60 /* Ethertype field values */
  61 #define PCH_GBE_MAX_RX_BUFFER_SIZE      0x2880
  62 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  63 #define PCH_GBE_FRAME_SIZE_2048         2048
  64 #define PCH_GBE_FRAME_SIZE_4096         4096
  65 #define PCH_GBE_FRAME_SIZE_8192         8192
  66
  67 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  68 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  69 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  70 #define PCH_GBE_DESC_UNUSED(R) \
  71         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  72         (R)->next_to_clean - (R)->next_to_use - 1)
  73
  74 /* Pause packet value */
  75 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  76 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  77 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  78 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  79
  80
  81 /* This defines the bits that are set in the Interrupt Mask
  82  * Set/Read Register.  Each bit is documented below:
  83  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  84  *   o TXDW   = Transmit Descriptor Written Back
  85  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  86  *   o RXSEQ  = Receive Sequence Error
  87  *   o LSC    = Link Status Change
  88  */
  89 #define PCH_GBE_INT_ENABLE_MASK ( \
  90         PCH_GBE_INT_RX_DMA_CMPLT |    \
  91         PCH_GBE_INT_RX_DSC_EMP   |    \
  92         PCH_GBE_INT_RX_FIFO_ERR  |    \
  93         PCH_GBE_INT_WOL_DET      |    \
  94         PCH_GBE_INT_TX_CMPLT          \
  95         )
  96
  97 #define PCH_GBE_INT_DISABLE_ALL         0
  98
  99 /* Macros for ieee1588 */
 100 /* 0x40 Time Synchronization Channel Control Register Bits */
 101 #define MASTER_MODE   (1<<0)
 102 #define SLAVE_MODE    (0)
 103 #define V2_MODE       (1<<31)
 104 #define CAP_MODE0     (0)
 105 #define CAP_MODE2     (1<<17)
 106
 107 /* 0x44 Time Synchronization Channel Event Register Bits */
 108 #define TX_SNAPSHOT_LOCKED (1<<0)
 109 #define RX_SNAPSHOT_LOCKED (1<<1)
 110
 111 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
 112 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
 113
 114 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
 115
 116 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 117 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
 118                                int data);
 119 static void pch_gbe_set_multi(struct net_device *netdev);
 120
 121 static struct sock_filter ptp_filter[] = {
 122         PTP_FILTER
 123 };
 124
 125 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 126 {
 127         u8 *data = skb->data;
 128         unsigned int offset;
 129         u16 *hi, *id;
 130         u32 lo;
 131
 132         if (sk_run_filter(skb, ptp_filter) == PTP_CLASS_NONE)
 133                 return 0;
 134
 135         offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 136
 137         if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 138                 return 0;
 139
 140         hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 141         id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 142
 143         memcpy(&lo, &hi[1], sizeof(lo));
 144
 145         return (uid_hi == *hi &&
 146                 uid_lo == lo &&
 147                 seqid  == *id);
 148 }
 149
 150 static void
 151 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 152 {
 153         struct skb_shared_hwtstamps *shhwtstamps;
 154         struct pci_dev *pdev;
 155         u64 ns;
 156         u32 hi, lo, val;
 157         u16 uid, seq;
 158
 159         if (!adapter->hwts_rx_en)
 160                 return;
 161
 162         /* Get ieee1588's dev information */
 163         pdev = adapter->ptp_pdev;
 164
 165         val = pch_ch_event_read(pdev);
 166
 167         if (!(val & RX_SNAPSHOT_LOCKED))
 168                 return;
 169
 170         lo = pch_src_uuid_lo_read(pdev);
 171         hi = pch_src_uuid_hi_read(pdev);
 172
 173         uid = hi & 0xffff;
 174         seq = (hi >> 16) & 0xffff;
 175
 176         if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 177                 goto out;
 178
 179         ns = pch_rx_snap_read(pdev);
 180
 181         shhwtstamps = skb_hwtstamps(skb);
 182         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 183         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 184 out:
 185         pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
 186 }
 187
 188 static void
 189 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 190 {
 191         struct skb_shared_hwtstamps shhwtstamps;
 192         struct pci_dev *pdev;
 193         struct skb_shared_info *shtx;
 194         u64 ns;
 195         u32 cnt, val;
 196
 197         shtx = skb_shinfo(skb);
 198         if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
 199                 return;
 200
 201         shtx->tx_flags |= SKBTX_IN_PROGRESS;
 202
 203         /* Get ieee1588's dev information */
 204         pdev = adapter->ptp_pdev;
 205
 206         /*
 207          * This really stinks, but we have to poll for the Tx time stamp.
 208          */
 209         for (cnt = 0; cnt < 100; cnt++) {
 210                 val = pch_ch_event_read(pdev);
 211                 if (val & TX_SNAPSHOT_LOCKED)
 212                         break;
 213                 udelay(1);
 214         }
 215         if (!(val & TX_SNAPSHOT_LOCKED)) {
 216                 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 217                 return;
 218         }
 219
 220         ns = pch_tx_snap_read(pdev);
 221
 222         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 223         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 224         skb_tstamp_tx(skb, &shhwtstamps);
 225
 226         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
 227 }
 228
 229 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 230 {
 231         struct hwtstamp_config cfg;
 232         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 233         struct pci_dev *pdev;
 234         u8 station[20];
 235
 236         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 237                 return -EFAULT;
 238
 239         if (cfg.flags) /* reserved for future extensions */
 240                 return -EINVAL;
 241
 242         /* Get ieee1588's dev information */
 243         pdev = adapter->ptp_pdev;
 244
 245         switch (cfg.tx_type) {
 246         case HWTSTAMP_TX_OFF:
 247                 adapter->hwts_tx_en = 0;
 248                 break;
 249         case HWTSTAMP_TX_ON:
 250                 adapter->hwts_tx_en = 1;
 251                 break;
 252         default:
 253                 return -ERANGE;
 254         }
 255
 256         switch (cfg.rx_filter) {
 257         case HWTSTAMP_FILTER_NONE:
 258                 adapter->hwts_rx_en = 0;
 259                 break;
 260         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 261                 adapter->hwts_rx_en = 0;
 262                 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
 263                 break;
 264         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 265                 adapter->hwts_rx_en = 1;
 266                 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
 267                 break;
 268         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 269                 adapter->hwts_rx_en = 1;
 270                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 271                 strcpy(station, PTP_L4_MULTICAST_SA);
 272                 pch_set_station_address(station, pdev);
 273                 break;
 274         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 275                 adapter->hwts_rx_en = 1;
 276                 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 277                 strcpy(station, PTP_L2_MULTICAST_SA);
 278                 pch_set_station_address(station, pdev);
 279                 break;
 280         default:
 281                 return -ERANGE;
 282         }
 283
 284         /* Clear out any old time stamps. */
 285         pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
 286
 287         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 288 }
 289
 290 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
 291 {
 292         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 293 }
 294
 295 /**
 296  * pch_gbe_mac_read_mac_addr - Read MAC address
 297  * @hw:             Pointer to the HW structure
 298  * Returns:
 299  *      0:                      Successful.
 300  */
 301 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 302 {
 303         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 304         u32  adr1a, adr1b;
 305
 306         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 307         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 308
 309         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 310         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 311         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 312         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 313         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 314         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 315
 316         netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
 317         return 0;
 318 }
 319
 320 /**
 321  * pch_gbe_wait_clr_bit - Wait to clear a bit
 322  * @reg:        Pointer of register
 323  * @busy:       Busy bit
 324  */
 325 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 326 {
 327         u32 tmp;
 328
 329         /* wait busy */
 330         tmp = 1000;
 331         while ((ioread32(reg) & bit) && --tmp)
 332                 cpu_relax();
 333         if (!tmp)
 334                 pr_err("Error: busy bit is not cleared\n");
 335 }
 336
 337 /**
 338  * pch_gbe_mac_mar_set - Set MAC address register
 339  * @hw:     Pointer to the HW structure
 340  * @addr:   Pointer to the MAC address
 341  * @index:  MAC address array register
 342  */
 343 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 344 {
 345         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 346         u32 mar_low, mar_high, adrmask;
 347
 348         netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
 349
 350         /*
 351          * HW expects these in little endian so we reverse the byte order
 352          * from network order (big endian) to little endian
 353          */
 354         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 355                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 356         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 357         /* Stop the MAC Address of index. */
 358         adrmask = ioread32(&hw->reg->ADDR_MASK);
 359         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 360         /* wait busy */
 361         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 362         /* Set the MAC address to the MAC address 1A/1B register */
 363         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 364         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 365         /* Start the MAC address of index */
 366         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 367         /* wait busy */
 368         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 369 }
 370
 371 /**
 372  * pch_gbe_mac_reset_hw - Reset hardware
 373  * @hw: Pointer to the HW structure
 374  */
 375 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 376 {
 377         /* Read the MAC address. and store to the private data */
 378         pch_gbe_mac_read_mac_addr(hw);
 379         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 380 #ifdef PCH_GBE_MAC_IFOP_RGMII
 381         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 382 #endif
 383         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 384         /* Setup the receive addresses */
 385         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 386         return;
 387 }
 388
 389 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 390 {
 391         u32 rctl;
 392         /* Disables Receive MAC */
 393         rctl = ioread32(&hw->reg->MAC_RX_EN);
 394         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 395 }
 396
 397 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
 398 {
 399         u32 rctl;
 400         /* Enables Receive MAC */
 401         rctl = ioread32(&hw->reg->MAC_RX_EN);
 402         iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 403 }
 404
 405 /**
 406  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 407  * @hw: Pointer to the HW structure
 408  * @mar_count: Receive address registers
 409  */
 410 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 411 {
 412         u32 i;
 413
 414         /* Setup the receive address */
 415         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 416
 417         /* Zero out the other receive addresses */
 418         for (i = 1; i < mar_count; i++) {
 419                 iowrite32(0, &hw->reg->mac_adr[i].high);
 420                 iowrite32(0, &hw->reg->mac_adr[i].low);
 421         }
 422         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 423         /* wait busy */
 424         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 425 }
 426
 427
 428 /**
 429  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 430  * @hw:             Pointer to the HW structure
 431  * @mc_addr_list:   Array of multicast addresses to program
 432  * @mc_addr_count:  Number of multicast addresses to program
 433  * @mar_used_count: The first MAC Address register free to program
 434  * @mar_total_num:  Total number of supported MAC Address Registers
 435  */
 436 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 437                                             u8 *mc_addr_list, u32 mc_addr_count,
 438                                             u32 mar_used_count, u32 mar_total_num)
 439 {
 440         u32 i, adrmask;
 441
 442         /* Load the first set of multicast addresses into the exact
 443          * filters (RAR).  If there are not enough to fill the RAR
 444          * array, clear the filters.
 445          */
 446         for (i = mar_used_count; i < mar_total_num; i++) {
 447                 if (mc_addr_count) {
 448                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 449                         mc_addr_count--;
 450                         mc_addr_list += ETH_ALEN;
 451                 } else {
 452                         /* Clear MAC address mask */
 453                         adrmask = ioread32(&hw->reg->ADDR_MASK);
 454                         iowrite32((adrmask | (0x0001 << i)),
 455                                         &hw->reg->ADDR_MASK);
 456                         /* wait busy */
 457                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 458                         /* Clear MAC address */
 459                         iowrite32(0, &hw->reg->mac_adr[i].high);
 460                         iowrite32(0, &hw->reg->mac_adr[i].low);
 461                 }
 462         }
 463 }
 464
 465 /**
 466  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 467  * @hw:             Pointer to the HW structure
 468  * Returns:
 469  *      0:                      Successful.
 470  *      Negative value:         Failed.
 471  */
 472 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 473 {
 474         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 475         struct pch_gbe_mac_info *mac = &hw->mac;
 476         u32 rx_fctrl;
 477
 478         netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
 479
 480         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 481
 482         switch (mac->fc) {
 483         case PCH_GBE_FC_NONE:
 484                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 485                 mac->tx_fc_enable = false;
 486                 break;
 487         case PCH_GBE_FC_RX_PAUSE:
 488                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 489                 mac->tx_fc_enable = false;
 490                 break;
 491         case PCH_GBE_FC_TX_PAUSE:
 492                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 493                 mac->tx_fc_enable = true;
 494                 break;
 495         case PCH_GBE_FC_FULL:
 496                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 497                 mac->tx_fc_enable = true;
 498                 break;
 499         default:
 500                 netdev_err(adapter->netdev,
 501                            "Flow control param set incorrectly\n");
 502                 return -EINVAL;
 503         }
 504         if (mac->link_duplex == DUPLEX_HALF)
 505                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 506         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 507         netdev_dbg(adapter->netdev,
 508                    "RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 509                    ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 510         return 0;
 511 }
 512
 513 /**
 514  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 515  * @hw:     Pointer to the HW structure
 516  * @wu_evt: Wake up event
 517  */
 518 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 519 {
 520         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 521         u32 addr_mask;
 522
 523         netdev_dbg(adapter->netdev, "wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 524                    wu_evt, ioread32(&hw->reg->ADDR_MASK));
 525
 526         if (wu_evt) {
 527                 /* Set Wake-On-Lan address mask */
 528                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 529                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 530                 /* wait busy */
 531                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 532                 iowrite32(0, &hw->reg->WOL_ST);
 533                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 534                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 535                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 536         } else {
 537                 iowrite32(0, &hw->reg->WOL_CTRL);
 538                 iowrite32(0, &hw->reg->WOL_ST);
 539         }
 540         return;
 541 }
 542
 543 /**
 544  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 545  * @hw:   Pointer to the HW structure
 546  * @addr: Address of PHY
 547  * @dir:  Operetion. (Write or Read)
 548  * @reg:  Access register of PHY
 549  * @data: Write data.
 550  *
 551  * Returns: Read date.
 552  */
 553 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 554                         u16 data)
 555 {
 556         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 557         u32 data_out = 0;
 558         unsigned int i;
 559         unsigned long flags;
 560
 561         spin_lock_irqsave(&hw->miim_lock, flags);
 562
 563         for (i = 100; i; --i) {
 564                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 565                         break;
 566                 udelay(20);
 567         }
 568         if (i == 0) {
 569                 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
 570                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 571                 return 0;       /* No way to indicate timeout error */
 572         }
 573         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 574                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 575                   dir | data), &hw->reg->MIIM);
 576         for (i = 0; i < 100; i++) {
 577                 udelay(20);
 578                 data_out = ioread32(&hw->reg->MIIM);
 579                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 580                         break;
 581         }
 582         spin_unlock_irqrestore(&hw->miim_lock, flags);
 583
 584         netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
 585                    dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 586                    dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 587         return (u16) data_out;
 588 }
 589
 590 /**
 591  * pch_gbe_mac_set_pause_packet - Set pause packet
 592  * @hw:   Pointer to the HW structure
 593  */
 594 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 595 {
 596         struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 597         unsigned long tmp2, tmp3;
 598
 599         /* Set Pause packet */
 600         tmp2 = hw->mac.addr[1];
 601         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 602         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 603
 604         tmp3 = hw->mac.addr[5];
 605         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 606         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 607         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 608
 609         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 610         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 611         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 612         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 613         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 614
 615         /* Transmit Pause Packet */
 616         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 617
 618         netdev_dbg(adapter->netdev,
 619                    "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 620                    ioread32(&hw->reg->PAUSE_PKT1),
 621                    ioread32(&hw->reg->PAUSE_PKT2),
 622                    ioread32(&hw->reg->PAUSE_PKT3),
 623                    ioread32(&hw->reg->PAUSE_PKT4),
 624                    ioread32(&hw->reg->PAUSE_PKT5));
 625
 626         return;
 627 }
 628
 629
 630 /**
 631  * pch_gbe_alloc_queues - Allocate memory for all rings
 632  * @adapter:  Board private structure to initialize
 633  * Returns:
 634  *      0:      Successfully
 635  *      Negative value: Failed
 636  */
 637 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 638 {
 639         adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
 640                                         sizeof(*adapter->tx_ring), GFP_KERNEL);
 641         if (!adapter->tx_ring)
 642                 return -ENOMEM;
 643
 644         adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
 645                                         sizeof(*adapter->rx_ring), GFP_KERNEL);
 646         if (!adapter->rx_ring)
 647                 return -ENOMEM;
 648         return 0;
 649 }
 650
 651 /**
 652  * pch_gbe_init_stats - Initialize status
 653  * @adapter:  Board private structure to initialize
 654  */
 655 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 656 {
 657         memset(&adapter->stats, 0, sizeof(adapter->stats));
 658         return;
 659 }
 660
 661 /**
 662  * pch_gbe_init_phy - Initialize PHY
 663  * @adapter:  Board private structure to initialize
 664  * Returns:
 665  *      0:      Successfully
 666  *      Negative value: Failed
 667  */
 668 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 669 {
 670         struct net_device *netdev = adapter->netdev;
 671         u32 addr;
 672         u16 bmcr, stat;
 673
 674         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 675         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 676                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 677                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 678                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 679                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 680                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 681                         break;
 682         }
 683         adapter->hw.phy.addr = adapter->mii.phy_id;
 684         netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
 685         if (addr == PCH_GBE_PHY_REGS_LEN)
 686                 return -EAGAIN;
 687         /* Selected the phy and isolate the rest */
 688         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 689                 if (addr != adapter->mii.phy_id) {
 690                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 691                                            BMCR_ISOLATE);
 692                 } else {
 693                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 694                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 695                                            bmcr & ~BMCR_ISOLATE);
 696                 }
 697         }
 698
 699         /* MII setup */
 700         adapter->mii.phy_id_mask = 0x1F;
 701         adapter->mii.reg_num_mask = 0x1F;
 702         adapter->mii.dev = adapter->netdev;
 703         adapter->mii.mdio_read = pch_gbe_mdio_read;
 704         adapter->mii.mdio_write = pch_gbe_mdio_write;
 705         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 706         return 0;
 707 }
 708
 709 /**
 710  * pch_gbe_mdio_read - The read function for mii
 711  * @netdev: Network interface device structure
 712  * @addr:   Phy ID
 713  * @reg:    Access location
 714  * Returns:
 715  *      0:      Successfully
 716  *      Negative value: Failed
 717  */
 718 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 719 {
 720         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 721         struct pch_gbe_hw *hw = &adapter->hw;
 722
 723         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 724                                      (u16) 0);
 725 }
 726
 727 /**
 728  * pch_gbe_mdio_write - The write function for mii
 729  * @netdev: Network interface device structure
 730  * @addr:   Phy ID (not used)
 731  * @reg:    Access location
 732  * @data:   Write data
 733  */
 734 static void pch_gbe_mdio_write(struct net_device *netdev,
 735                                int addr, int reg, int data)
 736 {
 737         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 738         struct pch_gbe_hw *hw = &adapter->hw;
 739
 740         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 741 }
 742
 743 /**
 744  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 745  * @work:  Pointer of board private structure
 746  */
 747 static void pch_gbe_reset_task(struct work_struct *work)
 748 {
 749         struct pch_gbe_adapter *adapter;
 750         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 751
 752         rtnl_lock();
 753         pch_gbe_reinit_locked(adapter);
 754         rtnl_unlock();
 755 }
 756
 757 /**
 758  * pch_gbe_reinit_locked- Re-initialization
 759  * @adapter:  Board private structure
 760  */
 761 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 762 {
 763         pch_gbe_down(adapter);
 764         pch_gbe_up(adapter);
 765 }
 766
 767 /**
 768  * pch_gbe_reset - Reset GbE
 769  * @adapter:  Board private structure
 770  */
 771 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 772 {
 773         struct net_device *netdev = adapter->netdev;
 774
 775         pch_gbe_mac_reset_hw(&adapter->hw);
 776         /* reprogram multicast address register after reset */
 777         pch_gbe_set_multi(netdev);
 778         /* Setup the receive address. */
 779         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 780         if (pch_gbe_hal_init_hw(&adapter->hw))
 781                 netdev_err(netdev, "Hardware Error\n");
 782 }
 783
 784 /**
 785  * pch_gbe_free_irq - Free an interrupt
 786  * @adapter:  Board private structure
 787  */
 788 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 789 {
 790         struct net_device *netdev = adapter->netdev;
 791
 792         free_irq(adapter->pdev->irq, netdev);
 793         if (adapter->have_msi) {
 794                 pci_disable_msi(adapter->pdev);
 795                 netdev_dbg(netdev, "call pci_disable_msi\n");
 796         }
 797 }
 798
 799 /**
 800  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 801  * @adapter:  Board private structure
 802  */
 803 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 804 {
 805         struct pch_gbe_hw *hw = &adapter->hw;
 806
 807         atomic_inc(&adapter->irq_sem);
 808         iowrite32(0, &hw->reg->INT_EN);
 809         ioread32(&hw->reg->INT_ST);
 810         synchronize_irq(adapter->pdev->irq);
 811
 812         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 813                    ioread32(&hw->reg->INT_EN));
 814 }
 815
 816 /**
 817  * pch_gbe_irq_enable - Enable default interrupt generation settings
 818  * @adapter:  Board private structure
 819  */
 820 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 821 {
 822         struct pch_gbe_hw *hw = &adapter->hw;
 823
 824         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 825                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 826         ioread32(&hw->reg->INT_ST);
 827         netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 828                    ioread32(&hw->reg->INT_EN));
 829 }
 830
 831
 832
 833 /**
 834  * pch_gbe_setup_tctl - configure the Transmit control registers
 835  * @adapter:  Board private structure
 836  */
 837 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 838 {
 839         struct pch_gbe_hw *hw = &adapter->hw;
 840         u32 tx_mode, tcpip;
 841
 842         tx_mode = PCH_GBE_TM_LONG_PKT |
 843                 PCH_GBE_TM_ST_AND_FD |
 844                 PCH_GBE_TM_SHORT_PKT |
 845                 PCH_GBE_TM_TH_TX_STRT_8 |
 846                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 847
 848         iowrite32(tx_mode, &hw->reg->TX_MODE);
 849
 850         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 851         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 852         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 853         return;
 854 }
 855
 856 /**
 857  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 858  * @adapter:  Board private structure
 859  */
 860 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 861 {
 862         struct pch_gbe_hw *hw = &adapter->hw;
 863         u32 tdba, tdlen, dctrl;
 864
 865         netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
 866                    (unsigned long long)adapter->tx_ring->dma,
 867                    adapter->tx_ring->size);
 868
 869         /* Setup the HW Tx Head and Tail descriptor pointers */
 870         tdba = adapter->tx_ring->dma;
 871         tdlen = adapter->tx_ring->size - 0x10;
 872         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 873         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 874         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 875
 876         /* Enables Transmission DMA */
 877         dctrl = ioread32(&hw->reg->DMA_CTRL);
 878         dctrl |= PCH_GBE_TX_DMA_EN;
 879         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 880 }
 881
 882 /**
 883  * pch_gbe_setup_rctl - Configure the receive control registers
 884  * @adapter:  Board private structure
 885  */
 886 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 887 {
 888         struct pch_gbe_hw *hw = &adapter->hw;
 889         u32 rx_mode, tcpip;
 890
 891         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 892         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 893
 894         iowrite32(rx_mode, &hw->reg->RX_MODE);
 895
 896         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 897
 898         tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 899         tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 900         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 901         return;
 902 }
 903
 904 /**
 905  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 906  * @adapter:  Board private structure
 907  */
 908 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 909 {
 910         struct pch_gbe_hw *hw = &adapter->hw;
 911         u32 rdba, rdlen, rxdma;
 912
 913         netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
 914                    (unsigned long long)adapter->rx_ring->dma,
 915                    adapter->rx_ring->size);
 916
 917         pch_gbe_mac_force_mac_fc(hw);
 918
 919         pch_gbe_disable_mac_rx(hw);
 920
 921         /* Disables Receive DMA */
 922         rxdma = ioread32(&hw->reg->DMA_CTRL);
 923         rxdma &= ~PCH_GBE_RX_DMA_EN;
 924         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 925
 926         netdev_dbg(adapter->netdev,
 927                    "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 928                    ioread32(&hw->reg->MAC_RX_EN),
 929                    ioread32(&hw->reg->DMA_CTRL));
 930
 931         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 932          * the Base and Length of the Rx Descriptor Ring */
 933         rdba = adapter->rx_ring->dma;
 934         rdlen = adapter->rx_ring->size - 0x10;
 935         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 936         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 937         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 938 }
 939
 940 /**
 941  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 942  * @adapter:     Board private structure
 943  * @buffer_info: Buffer information structure
 944  */
 945 static void pch_gbe_unmap_and_free_tx_resource(
 946         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 947 {
 948         if (buffer_info->mapped) {
 949                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 950                                  buffer_info->length, DMA_TO_DEVICE);
 951                 buffer_info->mapped = false;
 952         }
 953         if (buffer_info->skb) {
 954                 dev_kfree_skb_any(buffer_info->skb);
 955                 buffer_info->skb = NULL;
 956         }
 957 }
 958
 959 /**
 960  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 961  * @adapter:      Board private structure
 962  * @buffer_info:  Buffer information structure
 963  */
 964 static void pch_gbe_unmap_and_free_rx_resource(
 965                                         struct pch_gbe_adapter *adapter,
 966                                         struct pch_gbe_buffer *buffer_info)
 967 {
 968         if (buffer_info->mapped) {
 969                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 970                                  buffer_info->length, DMA_FROM_DEVICE);
 971                 buffer_info->mapped = false;
 972         }
 973         if (buffer_info->skb) {
 974                 dev_kfree_skb_any(buffer_info->skb);
 975                 buffer_info->skb = NULL;
 976         }
 977 }
 978
 979 /**
 980  * pch_gbe_clean_tx_ring - Free Tx Buffers
 981  * @adapter:  Board private structure
 982  * @tx_ring:  Ring to be cleaned
 983  */
 984 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 985                                    struct pch_gbe_tx_ring *tx_ring)
 986 {
 987         struct pch_gbe_hw *hw = &adapter->hw;
 988         struct pch_gbe_buffer *buffer_info;
 989         unsigned long size;
 990         unsigned int i;
 991
 992         /* Free all the Tx ring sk_buffs */
 993         for (i = 0; i < tx_ring->count; i++) {
 994                 buffer_info = &tx_ring->buffer_info[i];
 995                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 996         }
 997         netdev_dbg(adapter->netdev,
 998                    "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 999
1000         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1001         memset(tx_ring->buffer_info, 0, size);
1002
1003         /* Zero out the descriptor ring */
1004         memset(tx_ring->desc, 0, tx_ring->size);
1005         tx_ring->next_to_use = 0;
1006         tx_ring->next_to_clean = 0;
1007         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
1008         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
1009 }
1010
1011 /**
1012  * pch_gbe_clean_rx_ring - Free Rx Buffers
1013  * @adapter:  Board private structure
1014  * @rx_ring:  Ring to free buffers from
1015  */
1016 static void
1017 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1018                       struct pch_gbe_rx_ring *rx_ring)
1019 {
1020         struct pch_gbe_hw *hw = &adapter->hw;
1021         struct pch_gbe_buffer *buffer_info;
1022         unsigned long size;
1023         unsigned int i;
1024
1025         /* Free all the Rx ring sk_buffs */
1026         for (i = 0; i < rx_ring->count; i++) {
1027                 buffer_info = &rx_ring->buffer_info[i];
1028                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1029         }
1030         netdev_dbg(adapter->netdev,
1031                    "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1032         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1033         memset(rx_ring->buffer_info, 0, size);
1034
1035         /* Zero out the descriptor ring */
1036         memset(rx_ring->desc, 0, rx_ring->size);
1037         rx_ring->next_to_clean = 0;
1038         rx_ring->next_to_use = 0;
1039         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1040         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1041 }
1042
1043 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1044                                     u16 duplex)
1045 {
1046         struct pch_gbe_hw *hw = &adapter->hw;
1047         unsigned long rgmii = 0;
1048
1049         /* Set the RGMII control. */
1050 #ifdef PCH_GBE_MAC_IFOP_RGMII
1051         switch (speed) {
1052         case SPEED_10:
1053                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1054                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1055                 break;
1056         case SPEED_100:
1057                 rgmii = (PCH_GBE_RGMII_RATE_25M |
1058                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1059                 break;
1060         case SPEED_1000:
1061                 rgmii = (PCH_GBE_RGMII_RATE_125M |
1062                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
1063                 break;
1064         }
1065         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1066 #else   /* GMII */
1067         rgmii = 0;
1068         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1069 #endif
1070 }
1071 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1072                               u16 duplex)
1073 {
1074         struct net_device *netdev = adapter->netdev;
1075         struct pch_gbe_hw *hw = &adapter->hw;
1076         unsigned long mode = 0;
1077
1078         /* Set the communication mode */
1079         switch (speed) {
1080         case SPEED_10:
1081                 mode = PCH_GBE_MODE_MII_ETHER;
1082                 netdev->tx_queue_len = 10;
1083                 break;
1084         case SPEED_100:
1085                 mode = PCH_GBE_MODE_MII_ETHER;
1086                 netdev->tx_queue_len = 100;
1087                 break;
1088         case SPEED_1000:
1089                 mode = PCH_GBE_MODE_GMII_ETHER;
1090                 break;
1091         }
1092         if (duplex == DUPLEX_FULL)
1093                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1094         else
1095                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1096         iowrite32(mode, &hw->reg->MODE);
1097 }
1098
1099 /**
1100  * pch_gbe_watchdog - Watchdog process
1101  * @data:  Board private structure
1102  */
1103 static void pch_gbe_watchdog(unsigned long data)
1104 {
1105         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1106         struct net_device *netdev = adapter->netdev;
1107         struct pch_gbe_hw *hw = &adapter->hw;
1108
1109         netdev_dbg(netdev, "right now = %ld\n", jiffies);
1110
1111         pch_gbe_update_stats(adapter);
1112         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1113                 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1114                 netdev->tx_queue_len = adapter->tx_queue_len;
1115                 /* mii library handles link maintenance tasks */
1116                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1117                         netdev_err(netdev, "ethtool get setting Error\n");
1118                         mod_timer(&adapter->watchdog_timer,
1119                                   round_jiffies(jiffies +
1120                                                 PCH_GBE_WATCHDOG_PERIOD));
1121                         return;
1122                 }
1123                 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1124                 hw->mac.link_duplex = cmd.duplex;
1125                 /* Set the RGMII control. */
1126                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1127                                                 hw->mac.link_duplex);
1128                 /* Set the communication mode */
1129                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1130                                  hw->mac.link_duplex);
1131                 netdev_dbg(netdev,
1132                            "Link is Up %d Mbps %s-Duplex\n",
1133                            hw->mac.link_speed,
1134                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1135                 netif_carrier_on(netdev);
1136                 netif_wake_queue(netdev);
1137         } else if ((!mii_link_ok(&adapter->mii)) &&
1138                    (netif_carrier_ok(netdev))) {
1139                 netdev_dbg(netdev, "NIC Link is Down\n");
1140                 hw->mac.link_speed = SPEED_10;
1141                 hw->mac.link_duplex = DUPLEX_HALF;
1142                 netif_carrier_off(netdev);
1143                 netif_stop_queue(netdev);
1144         }
1145         mod_timer(&adapter->watchdog_timer,
1146                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1147 }
1148
1149 /**
1150  * pch_gbe_tx_queue - Carry out queuing of the transmission data
1151  * @adapter:  Board private structure
1152  * @tx_ring:  Tx descriptor ring structure
1153  * @skb:      Sockt buffer structure
1154  */
1155 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1156                               struct pch_gbe_tx_ring *tx_ring,
1157                               struct sk_buff *skb)
1158 {
1159         struct pch_gbe_hw *hw = &adapter->hw;
1160         struct pch_gbe_tx_desc *tx_desc;
1161         struct pch_gbe_buffer *buffer_info;
1162         struct sk_buff *tmp_skb;
1163         unsigned int frame_ctrl;
1164         unsigned int ring_num;
1165
1166         /*-- Set frame control --*/
1167         frame_ctrl = 0;
1168         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1169                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1170         if (skb->ip_summed == CHECKSUM_NONE)
1171                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1172
1173         /* Performs checksum processing */
1174         /*
1175          * It is because the hardware accelerator does not support a checksum,
1176          * when the received data size is less than 64 bytes.
1177          */
1178         if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1179                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1180                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1181                 if (skb->protocol == htons(ETH_P_IP)) {
1182                         struct iphdr *iph = ip_hdr(skb);
1183                         unsigned int offset;
1184                         offset = skb_transport_offset(skb);
1185                         if (iph->protocol == IPPROTO_TCP) {
1186                                 skb->csum = 0;
1187                                 tcp_hdr(skb)->check = 0;
1188                                 skb->csum = skb_checksum(skb, offset,
1189                                                          skb->len - offset, 0);
1190                                 tcp_hdr(skb)->check =
1191                                         csum_tcpudp_magic(iph->saddr,
1192                                                           iph->daddr,
1193                                                           skb->len - offset,
1194                                                           IPPROTO_TCP,
1195                                                           skb->csum);
1196                         } else if (iph->protocol == IPPROTO_UDP) {
1197                                 skb->csum = 0;
1198                                 udp_hdr(skb)->check = 0;
1199                                 skb->csum =
1200                                         skb_checksum(skb, offset,
1201                                                      skb->len - offset, 0);
1202                                 udp_hdr(skb)->check =
1203                                         csum_tcpudp_magic(iph->saddr,
1204                                                           iph->daddr,
1205                                                           skb->len - offset,
1206                                                           IPPROTO_UDP,
1207                                                           skb->csum);
1208                         }
1209                 }
1210         }
1211
1212         ring_num = tx_ring->next_to_use;
1213         if (unlikely((ring_num + 1) == tx_ring->count))
1214                 tx_ring->next_to_use = 0;
1215         else
1216                 tx_ring->next_to_use = ring_num + 1;
1217
1218
1219         buffer_info = &tx_ring->buffer_info[ring_num];
1220         tmp_skb = buffer_info->skb;
1221
1222         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1223         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1224         tmp_skb->data[ETH_HLEN] = 0x00;
1225         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1226         tmp_skb->len = skb->len;
1227         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1228                (skb->len - ETH_HLEN));
1229         /*-- Set Buffer information --*/
1230         buffer_info->length = tmp_skb->len;
1231         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1232                                           buffer_info->length,
1233                                           DMA_TO_DEVICE);
1234         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1235                 netdev_err(adapter->netdev, "TX DMA map failed\n");
1236                 buffer_info->dma = 0;
1237                 buffer_info->time_stamp = 0;
1238                 tx_ring->next_to_use = ring_num;
1239                 return;
1240         }
1241         buffer_info->mapped = true;
1242         buffer_info->time_stamp = jiffies;
1243
1244         /*-- Set Tx descriptor --*/
1245         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1246         tx_desc->buffer_addr = (buffer_info->dma);
1247         tx_desc->length = (tmp_skb->len);
1248         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1249         tx_desc->tx_frame_ctrl = (frame_ctrl);
1250         tx_desc->gbec_status = (DSC_INIT16);
1251
1252         if (unlikely(++ring_num == tx_ring->count))
1253                 ring_num = 0;
1254
1255         /* Update software pointer of TX descriptor */
1256         iowrite32(tx_ring->dma +
1257                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1258                   &hw->reg->TX_DSC_SW_P);
1259
1260         pch_tx_timestamp(adapter, skb);
1261
1262         dev_kfree_skb_any(skb);
1263 }
1264
1265 /**
1266  * pch_gbe_update_stats - Update the board statistics counters
1267  * @adapter:  Board private structure
1268  */
1269 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1270 {
1271         struct net_device *netdev = adapter->netdev;
1272         struct pci_dev *pdev = adapter->pdev;
1273         struct pch_gbe_hw_stats *stats = &adapter->stats;
1274         unsigned long flags;
1275
1276         /*
1277          * Prevent stats update while adapter is being reset, or if the pci
1278          * connection is down.
1279          */
1280         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1281                 return;
1282
1283         spin_lock_irqsave(&adapter->stats_lock, flags);
1284
1285         /* Update device status "adapter->stats" */
1286         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1287         stats->tx_errors = stats->tx_length_errors +
1288             stats->tx_aborted_errors +
1289             stats->tx_carrier_errors + stats->tx_timeout_count;
1290
1291         /* Update network device status "adapter->net_stats" */
1292         netdev->stats.rx_packets = stats->rx_packets;
1293         netdev->stats.rx_bytes = stats->rx_bytes;
1294         netdev->stats.rx_dropped = stats->rx_dropped;
1295         netdev->stats.tx_packets = stats->tx_packets;
1296         netdev->stats.tx_bytes = stats->tx_bytes;
1297         netdev->stats.tx_dropped = stats->tx_dropped;
1298         /* Fill out the OS statistics structure */
1299         netdev->stats.multicast = stats->multicast;
1300         netdev->stats.collisions = stats->collisions;
1301         /* Rx Errors */
1302         netdev->stats.rx_errors = stats->rx_errors;
1303         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1304         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1305         /* Tx Errors */
1306         netdev->stats.tx_errors = stats->tx_errors;
1307         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1308         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1309
1310         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1311 }
1312
1313 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1314 {
1315         u32 rxdma;
1316
1317         /* Disable Receive DMA */
1318         rxdma = ioread32(&hw->reg->DMA_CTRL);
1319         rxdma &= ~PCH_GBE_RX_DMA_EN;
1320         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1321 }
1322
1323 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1324 {
1325         u32 rxdma;
1326
1327         /* Enables Receive DMA */
1328         rxdma = ioread32(&hw->reg->DMA_CTRL);
1329         rxdma |= PCH_GBE_RX_DMA_EN;
1330         iowrite32(rxdma, &hw->reg->DMA_CTRL);
1331 }
1332
1333 /**
1334  * pch_gbe_intr - Interrupt Handler
1335  * @irq:   Interrupt number
1336  * @data:  Pointer to a network interface device structure
1337  * Returns:
1338  *      - IRQ_HANDLED:  Our interrupt
1339  *      - IRQ_NONE:     Not our interrupt
1340  */
1341 static irqreturn_t pch_gbe_intr(int irq, void *data)
1342 {
1343         struct net_device *netdev = data;
1344         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1345         struct pch_gbe_hw *hw = &adapter->hw;
1346         u32 int_st;
1347         u32 int_en;
1348
1349         /* Check request status */
1350         int_st = ioread32(&hw->reg->INT_ST);
1351         int_st = int_st & ioread32(&hw->reg->INT_EN);
1352         /* When request status is no interruption factor */
1353         if (unlikely(!int_st))
1354                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1355         netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1356         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1357                 adapter->stats.intr_rx_frame_err_count++;
1358         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1359                 if (!adapter->rx_stop_flag) {
1360                         adapter->stats.intr_rx_fifo_err_count++;
1361                         netdev_dbg(netdev, "Rx fifo over run\n");
1362                         adapter->rx_stop_flag = true;
1363                         int_en = ioread32(&hw->reg->INT_EN);
1364                         iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1365                                   &hw->reg->INT_EN);
1366                         pch_gbe_disable_dma_rx(&adapter->hw);
1367                         int_st |= ioread32(&hw->reg->INT_ST);
1368                         int_st = int_st & ioread32(&hw->reg->INT_EN);
1369                 }
1370         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1371                 adapter->stats.intr_rx_dma_err_count++;
1372         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1373                 adapter->stats.intr_tx_fifo_err_count++;
1374         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1375                 adapter->stats.intr_tx_dma_err_count++;
1376         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1377                 adapter->stats.intr_tcpip_err_count++;
1378         /* When Rx descriptor is empty  */
1379         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1380                 adapter->stats.intr_rx_dsc_empty_count++;
1381                 netdev_dbg(netdev, "Rx descriptor is empty\n");
1382                 int_en = ioread32(&hw->reg->INT_EN);
1383                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1384                 if (hw->mac.tx_fc_enable) {
1385                         /* Set Pause packet */
1386                         pch_gbe_mac_set_pause_packet(hw);
1387                 }
1388         }
1389
1390         /* When request status is Receive interruption */
1391         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1392             (adapter->rx_stop_flag)) {
1393                 if (likely(napi_schedule_prep(&adapter->napi))) {
1394                         /* Enable only Rx Descriptor empty */
1395                         atomic_inc(&adapter->irq_sem);
1396                         int_en = ioread32(&hw->reg->INT_EN);
1397                         int_en &=
1398                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1399                         iowrite32(int_en, &hw->reg->INT_EN);
1400                         /* Start polling for NAPI */
1401                         __napi_schedule(&adapter->napi);
1402                 }
1403         }
1404         netdev_dbg(netdev, "return = 0x%08x  INT_EN reg = 0x%08x\n",
1405                    IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1406         return IRQ_HANDLED;
1407 }
1408
1409 /**
1410  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1411  * @adapter:       Board private structure
1412  * @rx_ring:       Rx descriptor ring
1413  * @cleaned_count: Cleaned count
1414  */
1415 static void
1416 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1417                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1418 {
1419         struct net_device *netdev = adapter->netdev;
1420         struct pci_dev *pdev = adapter->pdev;
1421         struct pch_gbe_hw *hw = &adapter->hw;
1422         struct pch_gbe_rx_desc *rx_desc;
1423         struct pch_gbe_buffer *buffer_info;
1424         struct sk_buff *skb;
1425         unsigned int i;
1426         unsigned int bufsz;
1427
1428         bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1429         i = rx_ring->next_to_use;
1430
1431         while ((cleaned_count--)) {
1432                 buffer_info = &rx_ring->buffer_info[i];
1433                 skb = netdev_alloc_skb(netdev, bufsz);
1434                 if (unlikely(!skb)) {
1435                         /* Better luck next round */
1436                         adapter->stats.rx_alloc_buff_failed++;
1437                         break;
1438                 }
1439                 /* align */
1440                 skb_reserve(skb, NET_IP_ALIGN);
1441                 buffer_info->skb = skb;
1442
1443                 buffer_info->dma = dma_map_single(&pdev->dev,
1444                                                   buffer_info->rx_buffer,
1445                                                   buffer_info->length,
1446                                                   DMA_FROM_DEVICE);
1447                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1448                         dev_kfree_skb(skb);
1449                         buffer_info->skb = NULL;
1450                         buffer_info->dma = 0;
1451                         adapter->stats.rx_alloc_buff_failed++;
1452                         break; /* while !buffer_info->skb */
1453                 }
1454                 buffer_info->mapped = true;
1455                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1456                 rx_desc->buffer_addr = (buffer_info->dma);
1457                 rx_desc->gbec_status = DSC_INIT16;
1458
1459                 netdev_dbg(netdev,
1460                            "i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1461                            i, (unsigned long long)buffer_info->dma,
1462                            buffer_info->length);
1463
1464                 if (unlikely(++i == rx_ring->count))
1465                         i = 0;
1466         }
1467         if (likely(rx_ring->next_to_use != i)) {
1468                 rx_ring->next_to_use = i;
1469                 if (unlikely(i-- == 0))
1470                         i = (rx_ring->count - 1);
1471                 iowrite32(rx_ring->dma +
1472                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1473                           &hw->reg->RX_DSC_SW_P);
1474         }
1475         return;
1476 }
1477
1478 static int
1479 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1480                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1481 {
1482         struct pci_dev *pdev = adapter->pdev;
1483         struct pch_gbe_buffer *buffer_info;
1484         unsigned int i;
1485         unsigned int bufsz;
1486         unsigned int size;
1487
1488         bufsz = adapter->rx_buffer_len;
1489
1490         size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1491         rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size,
1492                                                    &rx_ring->rx_buff_pool_logic,
1493                                                    GFP_KERNEL | __GFP_ZERO);
1494         if (!rx_ring->rx_buff_pool)
1495                 return -ENOMEM;
1496
1497         rx_ring->rx_buff_pool_size = size;
1498         for (i = 0; i < rx_ring->count; i++) {
1499                 buffer_info = &rx_ring->buffer_info[i];
1500                 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1501                 buffer_info->length = bufsz;
1502         }
1503         return 0;
1504 }
1505
1506 /**
1507  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1508  * @adapter:   Board private structure
1509  * @tx_ring:   Tx descriptor ring
1510  */
1511 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1512                                         struct pch_gbe_tx_ring *tx_ring)
1513 {
1514         struct pch_gbe_buffer *buffer_info;
1515         struct sk_buff *skb;
1516         unsigned int i;
1517         unsigned int bufsz;
1518         struct pch_gbe_tx_desc *tx_desc;
1519
1520         bufsz =
1521             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1522
1523         for (i = 0; i < tx_ring->count; i++) {
1524                 buffer_info = &tx_ring->buffer_info[i];
1525                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1526                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1527                 buffer_info->skb = skb;
1528                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1529                 tx_desc->gbec_status = (DSC_INIT16);
1530         }
1531         return;
1532 }
1533
1534 /**
1535  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1536  * @adapter:   Board private structure
1537  * @tx_ring:   Tx descriptor ring
1538  * Returns:
1539  *      true:  Cleaned the descriptor
1540  *      false: Not cleaned the descriptor
1541  */
1542 static bool
1543 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1544                  struct pch_gbe_tx_ring *tx_ring)
1545 {
1546         struct pch_gbe_tx_desc *tx_desc;
1547         struct pch_gbe_buffer *buffer_info;
1548         struct sk_buff *skb;
1549         unsigned int i;
1550         unsigned int cleaned_count = 0;
1551         bool cleaned = false;
1552         int unused, thresh;
1553
1554         netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1555                    tx_ring->next_to_clean);
1556
1557         i = tx_ring->next_to_clean;
1558         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1559         netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
1560                    tx_desc->gbec_status, tx_desc->dma_status);
1561
1562         unused = PCH_GBE_DESC_UNUSED(tx_ring);
1563         thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1564         if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1565         {  /* current marked clean, tx queue filling up, do extra clean */
1566                 int j, k;
1567                 if (unused < 8) {  /* tx queue nearly full */
1568                         netdev_dbg(adapter->netdev,
1569                                    "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1570                                    tx_ring->next_to_clean, tx_ring->next_to_use,
1571                                    unused);
1572                 }
1573
1574                 /* current marked clean, scan for more that need cleaning. */
1575                 k = i;
1576                 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1577                 {
1578                         tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1579                         if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1580                         if (++k >= tx_ring->count) k = 0;  /*increment, wrap*/
1581                 }
1582                 if (j < PCH_GBE_TX_WEIGHT) {
1583                         netdev_dbg(adapter->netdev,
1584                                    "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1585                                    unused, j, i, k, tx_ring->next_to_use,
1586                                    tx_desc->gbec_status);
1587                         i = k;  /*found one to clean, usu gbec_status==2000.*/
1588                 }
1589         }
1590
1591         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1592                 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1593                            tx_desc->gbec_status);
1594                 buffer_info = &tx_ring->buffer_info[i];
1595                 skb = buffer_info->skb;
1596                 cleaned = true;
1597
1598                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1599                         adapter->stats.tx_aborted_errors++;
1600                         netdev_err(adapter->netdev, "Transfer Abort Error\n");
1601                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1602                           ) {
1603                         adapter->stats.tx_carrier_errors++;
1604                         netdev_err(adapter->netdev,
1605                                    "Transfer Carrier Sense Error\n");
1606                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1607                           ) {
1608                         adapter->stats.tx_aborted_errors++;
1609                         netdev_err(adapter->netdev,
1610                                    "Transfer Collision Abort Error\n");
1611                 } else if ((tx_desc->gbec_status &
1612                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1613                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1614                         adapter->stats.collisions++;
1615                         adapter->stats.tx_packets++;
1616                         adapter->stats.tx_bytes += skb->len;
1617                         netdev_dbg(adapter->netdev, "Transfer Collision\n");
1618                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1619                           ) {
1620                         adapter->stats.tx_packets++;
1621                         adapter->stats.tx_bytes += skb->len;
1622                 }
1623                 if (buffer_info->mapped) {
1624                         netdev_dbg(adapter->netdev,
1625                                    "unmap buffer_info->dma : %d\n", i);
1626                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1627                                          buffer_info->length, DMA_TO_DEVICE);
1628                         buffer_info->mapped = false;
1629                 }
1630                 if (buffer_info->skb) {
1631                         netdev_dbg(adapter->netdev,
1632                                    "trim buffer_info->skb : %d\n", i);
1633                         skb_trim(buffer_info->skb, 0);
1634                 }
1635                 tx_desc->gbec_status = DSC_INIT16;
1636                 if (unlikely(++i == tx_ring->count))
1637                         i = 0;
1638                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1639
1640                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1641                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1642                         cleaned = false;
1643                         break;
1644                 }
1645         }
1646         netdev_dbg(adapter->netdev,
1647                    "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1648                    cleaned_count);
1649         if (cleaned_count > 0)  { /*skip this if nothing cleaned*/
1650                 /* Recover from running out of Tx resources in xmit_frame */
1651                 spin_lock(&tx_ring->tx_lock);
1652                 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1653                 {
1654                         netif_wake_queue(adapter->netdev);
1655                         adapter->stats.tx_restart_count++;
1656                         netdev_dbg(adapter->netdev, "Tx wake queue\n");
1657                 }
1658
1659                 tx_ring->next_to_clean = i;
1660
1661                 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1662                            tx_ring->next_to_clean);
1663                 spin_unlock(&tx_ring->tx_lock);
1664         }
1665         return cleaned;
1666 }
1667
1668 /**
1669  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1670  * @adapter:     Board private structure
1671  * @rx_ring:     Rx descriptor ring
1672  * @work_done:   Completed count
1673  * @work_to_do:  Request count
1674  * Returns:
1675  *      true:  Cleaned the descriptor
1676  *      false: Not cleaned the descriptor
1677  */
1678 static bool
1679 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1680                  struct pch_gbe_rx_ring *rx_ring,
1681                  int *work_done, int work_to_do)
1682 {
1683         struct net_device *netdev = adapter->netdev;
1684         struct pci_dev *pdev = adapter->pdev;
1685         struct pch_gbe_buffer *buffer_info;
1686         struct pch_gbe_rx_desc *rx_desc;
1687         u32 length;
1688         unsigned int i;
1689         unsigned int cleaned_count = 0;
1690         bool cleaned = false;
1691         struct sk_buff *skb;
1692         u8 dma_status;
1693         u16 gbec_status;
1694         u32 tcp_ip_status;
1695
1696         i = rx_ring->next_to_clean;
1697
1698         while (*work_done < work_to_do) {
1699                 /* Check Rx descriptor status */
1700                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1701                 if (rx_desc->gbec_status == DSC_INIT16)
1702                         break;
1703                 cleaned = true;
1704                 cleaned_count++;
1705
1706                 dma_status = rx_desc->dma_status;
1707                 gbec_status = rx_desc->gbec_status;
1708                 tcp_ip_status = rx_desc->tcp_ip_status;
1709                 rx_desc->gbec_status = DSC_INIT16;
1710                 buffer_info = &rx_ring->buffer_info[i];
1711                 skb = buffer_info->skb;
1712                 buffer_info->skb = NULL;
1713
1714                 /* unmap dma */
1715                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1716                                    buffer_info->length, DMA_FROM_DEVICE);
1717                 buffer_info->mapped = false;
1718
1719                 netdev_dbg(netdev,
1720                            "RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x]  BufInf = 0x%p\n",
1721                            i, dma_status, gbec_status, tcp_ip_status,
1722                            buffer_info);
1723                 /* Error check */
1724                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1725                         adapter->stats.rx_frame_errors++;
1726                         netdev_err(netdev, "Receive Not Octal Error\n");
1727                 } else if (unlikely(gbec_status &
1728                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1729                         adapter->stats.rx_frame_errors++;
1730                         netdev_err(netdev, "Receive Nibble Error\n");
1731                 } else if (unlikely(gbec_status &
1732                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1733                         adapter->stats.rx_crc_errors++;
1734                         netdev_err(netdev, "Receive CRC Error\n");
1735                 } else {
1736                         /* get receive length */
1737                         /* length convert[-3], length includes FCS length */
1738                         length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1739                         if (rx_desc->rx_words_eob & 0x02)
1740                                 length = length - 4;
1741                         /*
1742                          * buffer_info->rx_buffer: [Header:14][payload]
1743                          * skb->data: [Reserve:2][Header:14][payload]
1744                          */
1745                         memcpy(skb->data, buffer_info->rx_buffer, length);
1746
1747                         /* update status of driver */
1748                         adapter->stats.rx_bytes += length;
1749                         adapter->stats.rx_packets++;
1750                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1751                                 adapter->stats.multicast++;
1752                         /* Write meta date of skb */
1753                         skb_put(skb, length);
1754
1755                         pch_rx_timestamp(adapter, skb);
1756
1757                         skb->protocol = eth_type_trans(skb, netdev);
1758                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1759                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1760                         else
1761                                 skb->ip_summed = CHECKSUM_NONE;
1762
1763                         napi_gro_receive(&adapter->napi, skb);
1764                         (*work_done)++;
1765                         netdev_dbg(netdev,
1766                                    "Receive skb->ip_summed: %d length: %d\n",
1767                                    skb->ip_summed, length);
1768                 }
1769                 /* return some buffers to hardware, one at a time is too slow */
1770                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1771                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1772                                                  cleaned_count);
1773                         cleaned_count = 0;
1774                 }
1775                 if (++i == rx_ring->count)
1776                         i = 0;
1777         }
1778         rx_ring->next_to_clean = i;
1779         if (cleaned_count)
1780                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1781         return cleaned;
1782 }
1783
1784 /**
1785  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1786  * @adapter:  Board private structure
1787  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1788  * Returns:
1789  *      0:              Successfully
1790  *      Negative value: Failed
1791  */
1792 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1793                                 struct pch_gbe_tx_ring *tx_ring)
1794 {
1795         struct pci_dev *pdev = adapter->pdev;
1796         struct pch_gbe_tx_desc *tx_desc;
1797         int size;
1798         int desNo;
1799
1800         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1801         tx_ring->buffer_info = vzalloc(size);
1802         if (!tx_ring->buffer_info)
1803                 return -ENOMEM;
1804
1805         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1806
1807         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1808                                            &tx_ring->dma,
1809                                            GFP_KERNEL | __GFP_ZERO);
1810         if (!tx_ring->desc) {
1811                 vfree(tx_ring->buffer_info);
1812                 return -ENOMEM;
1813         }
1814
1815         tx_ring->next_to_use = 0;
1816         tx_ring->next_to_clean = 0;
1817         spin_lock_init(&tx_ring->tx_lock);
1818
1819         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1820                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1821                 tx_desc->gbec_status = DSC_INIT16;
1822         }
1823         netdev_dbg(adapter->netdev,
1824                    "tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1825                    tx_ring->desc, (unsigned long long)tx_ring->dma,
1826                    tx_ring->next_to_clean, tx_ring->next_to_use);
1827         return 0;
1828 }
1829
1830 /**
1831  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1832  * @adapter:  Board private structure
1833  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1834  * Returns:
1835  *      0:              Successfully
1836  *      Negative value: Failed
1837  */
1838 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1839                                 struct pch_gbe_rx_ring *rx_ring)
1840 {
1841         struct pci_dev *pdev = adapter->pdev;
1842         struct pch_gbe_rx_desc *rx_desc;
1843         int size;
1844         int desNo;
1845
1846         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1847         rx_ring->buffer_info = vzalloc(size);
1848         if (!rx_ring->buffer_info)
1849                 return -ENOMEM;
1850
1851         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1852         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1853                                            &rx_ring->dma,
1854                                            GFP_KERNEL | __GFP_ZERO);
1855         if (!rx_ring->desc) {
1856                 vfree(rx_ring->buffer_info);
1857                 return -ENOMEM;
1858         }
1859         rx_ring->next_to_clean = 0;
1860         rx_ring->next_to_use = 0;
1861         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1862                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1863                 rx_desc->gbec_status = DSC_INIT16;
1864         }
1865         netdev_dbg(adapter->netdev,
1866                    "rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1867                    rx_ring->desc, (unsigned long long)rx_ring->dma,
1868                    rx_ring->next_to_clean, rx_ring->next_to_use);
1869         return 0;
1870 }
1871
1872 /**
1873  * pch_gbe_free_tx_resources - Free Tx Resources
1874  * @adapter:  Board private structure
1875  * @tx_ring:  Tx descriptor ring for a specific queue
1876  */
1877 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1878                                 struct pch_gbe_tx_ring *tx_ring)
1879 {
1880         struct pci_dev *pdev = adapter->pdev;
1881
1882         pch_gbe_clean_tx_ring(adapter, tx_ring);
1883         vfree(tx_ring->buffer_info);
1884         tx_ring->buffer_info = NULL;
1885         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1886         tx_ring->desc = NULL;
1887 }
1888
1889 /**
1890  * pch_gbe_free_rx_resources - Free Rx Resources
1891  * @adapter:  Board private structure
1892  * @rx_ring:  Ring to clean the resources from
1893  */
1894 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1895                                 struct pch_gbe_rx_ring *rx_ring)
1896 {
1897         struct pci_dev *pdev = adapter->pdev;
1898
1899         pch_gbe_clean_rx_ring(adapter, rx_ring);
1900         vfree(rx_ring->buffer_info);
1901         rx_ring->buffer_info = NULL;
1902         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1903         rx_ring->desc = NULL;
1904 }
1905
1906 /**
1907  * pch_gbe_request_irq - Allocate an interrupt line
1908  * @adapter:  Board private structure
1909  * Returns:
1910  *      0:              Successfully
1911  *      Negative value: Failed
1912  */
1913 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1914 {
1915         struct net_device *netdev = adapter->netdev;
1916         int err;
1917         int flags;
1918
1919         flags = IRQF_SHARED;
1920         adapter->have_msi = false;
1921         err = pci_enable_msi(adapter->pdev);
1922         netdev_dbg(netdev, "call pci_enable_msi\n");
1923         if (err) {
1924                 netdev_dbg(netdev, "call pci_enable_msi - Error: %d\n", err);
1925         } else {
1926                 flags = 0;
1927                 adapter->have_msi = true;
1928         }
1929         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1930                           flags, netdev->name, netdev);
1931         if (err)
1932                 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1933                            err);
1934         netdev_dbg(netdev,
1935                    "adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1936                    adapter->have_msi, flags, err);
1937         return err;
1938 }
1939
1940
1941 /**
1942  * pch_gbe_up - Up GbE network device
1943  * @adapter:  Board private structure
1944  * Returns:
1945  *      0:              Successfully
1946  *      Negative value: Failed
1947  */
1948 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1949 {
1950         struct net_device *netdev = adapter->netdev;
1951         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1952         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1953         int err = -EINVAL;
1954
1955         /* Ensure we have a valid MAC */
1956         if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1957                 netdev_err(netdev, "Error: Invalid MAC address\n");
1958                 goto out;
1959         }
1960
1961         /* hardware has been reset, we need to reload some things */
1962         pch_gbe_set_multi(netdev);
1963
1964         pch_gbe_setup_tctl(adapter);
1965         pch_gbe_configure_tx(adapter);
1966         pch_gbe_setup_rctl(adapter);
1967         pch_gbe_configure_rx(adapter);
1968
1969         err = pch_gbe_request_irq(adapter);
1970         if (err) {
1971                 netdev_err(netdev,
1972                            "Error: can't bring device up - irq request failed\n");
1973                 goto out;
1974         }
1975         err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1976         if (err) {
1977                 netdev_err(netdev,
1978                            "Error: can't bring device up - alloc rx buffers pool failed\n");
1979                 goto freeirq;
1980         }
1981         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1982         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1983         adapter->tx_queue_len = netdev->tx_queue_len;
1984         pch_gbe_enable_dma_rx(&adapter->hw);
1985         pch_gbe_enable_mac_rx(&adapter->hw);
1986
1987         mod_timer(&adapter->watchdog_timer, jiffies);
1988
1989         napi_enable(&adapter->napi);
1990         pch_gbe_irq_enable(adapter);
1991         netif_start_queue(adapter->netdev);
1992
1993         return 0;
1994
1995 freeirq:
1996         pch_gbe_free_irq(adapter);
1997 out:
1998         return err;
1999 }
2000
2001 /**
2002  * pch_gbe_down - Down GbE network device
2003  * @adapter:  Board private structure
2004  */
2005 void pch_gbe_down(struct pch_gbe_adapter *adapter)
2006 {
2007         struct net_device *netdev = adapter->netdev;
2008         struct pci_dev *pdev = adapter->pdev;
2009         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
2010
2011         /* signal that we're down so the interrupt handler does not
2012          * reschedule our watchdog timer */
2013         napi_disable(&adapter->napi);
2014         atomic_set(&adapter->irq_sem, 0);
2015
2016         pch_gbe_irq_disable(adapter);
2017         pch_gbe_free_irq(adapter);
2018
2019         del_timer_sync(&adapter->watchdog_timer);
2020
2021         netdev->tx_queue_len = adapter->tx_queue_len;
2022         netif_carrier_off(netdev);
2023         netif_stop_queue(netdev);
2024
2025         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2026                 pch_gbe_reset(adapter);
2027         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2028         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2029
2030         pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2031                             rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2032         rx_ring->rx_buff_pool_logic = 0;
2033         rx_ring->rx_buff_pool_size = 0;
2034         rx_ring->rx_buff_pool = NULL;
2035 }
2036
2037 /**
2038  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2039  * @adapter:  Board private structure to initialize
2040  * Returns:
2041  *      0:              Successfully
2042  *      Negative value: Failed
2043  */
2044 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2045 {
2046         struct pch_gbe_hw *hw = &adapter->hw;
2047         struct net_device *netdev = adapter->netdev;
2048
2049         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2050         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2051         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2052
2053         /* Initialize the hardware-specific values */
2054         if (pch_gbe_hal_setup_init_funcs(hw)) {
2055                 netdev_err(netdev, "Hardware Initialization Failure\n");
2056                 return -EIO;
2057         }
2058         if (pch_gbe_alloc_queues(adapter)) {
2059                 netdev_err(netdev, "Unable to allocate memory for queues\n");
2060                 return -ENOMEM;
2061         }
2062         spin_lock_init(&adapter->hw.miim_lock);
2063         spin_lock_init(&adapter->stats_lock);
2064         spin_lock_init(&adapter->ethtool_lock);
2065         atomic_set(&adapter->irq_sem, 0);
2066         pch_gbe_irq_disable(adapter);
2067
2068         pch_gbe_init_stats(adapter);
2069
2070         netdev_dbg(netdev,
2071                    "rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
2072                    (u32) adapter->rx_buffer_len,
2073                    hw->mac.min_frame_size, hw->mac.max_frame_size);
2074         return 0;
2075 }
2076
2077 /**
2078  * pch_gbe_open - Called when a network interface is made active
2079  * @netdev:     Network interface device structure
2080  * Returns:
2081  *      0:              Successfully
2082  *      Negative value: Failed
2083  */
2084 static int pch_gbe_open(struct net_device *netdev)
2085 {
2086         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2087         struct pch_gbe_hw *hw = &adapter->hw;
2088         int err;
2089
2090         /* allocate transmit descriptors */
2091         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2092         if (err)
2093                 goto err_setup_tx;
2094         /* allocate receive descriptors */
2095         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2096         if (err)
2097                 goto err_setup_rx;
2098         pch_gbe_hal_power_up_phy(hw);
2099         err = pch_gbe_up(adapter);
2100         if (err)
2101                 goto err_up;
2102         netdev_dbg(netdev, "Success End\n");
2103         return 0;
2104
2105 err_up:
2106         if (!adapter->wake_up_evt)
2107                 pch_gbe_hal_power_down_phy(hw);
2108         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2109 err_setup_rx:
2110         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2111 err_setup_tx:
2112         pch_gbe_reset(adapter);
2113         netdev_err(netdev, "Error End\n");
2114         return err;
2115 }
2116
2117 /**
2118  * pch_gbe_stop - Disables a network interface
2119  * @netdev:  Network interface device structure
2120  * Returns:
2121  *      0: Successfully
2122  */
2123 static int pch_gbe_stop(struct net_device *netdev)
2124 {
2125         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2126         struct pch_gbe_hw *hw = &adapter->hw;
2127
2128         pch_gbe_down(adapter);
2129         if (!adapter->wake_up_evt)
2130                 pch_gbe_hal_power_down_phy(hw);
2131         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2132         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2133         return 0;
2134 }
2135
2136 /**
2137  * pch_gbe_xmit_frame - Packet transmitting start
2138  * @skb:     Socket buffer structure
2139  * @netdev:  Network interface device structure
2140  * Returns:
2141  *      - NETDEV_TX_OK:   Normal end
2142  *      - NETDEV_TX_BUSY: Error end
2143  */
2144 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2145 {
2146         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2147         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2148         unsigned long flags;
2149
2150         if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
2151                 /* Collision - tell upper layer to requeue */
2152                 return NETDEV_TX_LOCKED;
2153         }
2154         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2155                 netif_stop_queue(netdev);
2156                 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2157                 netdev_dbg(netdev,
2158                            "Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
2159                            tx_ring->next_to_use, tx_ring->next_to_clean);
2160                 return NETDEV_TX_BUSY;
2161         }
2162
2163         /* CRC,ITAG no support */
2164         pch_gbe_tx_queue(adapter, tx_ring, skb);
2165         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2166         return NETDEV_TX_OK;
2167 }
2168
2169 /**
2170  * pch_gbe_get_stats - Get System Network Statistics
2171  * @netdev:  Network interface device structure
2172  * Returns:  The current stats
2173  */
2174 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2175 {
2176         /* only return the current stats */
2177         return &netdev->stats;
2178 }
2179
2180 /**
2181  * pch_gbe_set_multi - Multicast and Promiscuous mode set
2182  * @netdev:   Network interface device structure
2183  */
2184 static void pch_gbe_set_multi(struct net_device *netdev)
2185 {
2186         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2187         struct pch_gbe_hw *hw = &adapter->hw;
2188         struct netdev_hw_addr *ha;
2189         u8 *mta_list;
2190         u32 rctl;
2191         int i;
2192         int mc_count;
2193
2194         netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2195
2196         /* Check for Promiscuous and All Multicast modes */
2197         rctl = ioread32(&hw->reg->RX_MODE);
2198         mc_count = netdev_mc_count(netdev);
2199         if ((netdev->flags & IFF_PROMISC)) {
2200                 rctl &= ~PCH_GBE_ADD_FIL_EN;
2201                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2202         } else if ((netdev->flags & IFF_ALLMULTI)) {
2203                 /* all the multicasting receive permissions */
2204                 rctl |= PCH_GBE_ADD_FIL_EN;
2205                 rctl &= ~PCH_GBE_MLT_FIL_EN;
2206         } else {
2207                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2208                         /* all the multicasting receive permissions */
2209                         rctl |= PCH_GBE_ADD_FIL_EN;
2210                         rctl &= ~PCH_GBE_MLT_FIL_EN;
2211                 } else {
2212                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2213                 }
2214         }
2215         iowrite32(rctl, &hw->reg->RX_MODE);
2216
2217         if (mc_count >= PCH_GBE_MAR_ENTRIES)
2218                 return;
2219         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2220         if (!mta_list)
2221                 return;
2222
2223         /* The shared function expects a packed array of only addresses. */
2224         i = 0;
2225         netdev_for_each_mc_addr(ha, netdev) {
2226                 if (i == mc_count)
2227                         break;
2228                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2229         }
2230         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2231                                         PCH_GBE_MAR_ENTRIES);
2232         kfree(mta_list);
2233
2234         netdev_dbg(netdev,
2235                  "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
2236                  ioread32(&hw->reg->RX_MODE), mc_count);
2237 }
2238
2239 /**
2240  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2241  * @netdev: Network interface device structure
2242  * @addr:   Pointer to an address structure
2243  * Returns:
2244  *      0:              Successfully
2245  *      -EADDRNOTAVAIL: Failed
2246  */
2247 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2248 {
2249         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2250         struct sockaddr *skaddr = addr;
2251         int ret_val;
2252
2253         if (!is_valid_ether_addr(skaddr->sa_data)) {
2254                 ret_val = -EADDRNOTAVAIL;
2255         } else {
2256                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2257                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2258                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2259                 ret_val = 0;
2260         }
2261         netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2262         netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2263         netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2264         netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2265                    ioread32(&adapter->hw.reg->mac_adr[0].high),
2266                    ioread32(&adapter->hw.reg->mac_adr[0].low));
2267         return ret_val;
2268 }
2269
2270 /**
2271  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2272  * @netdev:   Network interface device structure
2273  * @new_mtu:  New value for maximum frame size
2274  * Returns:
2275  *      0:              Successfully
2276  *      -EINVAL:        Failed
2277  */
2278 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2279 {
2280         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2281         int max_frame;
2282         unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2283         int err;
2284
2285         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2286         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2287                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2288                 netdev_err(netdev, "Invalid MTU setting\n");
2289                 return -EINVAL;
2290         }
2291         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2292                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2293         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2294                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2295         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2296                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2297         else
2298                 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2299
2300         if (netif_running(netdev)) {
2301                 pch_gbe_down(adapter);
2302                 err = pch_gbe_up(adapter);
2303                 if (err) {
2304                         adapter->rx_buffer_len = old_rx_buffer_len;
2305                         pch_gbe_up(adapter);
2306                         return err;
2307                 } else {
2308                         netdev->mtu = new_mtu;
2309                         adapter->hw.mac.max_frame_size = max_frame;
2310                 }
2311         } else {
2312                 pch_gbe_reset(adapter);
2313                 netdev->mtu = new_mtu;
2314                 adapter->hw.mac.max_frame_size = max_frame;
2315         }
2316
2317         netdev_dbg(netdev,
2318                    "max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2319                    max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2320                    adapter->hw.mac.max_frame_size);
2321         return 0;
2322 }
2323
2324 /**
2325  * pch_gbe_set_features - Reset device after features changed
2326  * @netdev:   Network interface device structure
2327  * @features:  New features
2328  * Returns:
2329  *      0:              HW state updated successfully
2330  */
2331 static int pch_gbe_set_features(struct net_device *netdev,
2332         netdev_features_t features)
2333 {
2334         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2335         netdev_features_t changed = features ^ netdev->features;
2336
2337         if (!(changed & NETIF_F_RXCSUM))
2338                 return 0;
2339
2340         if (netif_running(netdev))
2341                 pch_gbe_reinit_locked(adapter);
2342         else
2343                 pch_gbe_reset(adapter);
2344
2345         return 0;
2346 }
2347
2348 /**
2349  * pch_gbe_ioctl - Controls register through a MII interface
2350  * @netdev:   Network interface device structure
2351  * @ifr:      Pointer to ifr structure
2352  * @cmd:      Control command
2353  * Returns:
2354  *      0:      Successfully
2355  *      Negative value: Failed
2356  */
2357 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2358 {
2359         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2360
2361         netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2362
2363         if (cmd == SIOCSHWTSTAMP)
2364                 return hwtstamp_ioctl(netdev, ifr, cmd);
2365
2366         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2367 }
2368
2369 /**
2370  * pch_gbe_tx_timeout - Respond to a Tx Hang
2371  * @netdev:   Network interface device structure
2372  */
2373 static void pch_gbe_tx_timeout(struct net_device *netdev)
2374 {
2375         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2376
2377         /* Do the reset outside of interrupt context */
2378         adapter->stats.tx_timeout_count++;
2379         schedule_work(&adapter->reset_task);
2380 }
2381
2382 /**
2383  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2384  * @napi:    Pointer of polling device struct
2385  * @budget:  The maximum number of a packet
2386  * Returns:
2387  *      false:  Exit the polling mode
2388  *      true:   Continue the polling mode
2389  */
2390 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2391 {
2392         struct pch_gbe_adapter *adapter =
2393             container_of(napi, struct pch_gbe_adapter, napi);
2394         int work_done = 0;
2395         bool poll_end_flag = false;
2396         bool cleaned = false;
2397
2398         netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2399
2400         pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2401         cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2402
2403         if (cleaned)
2404                 work_done = budget;
2405         /* If no Tx and not enough Rx work done,
2406          * exit the polling mode
2407          */
2408         if (work_done < budget)
2409                 poll_end_flag = true;
2410
2411         if (poll_end_flag) {
2412                 napi_complete(napi);
2413                 pch_gbe_irq_enable(adapter);
2414         }
2415
2416         if (adapter->rx_stop_flag) {
2417                 adapter->rx_stop_flag = false;
2418                 pch_gbe_enable_dma_rx(&adapter->hw);
2419         }
2420
2421         netdev_dbg(adapter->netdev,
2422                    "poll_end_flag : %d  work_done : %d  budget : %d\n",
2423                    poll_end_flag, work_done, budget);
2424
2425         return work_done;
2426 }
2427
2428 #ifdef CONFIG_NET_POLL_CONTROLLER
2429 /**
2430  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2431  * @netdev:  Network interface device structure
2432  */
2433 static void pch_gbe_netpoll(struct net_device *netdev)
2434 {
2435         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2436
2437         disable_irq(adapter->pdev->irq);
2438         pch_gbe_intr(adapter->pdev->irq, netdev);
2439         enable_irq(adapter->pdev->irq);
2440 }
2441 #endif
2442
2443 static const struct net_device_ops pch_gbe_netdev_ops = {
2444         .ndo_open = pch_gbe_open,
2445         .ndo_stop = pch_gbe_stop,
2446         .ndo_start_xmit = pch_gbe_xmit_frame,
2447         .ndo_get_stats = pch_gbe_get_stats,
2448         .ndo_set_mac_address = pch_gbe_set_mac,
2449         .ndo_tx_timeout = pch_gbe_tx_timeout,
2450         .ndo_change_mtu = pch_gbe_change_mtu,
2451         .ndo_set_features = pch_gbe_set_features,
2452         .ndo_do_ioctl = pch_gbe_ioctl,
2453         .ndo_set_rx_mode = pch_gbe_set_multi,
2454 #ifdef CONFIG_NET_POLL_CONTROLLER
2455         .ndo_poll_controller = pch_gbe_netpoll,
2456 #endif
2457 };
2458
2459 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2460                                                 pci_channel_state_t state)
2461 {
2462         struct net_device *netdev = pci_get_drvdata(pdev);
2463         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2464
2465         netif_device_detach(netdev);
2466         if (netif_running(netdev))
2467                 pch_gbe_down(adapter);
2468         pci_disable_device(pdev);
2469         /* Request a slot slot reset. */
2470         return PCI_ERS_RESULT_NEED_RESET;
2471 }
2472
2473 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2474 {
2475         struct net_device *netdev = pci_get_drvdata(pdev);
2476         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2477         struct pch_gbe_hw *hw = &adapter->hw;
2478
2479         if (pci_enable_device(pdev)) {
2480                 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2481                 return PCI_ERS_RESULT_DISCONNECT;
2482         }
2483         pci_set_master(pdev);
2484         pci_enable_wake(pdev, PCI_D0, 0);
2485         pch_gbe_hal_power_up_phy(hw);
2486         pch_gbe_reset(adapter);
2487         /* Clear wake up status */
2488         pch_gbe_mac_set_wol_event(hw, 0);
2489
2490         return PCI_ERS_RESULT_RECOVERED;
2491 }
2492
2493 static void pch_gbe_io_resume(struct pci_dev *pdev)
2494 {
2495         struct net_device *netdev = pci_get_drvdata(pdev);
2496         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2497
2498         if (netif_running(netdev)) {
2499                 if (pch_gbe_up(adapter)) {
2500                         netdev_dbg(netdev,
2501                                    "can't bring device back up after reset\n");
2502                         return;
2503                 }
2504         }
2505         netif_device_attach(netdev);
2506 }
2507
2508 static int __pch_gbe_suspend(struct pci_dev *pdev)
2509 {
2510         struct net_device *netdev = pci_get_drvdata(pdev);
2511         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2512         struct pch_gbe_hw *hw = &adapter->hw;
2513         u32 wufc = adapter->wake_up_evt;
2514         int retval = 0;
2515
2516         netif_device_detach(netdev);
2517         if (netif_running(netdev))
2518                 pch_gbe_down(adapter);
2519         if (wufc) {
2520                 pch_gbe_set_multi(netdev);
2521                 pch_gbe_setup_rctl(adapter);
2522                 pch_gbe_configure_rx(adapter);
2523                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2524                                         hw->mac.link_duplex);
2525                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2526                                         hw->mac.link_duplex);
2527                 pch_gbe_mac_set_wol_event(hw, wufc);
2528                 pci_disable_device(pdev);
2529         } else {
2530                 pch_gbe_hal_power_down_phy(hw);
2531                 pch_gbe_mac_set_wol_event(hw, wufc);
2532                 pci_disable_device(pdev);
2533         }
2534         return retval;
2535 }
2536
2537 #ifdef CONFIG_PM
2538 static int pch_gbe_suspend(struct device *device)
2539 {
2540         struct pci_dev *pdev = to_pci_dev(device);
2541
2542         return __pch_gbe_suspend(pdev);
2543 }
2544
2545 static int pch_gbe_resume(struct device *device)
2546 {
2547         struct pci_dev *pdev = to_pci_dev(device);
2548         struct net_device *netdev = pci_get_drvdata(pdev);
2549         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2550         struct pch_gbe_hw *hw = &adapter->hw;
2551         u32 err;
2552
2553         err = pci_enable_device(pdev);
2554         if (err) {
2555                 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2556                 return err;
2557         }
2558         pci_set_master(pdev);
2559         pch_gbe_hal_power_up_phy(hw);
2560         pch_gbe_reset(adapter);
2561         /* Clear wake on lan control and status */
2562         pch_gbe_mac_set_wol_event(hw, 0);
2563
2564         if (netif_running(netdev))
2565                 pch_gbe_up(adapter);
2566         netif_device_attach(netdev);
2567
2568         return 0;
2569 }
2570 #endif /* CONFIG_PM */
2571
2572 static void pch_gbe_shutdown(struct pci_dev *pdev)
2573 {
2574         __pch_gbe_suspend(pdev);
2575         if (system_state == SYSTEM_POWER_OFF) {
2576                 pci_wake_from_d3(pdev, true);
2577                 pci_set_power_state(pdev, PCI_D3hot);
2578         }
2579 }
2580
2581 static void pch_gbe_remove(struct pci_dev *pdev)
2582 {
2583         struct net_device *netdev = pci_get_drvdata(pdev);
2584         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2585
2586         cancel_work_sync(&adapter->reset_task);
2587         unregister_netdev(netdev);
2588
2589         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2590
2591         free_netdev(netdev);
2592 }
2593
2594 static int pch_gbe_probe(struct pci_dev *pdev,
2595                           const struct pci_device_id *pci_id)
2596 {
2597         struct net_device *netdev;
2598         struct pch_gbe_adapter *adapter;
2599         int ret;
2600
2601         ret = pcim_enable_device(pdev);
2602         if (ret)
2603                 return ret;
2604
2605         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2606                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2607                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2608                 if (ret) {
2609                         ret = pci_set_consistent_dma_mask(pdev,
2610                                                           DMA_BIT_MASK(32));
2611                         if (ret) {
2612                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2613                                         "configuration, aborting\n");
2614                                 return ret;
2615                         }
2616                 }
2617         }
2618
2619         ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2620         if (ret) {
2621                 dev_err(&pdev->dev,
2622                         "ERR: Can't reserve PCI I/O and memory resources\n");
2623                 return ret;
2624         }
2625         pci_set_master(pdev);
2626
2627         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2628         if (!netdev)
2629                 return -ENOMEM;
2630         SET_NETDEV_DEV(netdev, &pdev->dev);
2631
2632         pci_set_drvdata(pdev, netdev);
2633         adapter = netdev_priv(netdev);
2634         adapter->netdev = netdev;
2635         adapter->pdev = pdev;
2636         adapter->hw.back = adapter;
2637         adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2638
2639         adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2640                                                PCI_DEVFN(12, 4));
2641         if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
2642                 dev_err(&pdev->dev, "Bad ptp filter\n");
2643                 ret = -EINVAL;
2644                 goto err_free_netdev;
2645         }
2646
2647         netdev->netdev_ops = &pch_gbe_netdev_ops;
2648         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2649         netif_napi_add(netdev, &adapter->napi,
2650                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2651         netdev->hw_features = NETIF_F_RXCSUM |
2652                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2653         netdev->features = netdev->hw_features;
2654         pch_gbe_set_ethtool_ops(netdev);
2655
2656         pch_gbe_mac_load_mac_addr(&adapter->hw);
2657         pch_gbe_mac_reset_hw(&adapter->hw);
2658
2659         /* setup the private structure */
2660         ret = pch_gbe_sw_init(adapter);
2661         if (ret)
2662                 goto err_free_netdev;
2663
2664         /* Initialize PHY */
2665         ret = pch_gbe_init_phy(adapter);
2666         if (ret) {
2667                 dev_err(&pdev->dev, "PHY initialize error\n");
2668                 goto err_free_adapter;
2669         }
2670         pch_gbe_hal_get_bus_info(&adapter->hw);
2671
2672         /* Read the MAC address. and store to the private data */
2673         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2674         if (ret) {
2675                 dev_err(&pdev->dev, "MAC address Read Error\n");
2676                 goto err_free_adapter;
2677         }
2678
2679         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2680         if (!is_valid_ether_addr(netdev->dev_addr)) {
2681                 /*
2682                  * If the MAC is invalid (or just missing), display a warning
2683                  * but do not abort setting up the device. pch_gbe_up will
2684                  * prevent the interface from being brought up until a valid MAC
2685                  * is set.
2686                  */
2687                 dev_err(&pdev->dev, "Invalid MAC address, "
2688                                     "interface disabled.\n");
2689         }
2690         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2691                     (unsigned long)adapter);
2692
2693         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2694
2695         pch_gbe_check_options(adapter);
2696
2697         /* initialize the wol settings based on the eeprom settings */
2698         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2699         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2700
2701         /* reset the hardware with the new settings */
2702         pch_gbe_reset(adapter);
2703
2704         ret = register_netdev(netdev);
2705         if (ret)
2706                 goto err_free_adapter;
2707         /* tell the stack to leave us alone until pch_gbe_open() is called */
2708         netif_carrier_off(netdev);
2709         netif_stop_queue(netdev);
2710
2711         dev_dbg(&pdev->dev, "PCH Network Connection\n");
2712
2713         device_set_wakeup_enable(&pdev->dev, 1);
2714         return 0;
2715
2716 err_free_adapter:
2717         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2718 err_free_netdev:
2719         free_netdev(netdev);
2720         return ret;
2721 }
2722
2723 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2724         {.vendor = PCI_VENDOR_ID_INTEL,
2725          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2726          .subvendor = PCI_ANY_ID,
2727          .subdevice = PCI_ANY_ID,
2728          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2729          .class_mask = (0xFFFF00)
2730          },
2731         {.vendor = PCI_VENDOR_ID_ROHM,
2732          .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2733          .subvendor = PCI_ANY_ID,
2734          .subdevice = PCI_ANY_ID,
2735          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2736          .class_mask = (0xFFFF00)
2737          },
2738         {.vendor = PCI_VENDOR_ID_ROHM,
2739          .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2740          .subvendor = PCI_ANY_ID,
2741          .subdevice = PCI_ANY_ID,
2742          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2743          .class_mask = (0xFFFF00)
2744          },
2745         /* required last entry */
2746         {0}
2747 };
2748
2749 #ifdef CONFIG_PM
2750 static const struct dev_pm_ops pch_gbe_pm_ops = {
2751         .suspend = pch_gbe_suspend,
2752         .resume = pch_gbe_resume,
2753         .freeze = pch_gbe_suspend,
2754         .thaw = pch_gbe_resume,
2755         .poweroff = pch_gbe_suspend,
2756         .restore = pch_gbe_resume,
2757 };
2758 #endif
2759
2760 static const struct pci_error_handlers pch_gbe_err_handler = {
2761         .error_detected = pch_gbe_io_error_detected,
2762         .slot_reset = pch_gbe_io_slot_reset,
2763         .resume = pch_gbe_io_resume
2764 };
2765
2766 static struct pci_driver pch_gbe_driver = {
2767         .name = KBUILD_MODNAME,
2768         .id_table = pch_gbe_pcidev_id,
2769         .probe = pch_gbe_probe,
2770         .remove = pch_gbe_remove,
2771 #ifdef CONFIG_PM
2772         .driver.pm = &pch_gbe_pm_ops,
2773 #endif
2774         .shutdown = pch_gbe_shutdown,
2775         .err_handler = &pch_gbe_err_handler
2776 };
2777
2778
2779 static int __init pch_gbe_init_module(void)
2780 {
2781         int ret;
2782
2783         pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2784         ret = pci_register_driver(&pch_gbe_driver);
2785         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2786                 if (copybreak == 0) {
2787                         pr_info("copybreak disabled\n");
2788                 } else {
2789                         pr_info("copybreak enabled for packets <= %u bytes\n",
2790                                 copybreak);
2791                 }
2792         }
2793         return ret;
2794 }
2795
2796 static void __exit pch_gbe_exit_module(void)
2797 {
2798         pci_unregister_driver(&pch_gbe_driver);
2799 }
2800
2801 module_init(pch_gbe_init_module);
2802 module_exit(pch_gbe_exit_module);
2803
2804 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2805 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2806 MODULE_LICENSE("GPL");
2807 MODULE_VERSION(DRV_VERSION);
2808 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2809
2810 module_param(copybreak, uint, 0644);
2811 MODULE_PARM_DESC(copybreak,
2812         "Maximum size of packet that is copied to a new buffer on receive");
2813
2814 /* pch_gbe_main.c */