CHROMIUM: gpio: samsung: add support for interrupts on Exynos5 GPIOs

CHROMIUM: gpio: samsung: add support for interrupts on Exynos5 GPIOs

Add support for interrupts on all bank A and B GPIOs on Exynos 5,
in addition of the current XEINT pins.

Re-use the current Exynos4 / s5p code to minizime this CL overhead as we
probably won't use more that a couple of those interrupts but it's not
optimal in term of performance and it requires to do an explicit
5p_register_gpio_interrupt in the platform code for each GPIO used as an
interrupt.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:17228 chrome-os-partner:12625
TEST=on Spring, boot and see the counter of the HPD interrupt from the
eDP bridge incrementing.

Change-Id: I60bbe8e96d4028393f82e5717fdfa9ca19eb0773
Reviewed-on: https://gerrit.chromium.org/gerrit/43533
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>