CHROMIUM: gpio: samsung: add support for interrupts on Exynos5 GPIOs

Add support for interrupts on all bank A and B GPIOs on Exynos 5,
in addition of the current XEINT pins.

Re-use the current Exynos4 / s5p code to minizime this CL overhead as we
probably won't use more that a couple of those interrupts but it's not
optimal in term of performance and it requires to do an explicit
5p_register_gpio_interrupt in the platform code for each GPIO used as an
interrupt.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:17228 chrome-os-partner:12625
TEST=on Spring, boot and see the counter of the HPD interrupt from the
eDP bridge incrementing.

Change-Id: I60bbe8e96d4028393f82e5717fdfa9ca19eb0773
Reviewed-on: https://gerrit.chromium.org/gerrit/43533
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 7ea1034..1a79ccd 100644 (file)
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -426,6 +426,7 @@ config MACH_EXYNOS5_DT
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_PWM
        select EXYNOS4_SETUP_TVOUT
+       select S5P_GPIO_INT
        help
          Machine support for Samsung Exynos4 machine with device tree enabled.
          Select this if a fdt blob is available for the EXYNOS4 SoC based board.

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index de2566b..a1d4eab 100644 (file)
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3057,6 +3057,13 @@ static __init int samsung_gpiolib_init(void)
                }
                samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
                                               nr_chips, gpio_base4);
+#ifdef CONFIG_S5P_GPIO_INT
+               s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_XA, 0,
+                                         EXYNOS5_IRQ_GPIO1_NR_GROUPS);
+               s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_XB,
+                                         EXYNOS5_IRQ_GPIO1_NR_GROUPS,
+                                         EXYNOS5_IRQ_GPIO2_NR_GROUPS);
+#endif
 #endif /* CONFIG_SOC_EXYNOS5250 */
        } else {
                WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");