1 Device tree bindings for OMAP general purpose memory controllers (GPMC)
3 The actual devices are instantiated from the child nodes of a GPMC node.
7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
16 (see the example below)
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
21 - gpmc,num-cs: The maximum number of chip-select lines that controller
23 - gpmc,num-waitpins: The maximum number of wait pins that controller can
25 - ranges: Must be set up to reflect the memory layout with four
26 integer values for each chip-select line in use:
28 <cs-number> 0 <physical address of mapping> <size>
30 Currently, calculated values derived from the contents
31 of the per-CS register GPMC_CONFIG7 (as set up by the
32 bootloader) are used for the physical address decoding.
33 As this will change in the future, filling correct
34 values here is a requirement.
35 - interrupt-controller: The GPMC driver implements and interrupt controller for
36 the NAND events "fifoevent" and "termcount".
37 The interrupt number mapping is as follows
40 - interrupt-cells: Must be set to 2
41 - gpio-controller: The GPMC driver implements a GPIO controller for the
42 GPMC WAIT pins that can be used as general purpose inputs.
43 0 maps to GPMC_WAIT0 pin.
44 - gpio-cells: Must be set to 2
46 Timing properties for child nodes. All are optional and default to 0.
48 - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
50 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
51 - gpmc,cs-on-ns: Assertion time
52 - gpmc,cs-rd-off-ns: Read deassertion time
53 - gpmc,cs-wr-off-ns: Write deassertion time
55 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
56 - gpmc,adv-on-ns: Assertion time
57 - gpmc,adv-rd-off-ns: Read deassertion time
58 - gpmc,adv-wr-off-ns: Write deassertion time
59 - gpmc,adv-aad-mux-on-ns: Assertion time for AAD
60 - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
61 - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD
63 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
64 - gpmc,we-on-ns Assertion time
65 - gpmc,we-off-ns: Deassertion time
67 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
68 - gpmc,oe-on-ns: Assertion time
69 - gpmc,oe-off-ns: Deassertion time
70 - gpmc,oe-aad-mux-on-ns: Assertion time for AAD
71 - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD
73 Access time and cycle time timings (in nanoseconds) corresponding to
75 - gpmc,page-burst-access-ns: Multiple access word delay
76 - gpmc,access-ns: Start-cycle to first data valid delay
77 - gpmc,rd-cycle-ns: Total read cycle time
78 - gpmc,wr-cycle-ns: Total write cycle time
79 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
80 - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
81 - gpmc,clk-activation-ns: GPMC clock activation time
82 - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
85 Boolean timing parameters. If property is present parameter enabled and
87 - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
88 - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
89 - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
90 accesses to a different CS
91 - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
92 accesses to the same CS
93 - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
94 - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
95 - gpmc,time-para-granularity: Multiply all access times by 2
97 The following are only applicable to OMAP3+ and AM335x:
98 - gpmc,wr-access-ns: In synchronous write mode, for single or
99 burst accesses, defines the number of
100 GPMC_FCLK cycles from start access time
101 to the GPMC_CLK rising edge used by the
102 memory device for the first data capture.
103 - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
104 the time when the first data is driven on
105 the address-data bus.
107 GPMC chip-select settings properties for child nodes. All are optional.
109 - gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
110 - gpmc,burst-wrap Enables wrap bursting
111 - gpmc,burst-read Enables read page/burst mode
112 - gpmc,burst-write Enables write page/burst mode
113 - gpmc,device-width Total width of device(s) connected to a GPMC
114 chip-select in bytes. The GPMC supports 8-bit
115 and 16-bit devices and so this property must be
117 - gpmc,mux-add-data Address and data multiplexing configuration.
118 Valid values are 1 for address-address-data
119 multiplexing mode and 2 for address-data
121 - gpmc,sync-read Enables synchronous read. Defaults to asynchronous
123 - gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
125 - gpmc,wait-pin Wait-pin used by client. Must be less than
127 - gpmc,wait-on-read Enables wait monitoring on reads.
128 - gpmc,wait-on-write Enables wait monitoring on writes.
130 Example for an AM33xx board:
132 gpmc: gpmc@50000000 {
133 compatible = "ti,am3352-gpmc";
135 reg = <0x50000000 0x2000>;
139 gpmc,num-waitpins = <2>;
140 #address-cells = <2>;
142 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
143 interrupt-controller;
144 #interrupt-cells = <2>;
148 /* child nodes go here */