1 Device tree bindings for GPMC connected NANDs
3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
4 the GPMC controller with a name of "nand".
6 All timing relevant properties as well as generic gpmc child properties are
7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/bus/ti-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand.txt
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupt-parent: must point to gpmc node
20 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
24 - nand-bus-width: Set this numeric value to 16 if the hardware
25 is wired that way. If not specified, a bus
26 width of 8 is assumed.
28 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
29 "sw" 1-bit Hamming ecc code via software
30 "hw" <deprecated> use "ham1" instead
31 "hw-romcode" <deprecated> use "ham1" instead
32 "ham1" 1-bit Hamming ecc code
33 "bch4" 4-bit BCH ecc code
34 "bch8" 8-bit BCH ecc code
35 "bch16" 16-bit BCH ECC code
36 Refer below "How to select correct ECC scheme for your device ?"
38 - ti,nand-xfer-type: A string setting the data transfer type. One of:
40 "prefetch-polled" Prefetch polled mode (default)
41 "polled" Polled mode, without prefetch
42 "prefetch-dma" Prefetch enabled sDMA mode
43 "prefetch-irq" Prefetch enabled irq mode
45 - elm_id: <deprecated> use "ti,elm-id" instead
46 - ti,elm-id: Specifies phandle of the ELM devicetree node.
47 ELM is an on-chip hardware engine on TI SoC which is used for
48 locating ECC errors for BCHx algorithms. SoC devices which have
49 ELM hardware engines should specify this device node in .dtsi
50 Using ELM for ECC error correction frees some CPU cycles.
52 For inline partition table parsing (optional):
54 - #address-cells: should be set to 1
55 - #size-cells: should be set to 1
57 Example for an AM33xx board:
60 compatible = "ti,am3352-gpmc";
62 reg = <0x50000000 0x36c>;
65 gpmc,num-waitpins = <2>;
68 ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
71 #interrupt-cells = <2>;
74 compatible = "ti,omap2-nand";
75 reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
76 interrupt-parent = <&gpmc>;
77 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
78 nand-bus-width = <16>;
79 ti,nand-ecc-opt = "bch8";
80 ti,nand-xfer-type = "polled";
82 gpmc,sync-clk-ps = <0>;
84 gpmc,cs-rd-off-ns = <44>;
85 gpmc,cs-wr-off-ns = <44>;
87 gpmc,adv-rd-off-ns = <34>;
88 gpmc,adv-wr-off-ns = <44>;
89 gpmc,we-off-ns = <40>;
90 gpmc,oe-off-ns = <54>;
91 gpmc,access-ns = <64>;
92 gpmc,rd-cycle-ns = <82>;
93 gpmc,wr-cycle-ns = <82>;
94 gpmc,wr-access-ns = <40>;
95 gpmc,wr-data-mux-bus-ns = <0>;
100 /* partitions go here */
104 How to select correct ECC scheme for your device ?
105 --------------------------------------------------
106 Higher ECC scheme usually means better protection against bit-flips and
107 increased system lifetime. However, selection of ECC scheme is dependent
108 on various other factors also like;
110 (1) support of built in hardware engines.
111 Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
112 support ecc-schemes with hardware error-correction (BCHx_HW). However
113 such SoC can use ecc-schemes with software library for error-correction
114 (BCHx_HW_DETECTION_SW). The error correction capability with software
115 library remains equivalent to their hardware counter-part, but there is
116 slight CPU penalty when too many bit-flips are detected during reads.
118 (2) Device parameters like OOBSIZE.
119 Other factor which governs the selection of ecc-scheme is oob-size.
120 Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
121 so the device should have enough free bytes available its OOB/Spare
122 area to accommodate ECC for entire page. In general following expression
123 helps in determining if given device can accommodate ECC syndrome:
124 "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE"
126 OOBSIZE number of bytes in OOB/spare area
127 PAGESIZE number of bytes in main-area of device page
128 ECC_BYTES number of ECC bytes generated to protect
129 512 bytes of data, which is:
130 '3' for HAM1_xx ecc schemes
131 '7' for BCH4_xx ecc schemes
132 '14' for BCH8_xx ecc schemes
133 '26' for BCH16_xx ecc schemes
135 Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
136 trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
137 Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
138 which is greater than capacity of NAND device (OOBSIZE=64)
139 Hence, BCH16 cannot be supported on given device. But it can
140 probably use lower ecc-schemes like BCH8.
142 Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
143 trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
144 Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
145 which can be accommodated in the OOB/Spare area of this device
146 (OOBSIZE=128). So this device can use BCH16 ecc-scheme.