arch/arm/boot/dts/am335x-chilisom.dtsi

   1 /*
   2  * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
   3  * Author: Rostislav Lisovy <lisovy@jablotron.cz>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include "am33xx.dtsi"
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         model = "Grinn AM335x ChiliSOM";
  14         compatible = "grinn,am335x-chilisom", "ti,am33xx";
  15
  16         cpus {
  17                 cpu@0 {
  18                         cpu0-supply = <&dcdc2_reg>;
  19                 };
  20         };
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x80000000 0x20000000>; /* 512 MB */
  25         };
  26 };
  27
  28 &am33xx_pinmux {
  29         pinctrl-names = "default";
  30
  31         i2c0_pins: pinmux_i2c0_pins {
  32                 pinctrl-single,pins = <
  33                         AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
  34                         AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
  35                 >;
  36         };
  37
  38         uart0_pins: pinmux_uart0_pins {
  39                 pinctrl-single,pins = <
  40                         AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
  41                         AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
  42                 >;
  43         };
  44
  45         cpsw_default: cpsw_default {
  46                 pinctrl-single,pins = <
  47                         /* Slave 1 */
  48                         AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
  49                         AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxerr.rmii1_rxerr */
  50                         AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txen.rmii1_txen */
  51                         AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
  52                         AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
  53                         AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd1.rmii1_rxd1 */
  54                         AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd0.rmii1_rxd0 */
  55                         AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* rmii1_ref_clk.rmii_ref_clk */
  56                 >;
  57         };
  58
  59         cpsw_sleep: cpsw_sleep {
  60                 pinctrl-single,pins = <
  61                         /* Slave 1 reset value */
  62                         AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  63                         AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
  64                         AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
  65                         AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
  66                         AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
  67                         AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
  68                         AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  69                         AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
  70                         AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
  71                 >;
  72         };
  73
  74         davinci_mdio_default: davinci_mdio_default {
  75                 pinctrl-single,pins = <
  76                         /* mdio_data.mdio_data */
  77                         AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
  78                         /* mdio_clk.mdio_clk */
  79                         AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
  80                 >;
  81         };
  82
  83         davinci_mdio_sleep: davinci_mdio_sleep {
  84                 pinctrl-single,pins = <
  85                         /* MDIO reset value */
  86                         AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
  87                         AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  88                 >;
  89         };
  90
  91         nandflash_pins: nandflash_pins {
  92                 pinctrl-single,pins = <
  93                         AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
  94                         AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
  95                         AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
  96                         AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
  97                         AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
  98                         AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
  99                         AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 100                         AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 101
 102                         AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
 103                         AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_csn0.gpmc_csn0 */
 104                         AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_advn_ale.gpmc_advn_ale */
 105                         AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_oen_ren.gpmc_oen_ren */
 106                         AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_wen.gpmc_wen */
 107                         AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0)      /* gpmc_be0n_cle.gpmc_be0n_cle */
 108                 >;
 109         };
 110 };
 111
 112 &uart0 {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&uart0_pins>;
 115
 116         status = "okay";
 117 };
 118
 119 &i2c0 {
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&i2c0_pins>;
 122
 123         status = "okay";
 124         clock-frequency = <400000>;
 125
 126         tps: tps@24 {
 127                 reg = <0x24>;
 128         };
 129
 130 };
 131
 132 &tps {
 133         compatible = "ti,tps65217";
 134
 135         regulators {
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138
 139                 dcdc1_reg: regulator@0 {
 140                         reg = <0>;
 141                         regulator-name = "vdds_dpr";
 142                         regulator-always-on;
 143                 };
 144
 145                 dcdc2_reg: regulator@1 {
 146                         reg = <1>;
 147                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 148                         regulator-name = "vdd_mpu";
 149                         regulator-min-microvolt = <925000>;
 150                         regulator-max-microvolt = <1325000>;
 151                         regulator-boot-on;
 152                         regulator-always-on;
 153                 };
 154
 155                 dcdc3_reg: regulator@2 {
 156                         reg = <2>;
 157                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 158                         regulator-name = "vdd_core";
 159                         regulator-min-microvolt = <925000>;
 160                         regulator-max-microvolt = <1150000>;
 161                         regulator-boot-on;
 162                         regulator-always-on;
 163                 };
 164
 165                 ldo1_reg: regulator@3 {
 166                         reg = <3>;
 167                         regulator-name = "vio,vrtc,vdds";
 168                         regulator-boot-on;
 169                         regulator-always-on;
 170                 };
 171
 172                 ldo2_reg: regulator@4 {
 173                         reg = <4>;
 174                         regulator-name = "vdd_3v3aux";
 175                         regulator-boot-on;
 176                         regulator-always-on;
 177                 };
 178
 179                 ldo3_reg: regulator@5 {
 180                         reg = <5>;
 181                         regulator-name = "vdd_1v8";
 182                         regulator-boot-on;
 183                         regulator-always-on;
 184                 };
 185
 186                 ldo4_reg: regulator@6 {
 187                         reg = <6>;
 188                         regulator-name = "vdd_3v3d";
 189                         regulator-boot-on;
 190                         regulator-always-on;
 191                 };
 192         };
 193 };
 194
 195 /* Ethernet MAC */
 196 &mac {
 197         slaves = <1>;
 198         pinctrl-names = "default", "sleep";
 199         pinctrl-0 = <&cpsw_default>;
 200         pinctrl-1 = <&cpsw_sleep>;
 201         status = "okay";
 202 };
 203
 204 &davinci_mdio {
 205         pinctrl-names = "default", "sleep";
 206         pinctrl-0 = <&davinci_mdio_default>;
 207         pinctrl-1 = <&davinci_mdio_sleep>;
 208         status = "okay";
 209 };
 210
 211 /* NAND Flash */
 212 &elm {
 213         status = "okay";
 214 };
 215
 216 &gpmc {
 217         status = "okay";
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&nandflash_pins>;
 220         ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
 221         nand@0,0 {
 222                 compatible = "ti,omap2-nand";
 223                 reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
 224                 interrupt-parent = <&gpmc>;
 225                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 226                              <1 IRQ_TYPE_NONE>; /* termcount */
 227                 ti,nand-ecc-opt = "bch8";
 228                 ti,elm-id = <&elm>;
 229                 nand-bus-width = <8>;
 230                 gpmc,device-width = <1>;
 231                 gpmc,sync-clk-ps = <0>;
 232                 gpmc,cs-on-ns = <0>;
 233                 gpmc,cs-rd-off-ns = <44>;
 234                 gpmc,cs-wr-off-ns = <44>;
 235                 gpmc,adv-on-ns = <6>;
 236                 gpmc,adv-rd-off-ns = <34>;
 237                 gpmc,adv-wr-off-ns = <44>;
 238                 gpmc,we-on-ns = <0>;
 239                 gpmc,we-off-ns = <40>;
 240                 gpmc,oe-on-ns = <0>;
 241                 gpmc,oe-off-ns = <54>;
 242                 gpmc,access-ns = <64>;
 243                 gpmc,rd-cycle-ns = <82>;
 244                 gpmc,wr-cycle-ns = <82>;
 245                 gpmc,wait-on-read = "true";
 246                 gpmc,wait-on-write = "true";
 247                 gpmc,bus-turnaround-ns = <0>;
 248                 gpmc,cycle2cycle-delay-ns = <0>;
 249                 gpmc,clk-activation-ns = <0>;
 250                 gpmc,wait-monitoring-ns = <0>;
 251                 gpmc,wr-access-ns = <40>;
 252                 gpmc,wr-data-mux-bus-ns = <0>;
 253         };
 254 };