2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/pwm/pwm.h>
16 #include <dt-bindings/gpio/gpio.h>
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
26 evm_v3_3d: fixedregulator-v3_3d {
27 compatible = "regulator-fixed";
28 regulator-name = "evm_v3_3d";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
34 vtt_fixed: fixedregulator-vtt {
35 compatible = "regulator-fixed";
36 regulator-name = "vtt_fixed";
37 regulator-min-microvolt = <1500000>;
38 regulator-max-microvolt = <1500000>;
42 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
45 vmmcwl_fixed: fixedregulator-mmcwl {
46 compatible = "regulator-fixed";
47 regulator-name = "vmmcwl_fixed";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
55 compatible = "pwm-backlight";
56 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
57 brightness-levels = <0 51 53 56 62 75 101 152 255>;
58 default-brightness-level = <8>;
61 matrix_keypad: matrix_keypad@0 {
62 compatible = "gpio-matrix-keypad";
63 debounce-delay-ms = <5>;
64 col-scan-delay-us = <2>;
66 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
67 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
68 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
70 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
71 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
73 linux,keymap = <0x00000201 /* P1 */
76 0x0101006a /* RIGHT */
78 0x0201006c>; /* DOWN */
82 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
86 clock-frequency = <33000000>;
98 pixelclk-active = <1>;
103 remote-endpoint = <&dpi_out>;
108 /* fixed 12MHz oscillator */
111 compatible = "fixed-clock";
112 clock-frequency = <12000000>;
116 compatible = "simple-audio-card";
117 simple-audio-card,name = "AM437x-GP-EVM";
118 simple-audio-card,widgets =
119 "Headphone", "Headphone Jack",
121 simple-audio-card,routing =
122 "Headphone Jack", "HPLOUT",
123 "Headphone Jack", "HPROUT",
126 simple-audio-card,format = "dsp_b";
127 simple-audio-card,bitclock-master = <&sound0_master>;
128 simple-audio-card,frame-master = <&sound0_master>;
129 simple-audio-card,bitclock-inversion;
131 simple-audio-card,cpu {
132 sound-dai = <&mcasp1>;
133 system-clock-frequency = <12000000>;
136 sound0_master: simple-audio-card,codec {
137 sound-dai = <&tlv320aic3106>;
138 system-clock-frequency = <12000000>;
144 pinctrl-names = "default", "sleep";
145 pinctrl-0 = <&wlan_pins_default>;
146 pinctrl-1 = <&wlan_pins_sleep>;
148 i2c0_pins: i2c0_pins {
149 pinctrl-single,pins = <
150 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
151 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
155 i2c1_pins: i2c1_pins {
156 pinctrl-single,pins = <
157 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
158 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
162 mmc1_pins: pinmux_mmc1_pins {
163 pinctrl-single,pins = <
164 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
168 ecap0_pins: backlight_pins {
169 pinctrl-single,pins = <
170 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
174 pixcir_ts_pins: pixcir_ts_pins {
175 pinctrl-single,pins = <
176 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
180 cpsw_default: cpsw_default {
181 pinctrl-single,pins = <
183 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
184 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
185 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
186 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
187 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
188 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
189 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
190 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
191 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
192 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
193 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
194 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
198 cpsw_sleep: cpsw_sleep {
199 pinctrl-single,pins = <
200 /* Slave 1 reset value */
201 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
202 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
204 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
205 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
209 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
210 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
211 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
212 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
216 davinci_mdio_default: davinci_mdio_default {
217 pinctrl-single,pins = <
219 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
220 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
224 davinci_mdio_sleep: davinci_mdio_sleep {
225 pinctrl-single,pins = <
226 /* MDIO reset value */
227 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
232 nand_flash_x8: nand_flash_x8 {
233 pinctrl-single,pins = <
234 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
235 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
236 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
237 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
238 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
239 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
240 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
241 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
242 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
243 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
244 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
245 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
246 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
247 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
248 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
253 pinctrl-single,pins = <
254 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
255 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
256 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
257 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
258 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
259 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
260 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
261 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
262 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
263 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
264 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
265 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
266 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
267 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
268 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
269 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
270 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
271 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
272 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
273 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
274 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
275 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
276 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
277 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
278 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
279 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
280 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
281 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
286 display_mux_pins: display_mux_pins {
287 pinctrl-single,pins = <
288 /* GPIO 5_8 to select LCD / HDMI */
289 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
293 dcan0_default: dcan0_default_pins {
294 pinctrl-single,pins = <
295 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
296 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
300 dcan1_default: dcan1_default_pins {
301 pinctrl-single,pins = <
302 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
303 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
307 vpfe0_pins_default: vpfe0_pins_default {
308 pinctrl-single,pins = <
309 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
310 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
311 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
312 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
313 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
314 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
315 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
316 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
317 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
318 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
319 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
320 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
321 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
325 vpfe0_pins_sleep: vpfe0_pins_sleep {
326 pinctrl-single,pins = <
327 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
328 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
329 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
330 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
331 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
332 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
333 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
334 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
335 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
336 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
337 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
338 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
339 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
343 vpfe1_pins_default: vpfe1_pins_default {
344 pinctrl-single,pins = <
345 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
346 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
347 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
348 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
349 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
350 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
351 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
352 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
353 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
354 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
355 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
356 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
357 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
361 vpfe1_pins_sleep: vpfe1_pins_sleep {
362 pinctrl-single,pins = <
363 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
364 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
365 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
366 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
367 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
368 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
369 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
370 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
371 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
372 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
373 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
374 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
375 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
379 mmc3_pins_default: pinmux_mmc3_pins_default {
380 pinctrl-single,pins = <
381 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
382 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
383 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
384 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
385 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
386 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
390 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
391 pinctrl-single,pins = <
392 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
393 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
394 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
395 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
396 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
397 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
401 wlan_pins_default: pinmux_wlan_pins_default {
402 pinctrl-single,pins = <
403 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
404 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
405 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
409 wlan_pins_sleep: pinmux_wlan_pins_sleep {
410 pinctrl-single,pins = <
411 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
412 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
413 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
417 uart3_pins: uart3_pins {
418 pinctrl-single,pins = <
419 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
420 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
421 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
422 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
426 mcasp1_pins: mcasp1_pins {
427 pinctrl-single,pins = <
428 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
429 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
430 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
431 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
435 mcasp1_sleep_pins: mcasp1_sleep_pins {
436 pinctrl-single,pins = <
437 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
438 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
439 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
440 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
444 gpio0_pins: gpio0_pins {
445 pinctrl-single,pins = <
446 0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c0_pins>;
455 clock-frequency = <100000>;
457 tps65218: tps65218@24 {
459 compatible = "ti,tps65218";
460 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
461 interrupt-controller;
462 #interrupt-cells = <2>;
464 dcdc1: regulator-dcdc1 {
465 compatible = "ti,tps65218-dcdc1";
466 regulator-name = "vdd_core";
467 regulator-min-microvolt = <912000>;
468 regulator-max-microvolt = <1144000>;
473 dcdc2: regulator-dcdc2 {
474 compatible = "ti,tps65218-dcdc2";
475 regulator-name = "vdd_mpu";
476 regulator-min-microvolt = <912000>;
477 regulator-max-microvolt = <1378000>;
482 dcdc3: regulator-dcdc3 {
483 compatible = "ti,tps65218-dcdc3";
484 regulator-name = "vdcdc3";
485 regulator-min-microvolt = <1500000>;
486 regulator-max-microvolt = <1500000>;
490 dcdc5: regulator-dcdc5 {
491 compatible = "ti,tps65218-dcdc5";
492 regulator-name = "v1_0bat";
493 regulator-min-microvolt = <1000000>;
494 regulator-max-microvolt = <1000000>;
497 dcdc6: regulator-dcdc6 {
498 compatible = "ti,tps65218-dcdc6";
499 regulator-name = "v1_8bat";
500 regulator-min-microvolt = <1800000>;
501 regulator-max-microvolt = <1800000>;
504 ldo1: regulator-ldo1 {
505 compatible = "ti,tps65218-ldo1";
506 regulator-min-microvolt = <1800000>;
507 regulator-max-microvolt = <1800000>;
514 compatible = "ovti,ov2659";
517 clocks = <&refclk 0>;
518 clock-names = "xvclk";
522 remote-endpoint = <&vpfe1_ep>;
523 link-frequencies = /bits/ 64 <70000000>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c1_pins>;
534 compatible = "pixcir,pixcir_tangoc";
535 pinctrl-names = "default";
536 pinctrl-0 = <&pixcir_ts_pins>;
538 interrupt-parent = <&gpio3>;
541 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
543 touchscreen-size-x = <1024>;
544 touchscreen-size-y = <600>;
548 compatible = "ovti,ov2659";
551 clocks = <&refclk 0>;
552 clock-names = "xvclk";
556 remote-endpoint = <&vpfe0_ep>;
557 link-frequencies = /bits/ 64 <70000000>;
562 tlv320aic3106: tlv320aic3106@1b {
563 #sound-dai-cells = <0>;
564 compatible = "ti,tlv320aic3106";
569 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
570 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
571 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
572 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
584 ti,adc-channels = <0 1 2 3 4 5 6 7>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&ecap0_pins>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&gpio0_pins>;
601 gpios = <23 GPIO_ACTIVE_HIGH>;
602 /* SelEMMCorNAND selects between eMMC and NAND:
605 * When changing this line make sure the newly
606 * selected device node is enabled and the previously
607 * selected device node is disabled.
610 line-name = "SelEMMCorNAND";
627 pinctrl-names = "default";
628 pinctrl-0 = <&display_mux_pins>;
634 * SelLCDorHDMI selects between display and audio paths:
635 * Low: HDMI display with audio via HDMI
636 * High: LCD display with analog audio via aic3111 codec
639 gpios = <8 GPIO_ACTIVE_HIGH>;
641 line-name = "SelLCDorHDMI";
647 vmmc-supply = <&evm_v3_3d>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&mmc1_pins>;
651 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
656 /* these are on the crossbar and are outlined in the
657 xbar-event-map element */
660 dma-names = "tx", "rx";
661 vmmc-supply = <&vmmcwl_fixed>;
663 pinctrl-names = "default", "sleep";
664 pinctrl-0 = <&mmc3_pins_default>;
665 pinctrl-1 = <&mmc3_pins_sleep>;
667 keep-power-in-suspend;
670 #address-cells = <1>;
673 compatible = "ti,wl1835";
675 interrupt-parent = <&gpio1>;
676 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
681 ti,edma-xbar-event-map = /bits/ 16 <1 30
687 pinctrl-names = "default";
688 pinctrl-0 = <&uart3_pins>;
696 dr_mode = "peripheral";
711 pinctrl-names = "default", "sleep";
712 pinctrl-0 = <&cpsw_default>;
713 pinctrl-1 = <&cpsw_sleep>;
718 pinctrl-names = "default", "sleep";
719 pinctrl-0 = <&davinci_mdio_default>;
720 pinctrl-1 = <&davinci_mdio_sleep>;
725 phy_id = <&davinci_mdio>, <0>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&nand_flash_x8>;
737 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
739 reg = <0 0 4>; /* device IO registers */
740 ti,nand-ecc-opt = "bch16";
742 nand-bus-width = <8>;
743 gpmc,device-width = <1>;
744 gpmc,sync-clk-ps = <0>;
746 gpmc,cs-rd-off-ns = <40>;
747 gpmc,cs-wr-off-ns = <40>;
748 gpmc,adv-on-ns = <0>;
749 gpmc,adv-rd-off-ns = <25>;
750 gpmc,adv-wr-off-ns = <25>;
752 gpmc,we-off-ns = <20>;
754 gpmc,oe-off-ns = <30>;
755 gpmc,access-ns = <30>;
756 gpmc,rd-cycle-ns = <40>;
757 gpmc,wr-cycle-ns = <40>;
759 gpmc,bus-turnaround-ns = <0>;
760 gpmc,cycle2cycle-delay-ns = <0>;
761 gpmc,clk-activation-ns = <0>;
762 gpmc,wait-monitoring-ns = <0>;
763 gpmc,wr-access-ns = <40>;
764 gpmc,wr-data-mux-bus-ns = <0>;
765 /* MTD partition table */
766 /* All SPL-* partitions are sized to minimal length
767 * which can be independently programmable. For
768 * NAND flash this is equal to size of erase-block */
769 #address-cells = <1>;
773 reg = <0x00000000 0x00040000>;
776 label = "NAND.SPL.backup1";
777 reg = <0x00040000 0x00040000>;
780 label = "NAND.SPL.backup2";
781 reg = <0x00080000 0x00040000>;
784 label = "NAND.SPL.backup3";
785 reg = <0x000c0000 0x00040000>;
788 label = "NAND.u-boot-spl-os";
789 reg = <0x00100000 0x00080000>;
792 label = "NAND.u-boot";
793 reg = <0x00180000 0x00100000>;
796 label = "NAND.u-boot-env";
797 reg = <0x00280000 0x00040000>;
800 label = "NAND.u-boot-env.backup1";
801 reg = <0x002c0000 0x00040000>;
804 label = "NAND.kernel";
805 reg = <0x00300000 0x00700000>;
808 label = "NAND.file-system";
809 reg = <0x00a00000 0x1f600000>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&dss_pins>;
821 dpi_out: endpoint@0 {
822 remote-endpoint = <&lcd_in>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&dcan0_default>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&dcan1_default>;
842 pinctrl-names = "default", "sleep";
843 pinctrl-0 = <&vpfe0_pins_default>;
844 pinctrl-1 = <&vpfe0_pins_sleep>;
848 remote-endpoint = <&ov2659_1>;
849 ti,am437x-vpfe-interface = <0>;
859 pinctrl-names = "default", "sleep";
860 pinctrl-0 = <&vpfe1_pins_default>;
861 pinctrl-1 = <&vpfe1_pins_sleep>;
865 remote-endpoint = <&ov2659_0>;
866 ti,am437x-vpfe-interface = <0>;
875 #sound-dai-cells = <0>;
876 pinctrl-names = "default", "sleep";
877 pinctrl-0 = <&mcasp1_pins>;
878 pinctrl-1 = <&mcasp1_sleep_pins>;
882 op-mode = <0>; /* MCASP_IIS_MODE */
885 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */