arch/arm/boot/dts/am437x-gp-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM437x GP EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17
  18 / {
  19         model = "TI AM437x GP EVM";
  20         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24         };
  25
  26         evm_v3_3d: fixedregulator-v3_3d {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "evm_v3_3d";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 enable-active-high;
  32         };
  33
  34         vtt_fixed: fixedregulator-vtt {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "vtt_fixed";
  37                 regulator-min-microvolt = <1500000>;
  38                 regulator-max-microvolt = <1500000>;
  39                 regulator-always-on;
  40                 regulator-boot-on;
  41                 enable-active-high;
  42                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  43         };
  44
  45         vmmcwl_fixed: fixedregulator-mmcwl {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "vmmcwl_fixed";
  48                 regulator-min-microvolt = <1800000>;
  49                 regulator-max-microvolt = <1800000>;
  50                 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         backlight {
  55                 compatible = "pwm-backlight";
  56                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  57                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  58                 default-brightness-level = <8>;
  59         };
  60
  61         matrix_keypad: matrix_keypad@0 {
  62                 compatible = "gpio-matrix-keypad";
  63                 debounce-delay-ms = <5>;
  64                 col-scan-delay-us = <2>;
  65
  66                 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  67                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  68                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  69
  70                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  71                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  72
  73                 linux,keymap = <0x00000201      /* P1 */
  74                                 0x00010202      /* P2 */
  75                                 0x01000067      /* UP */
  76                                 0x0101006a      /* RIGHT */
  77                                 0x02000069      /* LEFT */
  78                                 0x0201006c>;      /* DOWN */
  79                 };
  80
  81         lcd0: display {
  82                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  83                 label = "lcd";
  84
  85                 panel-timing {
  86                         clock-frequency = <33000000>;
  87                         hactive = <800>;
  88                         vactive = <480>;
  89                         hfront-porch = <210>;
  90                         hback-porch = <16>;
  91                         hsync-len = <30>;
  92                         vback-porch = <10>;
  93                         vfront-porch = <22>;
  94                         vsync-len = <13>;
  95                         hsync-active = <0>;
  96                         vsync-active = <0>;
  97                         de-active = <1>;
  98                         pixelclk-active = <1>;
  99                 };
 100
 101                 port {
 102                         lcd_in: endpoint {
 103                                 remote-endpoint = <&dpi_out>;
 104                         };
 105                 };
 106         };
 107
 108         /* fixed 12MHz oscillator */
 109         refclk: oscillator {
 110                 #clock-cells = <0>;
 111                 compatible = "fixed-clock";
 112                 clock-frequency = <12000000>;
 113         };
 114
 115         sound0: sound@0 {
 116                 compatible = "simple-audio-card";
 117                 simple-audio-card,name = "AM437x-GP-EVM";
 118                 simple-audio-card,widgets =
 119                         "Headphone", "Headphone Jack",
 120                         "Line", "Line In";
 121                 simple-audio-card,routing =
 122                         "Headphone Jack",       "HPLOUT",
 123                         "Headphone Jack",       "HPROUT",
 124                         "LINE1L",               "Line In",
 125                         "LINE1R",               "Line In";
 126                 simple-audio-card,format = "dsp_b";
 127                 simple-audio-card,bitclock-master = <&sound0_master>;
 128                 simple-audio-card,frame-master = <&sound0_master>;
 129                 simple-audio-card,bitclock-inversion;
 130
 131                 simple-audio-card,cpu {
 132                         sound-dai = <&mcasp1>;
 133                         system-clock-frequency = <12000000>;
 134                 };
 135
 136                 sound0_master: simple-audio-card,codec {
 137                         sound-dai = <&tlv320aic3106>;
 138                         system-clock-frequency = <12000000>;
 139                 };
 140         };
 141 };
 142
 143 &am43xx_pinmux {
 144         pinctrl-names = "default", "sleep";
 145         pinctrl-0 = <&wlan_pins_default>;
 146         pinctrl-1 = <&wlan_pins_sleep>;
 147
 148         i2c0_pins: i2c0_pins {
 149                 pinctrl-single,pins = <
 150                         0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 151                         0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 152                 >;
 153         };
 154
 155         i2c1_pins: i2c1_pins {
 156                 pinctrl-single,pins = <
 157                         0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 158                         0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 159                 >;
 160         };
 161
 162         mmc1_pins: pinmux_mmc1_pins {
 163                 pinctrl-single,pins = <
 164                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 165                 >;
 166         };
 167
 168         ecap0_pins: backlight_pins {
 169                 pinctrl-single,pins = <
 170                         0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 171                 >;
 172         };
 173
 174         pixcir_ts_pins: pixcir_ts_pins {
 175                 pinctrl-single,pins = <
 176                         0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 177                 >;
 178         };
 179
 180         cpsw_default: cpsw_default {
 181                 pinctrl-single,pins = <
 182                         /* Slave 1 */
 183                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
 184                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
 185                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
 186                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
 187                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
 188                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
 189                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
 190                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
 191                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
 192                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
 193                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
 194                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
 195                 >;
 196         };
 197
 198         cpsw_sleep: cpsw_sleep {
 199                 pinctrl-single,pins = <
 200                         /* Slave 1 reset value */
 201                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 202                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 203                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 204                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 205                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 206                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 207                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 208                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 209                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 210                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 211                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 212                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 213                 >;
 214         };
 215
 216         davinci_mdio_default: davinci_mdio_default {
 217                 pinctrl-single,pins = <
 218                         /* MDIO */
 219                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 220                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 221                 >;
 222         };
 223
 224         davinci_mdio_sleep: davinci_mdio_sleep {
 225                 pinctrl-single,pins = <
 226                         /* MDIO reset value */
 227                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 228                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 229                 >;
 230         };
 231
 232         nand_flash_x8: nand_flash_x8 {
 233                 pinctrl-single,pins = <
 234                         0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 235                         0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 236                         0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 237                         0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 238                         0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 239                         0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 240                         0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 241                         0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 242                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 243                         0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 244                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 245                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 246                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 247                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 248                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 249                 >;
 250         };
 251
 252         dss_pins: dss_pins {
 253                 pinctrl-single,pins = <
 254                         0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 255                         0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 256                         0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 257                         0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
 258                         0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 259                         0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 260                         0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 261                         0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 262                         0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 263                         0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 264                         0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 265                         0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
 266                         0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 267                         0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 268                         0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 269                         0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 270                         0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 271                         0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 272                         0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 273                         0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 274                         0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 275                         0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 276                         0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 277                         0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 278                         0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 279                         0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 280                         0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 281                         0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 282
 283                 >;
 284         };
 285
 286         display_mux_pins: display_mux_pins {
 287                 pinctrl-single,pins = <
 288                         /* GPIO 5_8 to select LCD / HDMI */
 289                         0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
 290                 >;
 291         };
 292
 293         dcan0_default: dcan0_default_pins {
 294                 pinctrl-single,pins = <
 295                         0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
 296                         0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
 297                 >;
 298         };
 299
 300         dcan1_default: dcan1_default_pins {
 301                 pinctrl-single,pins = <
 302                         0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
 303                         0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
 304                 >;
 305         };
 306
 307         vpfe0_pins_default: vpfe0_pins_default {
 308                 pinctrl-single,pins = <
 309                         0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
 310                         0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
 311                         0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
 312                         0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
 313                         0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
 314                         0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
 315                         0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
 316                         0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
 317                         0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
 318                         0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
 319                         0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
 320                         0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
 321                         0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 322                 >;
 323         };
 324
 325         vpfe0_pins_sleep: vpfe0_pins_sleep {
 326                 pinctrl-single,pins = <
 327                         0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
 328                         0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
 329                         0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
 330                         0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
 331                         0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
 332                         0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
 333                         0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
 334                         0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
 335                         0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
 336                         0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
 337                         0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
 338                         0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
 339                         0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 340                 >;
 341         };
 342
 343         vpfe1_pins_default: vpfe1_pins_default {
 344                 pinctrl-single,pins = <
 345                         0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
 346                         0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
 347                         0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
 348                         0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
 349                         0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
 350                         0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
 351                         0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
 352                         0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
 353                         0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
 354                         0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
 355                         0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
 356                         0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
 357                         0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 358                 >;
 359         };
 360
 361         vpfe1_pins_sleep: vpfe1_pins_sleep {
 362                 pinctrl-single,pins = <
 363                         0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
 364                         0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
 365                         0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
 366                         0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
 367                         0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
 368                         0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
 369                         0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
 370                         0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
 371                         0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
 372                         0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
 373                         0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
 374                         0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
 375                         0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 376                 >;
 377         };
 378
 379         mmc3_pins_default: pinmux_mmc3_pins_default {
 380                 pinctrl-single,pins = <
 381                         0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
 382                         0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
 383                         0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
 384                         0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
 385                         0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
 386                         0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 387                 >;
 388         };
 389
 390         mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 391                 pinctrl-single,pins = <
 392                         0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_clk.mmc2_clk */
 393                         0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_csn3.mmc2_cmd */
 394                         0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a1.mmc2_dat0 */
 395                         0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a2.mmc2_dat1 */
 396                         0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a3.mmc2_dat2 */
 397                         0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_be1n.mmc2_dat3 */
 398                 >;
 399         };
 400
 401         wlan_pins_default: pinmux_wlan_pins_default {
 402                 pinctrl-single,pins = <
 403                         0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
 404                         0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
 405                         0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a0.gpio1_16 BT_EN*/
 406                 >;
 407         };
 408
 409         wlan_pins_sleep: pinmux_wlan_pins_sleep {
 410                 pinctrl-single,pins = <
 411                         0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
 412                         0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
 413                         0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
 414                 >;
 415         };
 416
 417         uart3_pins: uart3_pins {
 418                 pinctrl-single,pins = <
 419                         0x228 (PIN_INPUT | MUX_MODE0)           /* uart3_rxd.uart3_rxd */
 420                         0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
 421                         0x230 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_ctsn.uart3_ctsn */
 422                         0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 423                 >;
 424         };
 425
 426         mcasp1_pins: mcasp1_pins {
 427                 pinctrl-single,pins = <
 428                         0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
 429                         0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4)  /* mii1_crs.mcasp1_aclkx */
 430                         0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4)  /* mii1_rxerr.mcasp1_fsx */
 431                         0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4)  /* rmii1_ref_clk.mcasp1_axr3 */
 432                 >;
 433         };
 434
 435         mcasp1_sleep_pins: mcasp1_sleep_pins {
 436                 pinctrl-single,pins = <
 437                         0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 438                         0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 439                         0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 440                         0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 441                 >;
 442         };
 443
 444         gpio0_pins: gpio0_pins {
 445                 pinctrl-single,pins = <
 446                         0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
 447                 >;
 448         };
 449
 450         emmc_pins_default: emmc_pins_default {
 451                 pinctrl-single,pins = <
 452                         0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
 453                         0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
 454                         0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
 455                         0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
 456                         0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
 457                         0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
 458                         0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
 459                         0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
 460                         0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
 461                         0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
 462                 >;
 463         };
 464
 465         emmc_pins_sleep: emmc_pins_sleep {
 466                 pinctrl-single,pins = <
 467                         0x00 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
 468                         0x04 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
 469                         0x08 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
 470                         0x0c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
 471                         0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
 472                         0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
 473                         0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
 474                         0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
 475                         0x80 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
 476                         0x84 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
 477                 >;
 478         };
 479 };
 480
 481 &i2c0 {
 482         status = "okay";
 483         pinctrl-names = "default";
 484         pinctrl-0 = <&i2c0_pins>;
 485         clock-frequency = <100000>;
 486
 487         tps65218: tps65218@24 {
 488                 reg = <0x24>;
 489                 compatible = "ti,tps65218";
 490                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 491                 interrupt-controller;
 492                 #interrupt-cells = <2>;
 493
 494                 dcdc1: regulator-dcdc1 {
 495                         compatible = "ti,tps65218-dcdc1";
 496                         regulator-name = "vdd_core";
 497                         regulator-min-microvolt = <912000>;
 498                         regulator-max-microvolt = <1144000>;
 499                         regulator-boot-on;
 500                         regulator-always-on;
 501                 };
 502
 503                 dcdc2: regulator-dcdc2 {
 504                         compatible = "ti,tps65218-dcdc2";
 505                         regulator-name = "vdd_mpu";
 506                         regulator-min-microvolt = <912000>;
 507                         regulator-max-microvolt = <1378000>;
 508                         regulator-boot-on;
 509                         regulator-always-on;
 510                 };
 511
 512                 dcdc3: regulator-dcdc3 {
 513                         compatible = "ti,tps65218-dcdc3";
 514                         regulator-name = "vdcdc3";
 515                         regulator-min-microvolt = <1500000>;
 516                         regulator-max-microvolt = <1500000>;
 517                         regulator-boot-on;
 518                         regulator-always-on;
 519                 };
 520                 dcdc5: regulator-dcdc5 {
 521                         compatible = "ti,tps65218-dcdc5";
 522                         regulator-name = "v1_0bat";
 523                         regulator-min-microvolt = <1000000>;
 524                         regulator-max-microvolt = <1000000>;
 525                 };
 526
 527                 dcdc6: regulator-dcdc6 {
 528                         compatible = "ti,tps65218-dcdc6";
 529                         regulator-name = "v1_8bat";
 530                         regulator-min-microvolt = <1800000>;
 531                         regulator-max-microvolt = <1800000>;
 532                 };
 533
 534                 ldo1: regulator-ldo1 {
 535                         compatible = "ti,tps65218-ldo1";
 536                         regulator-min-microvolt = <1800000>;
 537                         regulator-max-microvolt = <1800000>;
 538                         regulator-boot-on;
 539                         regulator-always-on;
 540                 };
 541         };
 542
 543         ov2659@30 {
 544                 compatible = "ovti,ov2659";
 545                 reg = <0x30>;
 546
 547                 clocks = <&refclk 0>;
 548                 clock-names = "xvclk";
 549
 550                 port {
 551                         ov2659_0: endpoint {
 552                                 remote-endpoint = <&vpfe1_ep>;
 553                                 link-frequencies = /bits/ 64 <70000000>;
 554                         };
 555                 };
 556         };
 557 };
 558
 559 &i2c1 {
 560         status = "okay";
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&i2c1_pins>;
 563         pixcir_ts@5c {
 564                 compatible = "pixcir,pixcir_tangoc";
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&pixcir_ts_pins>;
 567                 reg = <0x5c>;
 568                 interrupt-parent = <&gpio3>;
 569                 interrupts = <22 0>;
 570
 571                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 572
 573                 touchscreen-size-x = <1024>;
 574                 touchscreen-size-y = <600>;
 575         };
 576
 577         ov2659@30 {
 578                 compatible = "ovti,ov2659";
 579                 reg = <0x30>;
 580
 581                 clocks = <&refclk 0>;
 582                 clock-names = "xvclk";
 583
 584                 port {
 585                         ov2659_1: endpoint {
 586                                 remote-endpoint = <&vpfe0_ep>;
 587                                 link-frequencies = /bits/ 64 <70000000>;
 588                         };
 589                 };
 590         };
 591
 592         tlv320aic3106: tlv320aic3106@1b {
 593                 #sound-dai-cells = <0>;
 594                 compatible = "ti,tlv320aic3106";
 595                 reg = <0x1b>;
 596                 status = "okay";
 597
 598                 /* Regulators */
 599                 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
 600                 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 601                 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 602                 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
 603         };
 604 };
 605
 606 &epwmss0 {
 607         status = "okay";
 608 };
 609
 610 &tscadc {
 611         status = "okay";
 612
 613         adc {
 614                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 615         };
 616 };
 617
 618 &ecap0 {
 619         status = "okay";
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&ecap0_pins>;
 622 };
 623
 624 &gpio0 {
 625         pinctrl-names = "default";
 626         pinctrl-0 = <&gpio0_pins>;
 627         status = "okay";
 628
 629         p23 {
 630                 gpio-hog;
 631                 gpios = <23 GPIO_ACTIVE_HIGH>;
 632                 /* SelEMMCorNAND selects between eMMC and NAND:
 633                  * Low: NAND
 634                  * High: eMMC
 635                  * When changing this line make sure the newly
 636                  * selected device node is enabled and the previously
 637                  * selected device node is disabled.
 638                  */
 639                 output-low;
 640                 line-name = "SelEMMCorNAND";
 641         };
 642 };
 643
 644 &gpio1 {
 645         status = "okay";
 646 };
 647
 648 &gpio3 {
 649         status = "okay";
 650 };
 651
 652 &gpio4 {
 653         status = "okay";
 654 };
 655
 656 &gpio5 {
 657         pinctrl-names = "default";
 658         pinctrl-0 = <&display_mux_pins>;
 659         status = "okay";
 660         ti,no-reset-on-init;
 661
 662         p8 {
 663                 /*
 664                  * SelLCDorHDMI selects between display and audio paths:
 665                  * Low: HDMI display with audio via HDMI
 666                  * High: LCD display with analog audio via aic3111 codec
 667                  */
 668                 gpio-hog;
 669                 gpios = <8 GPIO_ACTIVE_HIGH>;
 670                 output-high;
 671                 line-name = "SelLCDorHDMI";
 672         };
 673 };
 674
 675 &mmc1 {
 676         status = "okay";
 677         vmmc-supply = <&evm_v3_3d>;
 678         bus-width = <4>;
 679         pinctrl-names = "default";
 680         pinctrl-0 = <&mmc1_pins>;
 681         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 682 };
 683
 684 /* eMMC sits on mmc2 */
 685 &mmc2 {
 686         /*
 687          * When enabling eMMC, disable GPMC/NAND and set
 688          * SelEMMCorNAND to output-high
 689          */
 690         status = "disabled";
 691         vmmc-supply = <&evm_v3_3d>;
 692         bus-width = <8>;
 693         pinctrl-names = "default", "sleep";
 694         pinctrl-0 = <&emmc_pins_default>;
 695         pinctrl-1 = <&emmc_pins_sleep>;
 696         ti,non-removable;
 697 };
 698
 699 &mmc3 {
 700         status = "okay";
 701         /* these are on the crossbar and are outlined in the
 702            xbar-event-map element */
 703         dmas = <&edma 30
 704                 &edma 31>;
 705         dma-names = "tx", "rx";
 706         vmmc-supply = <&vmmcwl_fixed>;
 707         bus-width = <4>;
 708         pinctrl-names = "default", "sleep";
 709         pinctrl-0 = <&mmc3_pins_default>;
 710         pinctrl-1 = <&mmc3_pins_sleep>;
 711         cap-power-off-card;
 712         keep-power-in-suspend;
 713         ti,non-removable;
 714
 715         #address-cells = <1>;
 716         #size-cells = <0>;
 717         wlcore: wlcore@0 {
 718                 compatible = "ti,wl1835";
 719                 reg = <2>;
 720                 interrupt-parent = <&gpio1>;
 721                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 722         };
 723 };
 724
 725 &edma {
 726         ti,edma-xbar-event-map = /bits/ 16 <1 30
 727                                             2 31>;
 728 };
 729
 730 &uart3 {
 731         status = "okay";
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&uart3_pins>;
 734 };
 735
 736 &usb2_phy1 {
 737         status = "okay";
 738 };
 739
 740 &usb1 {
 741         dr_mode = "peripheral";
 742         status = "okay";
 743 };
 744
 745 &usb2_phy2 {
 746         status = "okay";
 747 };
 748
 749 &usb2 {
 750         dr_mode = "host";
 751         status = "okay";
 752 };
 753
 754 &mac {
 755         slaves = <1>;
 756         pinctrl-names = "default", "sleep";
 757         pinctrl-0 = <&cpsw_default>;
 758         pinctrl-1 = <&cpsw_sleep>;
 759         status = "okay";
 760 };
 761
 762 &davinci_mdio {
 763         pinctrl-names = "default", "sleep";
 764         pinctrl-0 = <&davinci_mdio_default>;
 765         pinctrl-1 = <&davinci_mdio_sleep>;
 766         status = "okay";
 767 };
 768
 769 &cpsw_emac0 {
 770         phy_id = <&davinci_mdio>, <0>;
 771         phy-mode = "rgmii";
 772 };
 773
 774 &elm {
 775         status = "okay";
 776 };
 777
 778 &gpmc {
 779         /*
 780          * When enabling GPMC, disable eMMC and set
 781          * SelEMMCorNAND to output-low
 782          */
 783         status = "okay";
 784         pinctrl-names = "default";
 785         pinctrl-0 = <&nand_flash_x8>;
 786         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 787         nand@0,0 {
 788                 reg = <0 0 4>;          /* device IO registers */
 789                 ti,nand-ecc-opt = "bch16";
 790                 ti,elm-id = <&elm>;
 791                 nand-bus-width = <8>;
 792                 gpmc,device-width = <1>;
 793                 gpmc,sync-clk-ps = <0>;
 794                 gpmc,cs-on-ns = <0>;
 795                 gpmc,cs-rd-off-ns = <40>;
 796                 gpmc,cs-wr-off-ns = <40>;
 797                 gpmc,adv-on-ns = <0>;
 798                 gpmc,adv-rd-off-ns = <25>;
 799                 gpmc,adv-wr-off-ns = <25>;
 800                 gpmc,we-on-ns = <0>;
 801                 gpmc,we-off-ns = <20>;
 802                 gpmc,oe-on-ns = <3>;
 803                 gpmc,oe-off-ns = <30>;
 804                 gpmc,access-ns = <30>;
 805                 gpmc,rd-cycle-ns = <40>;
 806                 gpmc,wr-cycle-ns = <40>;
 807                 gpmc,wait-pin = <0>;
 808                 gpmc,bus-turnaround-ns = <0>;
 809                 gpmc,cycle2cycle-delay-ns = <0>;
 810                 gpmc,clk-activation-ns = <0>;
 811                 gpmc,wait-monitoring-ns = <0>;
 812                 gpmc,wr-access-ns = <40>;
 813                 gpmc,wr-data-mux-bus-ns = <0>;
 814                 /* MTD partition table */
 815                 /* All SPL-* partitions are sized to minimal length
 816                  * which can be independently programmable. For
 817                  * NAND flash this is equal to size of erase-block */
 818                 #address-cells = <1>;
 819                 #size-cells = <1>;
 820                 partition@0 {
 821                         label = "NAND.SPL";
 822                         reg = <0x00000000 0x00040000>;
 823                 };
 824                 partition@1 {
 825                         label = "NAND.SPL.backup1";
 826                         reg = <0x00040000 0x00040000>;
 827                 };
 828                 partition@2 {
 829                         label = "NAND.SPL.backup2";
 830                         reg = <0x00080000 0x00040000>;
 831                 };
 832                 partition@3 {
 833                         label = "NAND.SPL.backup3";
 834                         reg = <0x000c0000 0x00040000>;
 835                 };
 836                 partition@4 {
 837                         label = "NAND.u-boot-spl-os";
 838                         reg = <0x00100000 0x00080000>;
 839                 };
 840                 partition@5 {
 841                         label = "NAND.u-boot";
 842                         reg = <0x00180000 0x00100000>;
 843                 };
 844                 partition@6 {
 845                         label = "NAND.u-boot-env";
 846                         reg = <0x00280000 0x00040000>;
 847                 };
 848                 partition@7 {
 849                         label = "NAND.u-boot-env.backup1";
 850                         reg = <0x002c0000 0x00040000>;
 851                 };
 852                 partition@8 {
 853                         label = "NAND.kernel";
 854                         reg = <0x00300000 0x00700000>;
 855                 };
 856                 partition@9 {
 857                         label = "NAND.file-system";
 858                         reg = <0x00a00000 0x1f600000>;
 859                 };
 860         };
 861 };
 862
 863 &dss {
 864         status = "ok";
 865
 866         pinctrl-names = "default";
 867         pinctrl-0 = <&dss_pins>;
 868
 869         port {
 870                 dpi_out: endpoint@0 {
 871                         remote-endpoint = <&lcd_in>;
 872                         data-lines = <24>;
 873                 };
 874         };
 875 };
 876
 877 &dcan0 {
 878         pinctrl-names = "default";
 879         pinctrl-0 = <&dcan0_default>;
 880         status = "okay";
 881 };
 882
 883 &dcan1 {
 884         pinctrl-names = "default";
 885         pinctrl-0 = <&dcan1_default>;
 886         status = "okay";
 887 };
 888
 889 &vpfe0 {
 890         status = "okay";
 891         pinctrl-names = "default", "sleep";
 892         pinctrl-0 = <&vpfe0_pins_default>;
 893         pinctrl-1 = <&vpfe0_pins_sleep>;
 894
 895         port {
 896                 vpfe0_ep: endpoint {
 897                         remote-endpoint = <&ov2659_1>;
 898                         ti,am437x-vpfe-interface = <0>;
 899                         bus-width = <8>;
 900                         hsync-active = <0>;
 901                         vsync-active = <0>;
 902                 };
 903         };
 904 };
 905
 906 &vpfe1 {
 907         status = "okay";
 908         pinctrl-names = "default", "sleep";
 909         pinctrl-0 = <&vpfe1_pins_default>;
 910         pinctrl-1 = <&vpfe1_pins_sleep>;
 911
 912         port {
 913                 vpfe1_ep: endpoint {
 914                         remote-endpoint = <&ov2659_0>;
 915                         ti,am437x-vpfe-interface = <0>;
 916                         bus-width = <8>;
 917                         hsync-active = <0>;
 918                         vsync-active = <0>;
 919                 };
 920         };
 921 };
 922
 923 &mcasp1 {
 924         #sound-dai-cells = <0>;
 925         pinctrl-names = "default", "sleep";
 926         pinctrl-0 = <&mcasp1_pins>;
 927         pinctrl-1 = <&mcasp1_sleep_pins>;
 928
 929         status = "okay";
 930
 931         op-mode = <0>; /* MCASP_IIS_MODE */
 932         tdm-slots = <2>;
 933         /* 4 serializers */
 934         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 935                 0 0 1 2
 936         >;
 937         tx-num-evt = <32>;
 938         rx-num-evt = <32>;
 939 };