arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
  22         };
  23
  24         evm_3v3_sd: fixedregulator-sd {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "evm_3v3_sd";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 enable-active-high;
  30                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  31         };
  32
  33         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "evm_3v3_sw";
  36                 vin-supply = <&sysen1>;
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39         };
  40
  41         aic_dvdd: fixedregulator-aic_dvdd {
  42                 /* TPS77018DBVT */
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "aic_dvdd";
  45                 vin-supply = <&evm_3v3_sw>;
  46                 regulator-min-microvolt = <1800000>;
  47                 regulator-max-microvolt = <1800000>;
  48         };
  49
  50         extcon_usb1: extcon_usb1 {
  51                 compatible = "linux,extcon-usb-gpio";
  52                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  53         };
  54
  55         extcon_usb2: extcon_usb2 {
  56                 compatible = "linux,extcon-usb-gpio";
  57                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  58         };
  59
  60         vtt_fixed: fixedregulator-vtt {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "vtt_fixed";
  63                 regulator-min-microvolt = <1350000>;
  64                 regulator-max-microvolt = <1350000>;
  65                 regulator-always-on;
  66                 regulator-boot-on;
  67                 enable-active-high;
  68                 vin-supply = <&sysen2>;
  69                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  70         };
  71
  72         sound0: sound0 {
  73                 compatible = "simple-audio-card";
  74                 simple-audio-card,name = "DRA7xx-EVM";
  75                 simple-audio-card,widgets =
  76                         "Headphone", "Headphone Jack",
  77                         "Line", "Line Out",
  78                         "Microphone", "Mic Jack",
  79                         "Line", "Line In";
  80                 simple-audio-card,routing =
  81                         "Headphone Jack",       "HPLOUT",
  82                         "Headphone Jack",       "HPROUT",
  83                         "Line Out",             "LLOUT",
  84                         "Line Out",             "RLOUT",
  85                         "MIC3L",                "Mic Jack",
  86                         "MIC3R",                "Mic Jack",
  87                         "Mic Jack",             "Mic Bias",
  88                         "LINE1L",               "Line In",
  89                         "LINE1R",               "Line In";
  90                 simple-audio-card,format = "dsp_b";
  91                 simple-audio-card,bitclock-master = <&sound0_master>;
  92                 simple-audio-card,frame-master = <&sound0_master>;
  93                 simple-audio-card,bitclock-inversion;
  94
  95                 sound0_master: simple-audio-card,cpu {
  96                         sound-dai = <&mcasp3>;
  97                         system-clock-frequency = <5644800>;
  98                 };
  99
 100                 simple-audio-card,codec {
 101                         sound-dai = <&tlv320aic3106>;
 102                         clocks = <&atl_clkin2_ck>;
 103                 };
 104         };
 105
 106         leds {
 107                 compatible = "gpio-leds";
 108                 led@0 {
 109                         label = "dra7:usr1";
 110                         gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
 111                         default-state = "off";
 112                 };
 113
 114                 led@1 {
 115                         label = "dra7:usr2";
 116                         gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
 117                         default-state = "off";
 118                 };
 119
 120                 led@2 {
 121                         label = "dra7:usr3";
 122                         gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
 123                         default-state = "off";
 124                 };
 125
 126                 led@3 {
 127                         label = "dra7:usr4";
 128                         gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
 129                         default-state = "off";
 130                 };
 131         };
 132
 133         gpio_keys {
 134                 compatible = "gpio-keys";
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 autorepeat;
 138
 139                 USER1 {
 140                         label = "btnUser1";
 141                         linux,code = <BTN_0>;
 142                         gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
 143                 };
 144
 145                 USER2 {
 146                         label = "btnUser2";
 147                         linux,code = <BTN_1>;
 148                         gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
 149                 };
 150         };
 151 };
 152
 153 &dra7_pmx_core {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&vtt_pin>;
 156
 157         vtt_pin: pinmux_vtt_pin {
 158                 pinctrl-single,pins = <
 159                         DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
 160                 >;
 161         };
 162
 163         i2c1_pins: pinmux_i2c1_pins {
 164                 pinctrl-single,pins = <
 165                         DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
 166                         DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
 167                 >;
 168         };
 169
 170         i2c2_pins: pinmux_i2c2_pins {
 171                 pinctrl-single,pins = <
 172                         DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 173                         DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 174                 >;
 175         };
 176
 177         i2c3_pins: pinmux_i2c3_pins {
 178                 pinctrl-single,pins = <
 179                         DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
 180                         DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
 181                 >;
 182         };
 183
 184         mcspi1_pins: pinmux_mcspi1_pins {
 185                 pinctrl-single,pins = <
 186                         DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
 187                         DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
 188                         DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
 189                         DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
 190                         DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
 191                         DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
 192                 >;
 193         };
 194
 195         mcspi2_pins: pinmux_mcspi2_pins {
 196                 pinctrl-single,pins = <
 197                         DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 198                         DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 199                         DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 200                         DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 201                 >;
 202         };
 203
 204         uart1_pins: pinmux_uart1_pins {
 205                 pinctrl-single,pins = <
 206                         DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 207                         DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 208                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 209                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 210                 >;
 211         };
 212
 213         uart2_pins: pinmux_uart2_pins {
 214                 pinctrl-single,pins = <
 215                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 216                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
 217                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 218                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 219                 >;
 220         };
 221
 222         uart3_pins: pinmux_uart3_pins {
 223                 pinctrl-single,pins = <
 224                         DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 225                         DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 226                 >;
 227         };
 228
 229         qspi1_pins: pinmux_qspi1_pins {
 230                 pinctrl-single,pins = <
 231                         DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 232                         DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 233                         DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 234                         DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 235                         DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 236                         DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 237                         DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 238                         DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 239                         DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 240                         DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 241                 >;
 242         };
 243
 244         usb1_pins: pinmux_usb1_pins {
 245                 pinctrl-single,pins = <
 246                         DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 247                 >;
 248         };
 249
 250         usb2_pins: pinmux_usb2_pins {
 251                 pinctrl-single,pins = <
 252                         DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 253                 >;
 254         };
 255
 256         nand_flash_x16: nand_flash_x16 {
 257                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 258                  * So NAND flash requires following switch settings:
 259                  * SW5.9 (GPMC_WPN) = LOW
 260                  * SW5.1 (NAND_BOOTn) = HIGH */
 261                 pinctrl-single,pins = <
 262                         DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad0     */
 263                         DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad1     */
 264                         DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad2     */
 265                         DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad3     */
 266                         DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad4     */
 267                         DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad5     */
 268                         DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad6     */
 269                         DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad7     */
 270                         DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad8     */
 271                         DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad9     */
 272                         DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad10    */
 273                         DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad11    */
 274                         DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad12    */
 275                         DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad13    */
 276                         DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad14    */
 277                         DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad15    */
 278                         DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP  | MUX_MODE0)        /* gpmc_wait0   */
 279                         DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0)       /* gpmc_wen     */
 280                         DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* gpmc_csn0    */
 281                         DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0)       /* gpmc_advn_ale */
 282                         DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0)       /* gpmc_oen_ren  */
 283                         DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_be0n_cle */
 284                 >;
 285         };
 286
 287         cpsw_default: cpsw_default {
 288                 pinctrl-single,pins = <
 289                         /* Slave 1 */
 290                         DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txc.rgmii0_txc */
 291                         DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txctl.rgmii0_txctl */
 292                         DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_td3.rgmii0_txd3 */
 293                         DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd2.rgmii0_txd2 */
 294                         DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd1.rgmii0_txd1 */
 295                         DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd0.rgmii0_txd0 */
 296                         DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxc.rgmii0_rxc */
 297                         DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxctl.rgmii0_rxctl */
 298                         DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd3.rgmii0_rxd3 */
 299                         DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd2.rgmii0_rxd2 */
 300                         DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd1.rgmii0_rxd1 */
 301                         DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd0.rgmii0_rxd0 */
 302
 303                         /* Slave 2 */
 304                         DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d12.rgmii1_txc */
 305                         DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d13.rgmii1_tctl */
 306                         DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d14.rgmii1_td3 */
 307                         DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d15.rgmii1_td2 */
 308                         DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d16.rgmii1_td1 */
 309                         DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d17.rgmii1_td0 */
 310                         DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)        /* vin2a_d18.rgmii1_rclk */
 311                         DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)        /* vin2a_d19.rgmii1_rctl */
 312                         DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)        /* vin2a_d20.rgmii1_rd3 */
 313                         DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)        /* vin2a_d21.rgmii1_rd2 */
 314                         DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)        /* vin2a_d22.rgmii1_rd1 */
 315                         DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)        /* vin2a_d23.rgmii1_rd0 */
 316                 >;
 317
 318         };
 319
 320         cpsw_sleep: cpsw_sleep {
 321                 pinctrl-single,pins = <
 322                         /* Slave 1 */
 323                         DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
 324                         DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
 325                         DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
 326                         DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
 327                         DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
 328                         DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
 329                         DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
 330                         DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
 331                         DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
 332                         DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
 333                         DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
 334                         DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
 335
 336                         /* Slave 2 */
 337                         DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
 338                         DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
 339                         DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
 340                         DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
 341                         DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
 342                         DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
 343                         DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
 344                         DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
 345                         DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
 346                         DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
 347                         DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
 348                         DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
 349                 >;
 350         };
 351
 352         davinci_mdio_default: davinci_mdio_default {
 353                 pinctrl-single,pins = <
 354                         DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* mdio_d.mdio_d */
 355                         DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
 356                 >;
 357         };
 358
 359         davinci_mdio_sleep: davinci_mdio_sleep {
 360                 pinctrl-single,pins = <
 361                         DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
 362                         DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
 363                 >;
 364         };
 365
 366         dcan1_pins_default: dcan1_pins_default {
 367                 pinctrl-single,pins = <
 368                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 369                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 370                 >;
 371         };
 372
 373         dcan1_pins_sleep: dcan1_pins_sleep {
 374                 pinctrl-single,pins = <
 375                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 376                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 377                 >;
 378         };
 379
 380         atl_pins: pinmux_atl_pins {
 381                 pinctrl-single,pins = <
 382                         DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)       /* xref_clk1.atl_clk1 */
 383                         DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)       /* xref_clk2.atl_clk2 */
 384                 >;
 385         };
 386
 387         mcasp3_pins: pinmux_mcasp3_pins {
 388                 pinctrl-single,pins = <
 389                         DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_aclkx */
 390                         DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_fsx */
 391                         DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_axr0 */
 392                         DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcasp3_axr1 */
 393                 >;
 394         };
 395
 396         mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
 397                 pinctrl-single,pins = <
 398                         DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
 399                         DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
 400                         DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
 401                         DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
 402                 >;
 403         };
 404 };
 405
 406 &i2c1 {
 407         status = "okay";
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&i2c1_pins>;
 410         clock-frequency = <400000>;
 411
 412         tps659038: tps659038@58 {
 413                 compatible = "ti,tps659038";
 414                 reg = <0x58>;
 415
 416                 tps659038_pmic {
 417                         compatible = "ti,tps659038-pmic";
 418
 419                         regulators {
 420                                 smps123_reg: smps123 {
 421                                         /* VDD_MPU */
 422                                         regulator-name = "smps123";
 423                                         regulator-min-microvolt = < 850000>;
 424                                         regulator-max-microvolt = <1250000>;
 425                                         regulator-always-on;
 426                                         regulator-boot-on;
 427                                 };
 428
 429                                 smps45_reg: smps45 {
 430                                         /* VDD_DSPEVE */
 431                                         regulator-name = "smps45";
 432                                         regulator-min-microvolt = < 850000>;
 433                                         regulator-max-microvolt = <1150000>;
 434                                         regulator-always-on;
 435                                         regulator-boot-on;
 436                                 };
 437
 438                                 smps6_reg: smps6 {
 439                                         /* VDD_GPU - over VDD_SMPS6 */
 440                                         regulator-name = "smps6";
 441                                         regulator-min-microvolt = <850000>;
 442                                         regulator-max-microvolt = <1250000>;
 443                                         regulator-always-on;
 444                                         regulator-boot-on;
 445                                 };
 446
 447                                 smps7_reg: smps7 {
 448                                         /* CORE_VDD */
 449                                         regulator-name = "smps7";
 450                                         regulator-min-microvolt = <850000>;
 451                                         regulator-max-microvolt = <1060000>;
 452                                         regulator-always-on;
 453                                         regulator-boot-on;
 454                                 };
 455
 456                                 smps8_reg: smps8 {
 457                                         /* VDD_IVAHD */
 458                                         regulator-name = "smps8";
 459                                         regulator-min-microvolt = < 850000>;
 460                                         regulator-max-microvolt = <1250000>;
 461                                         regulator-always-on;
 462                                         regulator-boot-on;
 463                                 };
 464
 465                                 smps9_reg: smps9 {
 466                                         /* VDDS1V8 */
 467                                         regulator-name = "smps9";
 468                                         regulator-min-microvolt = <1800000>;
 469                                         regulator-max-microvolt = <1800000>;
 470                                         regulator-always-on;
 471                                         regulator-boot-on;
 472                                 };
 473
 474                                 ldo1_reg: ldo1 {
 475                                         /* LDO1_OUT --> SDIO  */
 476                                         regulator-name = "ldo1";
 477                                         regulator-min-microvolt = <1800000>;
 478                                         regulator-max-microvolt = <3300000>;
 479                                         regulator-always-on;
 480                                         regulator-boot-on;
 481                                 };
 482
 483                                 ldo2_reg: ldo2 {
 484                                         /* VDD_RTCIO */
 485                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 486                                         regulator-name = "ldo2";
 487                                         regulator-min-microvolt = <3300000>;
 488                                         regulator-max-microvolt = <3300000>;
 489                                         regulator-always-on;
 490                                         regulator-boot-on;
 491                                 };
 492
 493                                 ldo3_reg: ldo3 {
 494                                         /* VDDA_1V8_PHY */
 495                                         regulator-name = "ldo3";
 496                                         regulator-min-microvolt = <1800000>;
 497                                         regulator-max-microvolt = <1800000>;
 498                                         regulator-always-on;
 499                                         regulator-boot-on;
 500                                 };
 501
 502                                 ldo9_reg: ldo9 {
 503                                         /* VDD_RTC */
 504                                         regulator-name = "ldo9";
 505                                         regulator-min-microvolt = <1050000>;
 506                                         regulator-max-microvolt = <1050000>;
 507                                         regulator-always-on;
 508                                         regulator-boot-on;
 509                                         regulator-allow-bypass;
 510                                 };
 511
 512                                 ldoln_reg: ldoln {
 513                                         /* VDDA_1V8_PLL */
 514                                         regulator-name = "ldoln";
 515                                         regulator-min-microvolt = <1800000>;
 516                                         regulator-max-microvolt = <1800000>;
 517                                         regulator-always-on;
 518                                         regulator-boot-on;
 519                                 };
 520
 521                                 ldousb_reg: ldousb {
 522                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 523                                         regulator-name = "ldousb";
 524                                         regulator-min-microvolt = <3300000>;
 525                                         regulator-max-microvolt = <3300000>;
 526                                         regulator-boot-on;
 527                                 };
 528
 529                                 /* REGEN1 is unused */
 530
 531                                 regen2: regen2 {
 532                                         /* Needed for PMIC internal resources */
 533                                         regulator-name = "regen2";
 534                                         regulator-boot-on;
 535                                         regulator-always-on;
 536                                 };
 537
 538                                 /* REGEN3 is unused */
 539
 540                                 sysen1: sysen1 {
 541                                         /* PMIC_REGEN_3V3 */
 542                                         regulator-name = "sysen1";
 543                                         regulator-boot-on;
 544                                         regulator-always-on;
 545                                 };
 546
 547                                 sysen2: sysen2 {
 548                                         /* PMIC_REGEN_DDR */
 549                                         regulator-name = "sysen2";
 550                                         regulator-boot-on;
 551                                         regulator-always-on;
 552                                 };
 553                         };
 554                 };
 555         };
 556
 557         pcf_lcd: gpio@20 {
 558                 compatible = "nxp,pcf8575";
 559                 reg = <0x20>;
 560                 gpio-controller;
 561                 #gpio-cells = <2>;
 562                 interrupt-parent = <&gpio6>;
 563                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 564                 interrupt-controller;
 565                 #interrupt-cells = <2>;
 566         };
 567
 568         pcf_gpio_21: gpio@21 {
 569                 compatible = "ti,pcf8575";
 570                 reg = <0x21>;
 571                 lines-initial-states = <0x1408>;
 572                 gpio-controller;
 573                 #gpio-cells = <2>;
 574                 interrupt-parent = <&gpio6>;
 575                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 576                 interrupt-controller;
 577                 #interrupt-cells = <2>;
 578         };
 579
 580         tlv320aic3106: tlv320aic3106@19 {
 581                 #sound-dai-cells = <0>;
 582                 compatible = "ti,tlv320aic3106";
 583                 reg = <0x19>;
 584                 adc-settle-ms = <40>;
 585                 ai3x-micbias-vg = <1>;          /* 2.0V */
 586                 status = "okay";
 587
 588                 /* Regulators */
 589                 AVDD-supply = <&evm_3v3_sw>;
 590                 IOVDD-supply = <&evm_3v3_sw>;
 591                 DRVDD-supply = <&evm_3v3_sw>;
 592                 DVDD-supply = <&aic_dvdd>;
 593         };
 594 };
 595
 596 &i2c2 {
 597         status = "okay";
 598         pinctrl-names = "default";
 599         pinctrl-0 = <&i2c2_pins>;
 600         clock-frequency = <400000>;
 601
 602         pcf_hdmi: gpio@26 {
 603                 compatible = "nxp,pcf8575";
 604                 reg = <0x26>;
 605                 gpio-controller;
 606                 #gpio-cells = <2>;
 607                 p1 {
 608                         /* vin6_sel_s0: high: VIN6, low: audio */
 609                         gpio-hog;
 610                         gpios = <1 GPIO_ACTIVE_HIGH>;
 611                         output-low;
 612                         line-name = "vin6_sel_s0";
 613                 };
 614         };
 615 };
 616
 617 &i2c3 {
 618         status = "okay";
 619         pinctrl-names = "default";
 620         pinctrl-0 = <&i2c3_pins>;
 621         clock-frequency = <400000>;
 622 };
 623
 624 &mcspi1 {
 625         status = "okay";
 626         pinctrl-names = "default";
 627         pinctrl-0 = <&mcspi1_pins>;
 628 };
 629
 630 &mcspi2 {
 631         status = "okay";
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&mcspi2_pins>;
 634 };
 635
 636 &uart1 {
 637         status = "okay";
 638         pinctrl-names = "default";
 639         pinctrl-0 = <&uart1_pins>;
 640         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 641                               <&dra7_pmx_core 0x3e0>;
 642 };
 643
 644 &uart2 {
 645         status = "okay";
 646         pinctrl-names = "default";
 647         pinctrl-0 = <&uart2_pins>;
 648 };
 649
 650 &uart3 {
 651         status = "okay";
 652         pinctrl-names = "default";
 653         pinctrl-0 = <&uart3_pins>;
 654 };
 655
 656 &mmc1 {
 657         status = "okay";
 658         vmmc-supply = <&evm_3v3_sd>;
 659         vmmc_aux-supply = <&ldo1_reg>;
 660         bus-width = <4>;
 661         /*
 662          * SDCD signal is not being used here - using the fact that GPIO mode
 663          * is always hardwired.
 664          */
 665         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 666 };
 667
 668 &mmc2 {
 669         status = "okay";
 670         vmmc-supply = <&evm_3v3_sw>;
 671         bus-width = <8>;
 672 };
 673
 674 &cpu0 {
 675         cpu0-supply = <&smps123_reg>;
 676 };
 677
 678 &qspi {
 679         status = "okay";
 680         pinctrl-names = "default";
 681         pinctrl-0 = <&qspi1_pins>;
 682
 683         spi-max-frequency = <48000000>;
 684         m25p80@0 {
 685                 compatible = "s25fl256s1";
 686                 spi-max-frequency = <48000000>;
 687                 reg = <0>;
 688                 spi-tx-bus-width = <1>;
 689                 spi-rx-bus-width = <4>;
 690                 spi-cpol;
 691                 spi-cpha;
 692                 #address-cells = <1>;
 693                 #size-cells = <1>;
 694
 695                 /* MTD partition table.
 696                  * The ROM checks the first four physical blocks
 697                  * for a valid file to boot and the flash here is
 698                  * 64KiB block size.
 699                  */
 700                 partition@0 {
 701                         label = "QSPI.SPL";
 702                         reg = <0x00000000 0x000010000>;
 703                 };
 704                 partition@1 {
 705                         label = "QSPI.SPL.backup1";
 706                         reg = <0x00010000 0x00010000>;
 707                 };
 708                 partition@2 {
 709                         label = "QSPI.SPL.backup2";
 710                         reg = <0x00020000 0x00010000>;
 711                 };
 712                 partition@3 {
 713                         label = "QSPI.SPL.backup3";
 714                         reg = <0x00030000 0x00010000>;
 715                 };
 716                 partition@4 {
 717                         label = "QSPI.u-boot";
 718                         reg = <0x00040000 0x00100000>;
 719                 };
 720                 partition@5 {
 721                         label = "QSPI.u-boot-spl-os";
 722                         reg = <0x00140000 0x00080000>;
 723                 };
 724                 partition@6 {
 725                         label = "QSPI.u-boot-env";
 726                         reg = <0x001c0000 0x00010000>;
 727                 };
 728                 partition@7 {
 729                         label = "QSPI.u-boot-env.backup1";
 730                         reg = <0x001d0000 0x0010000>;
 731                 };
 732                 partition@8 {
 733                         label = "QSPI.kernel";
 734                         reg = <0x001e0000 0x0800000>;
 735                 };
 736                 partition@9 {
 737                         label = "QSPI.file-system";
 738                         reg = <0x009e0000 0x01620000>;
 739                 };
 740         };
 741 };
 742
 743 &omap_dwc3_1 {
 744         extcon = <&extcon_usb1>;
 745 };
 746
 747 &omap_dwc3_2 {
 748         extcon = <&extcon_usb2>;
 749 };
 750
 751 &usb1 {
 752         dr_mode = "peripheral";
 753         pinctrl-names = "default";
 754         pinctrl-0 = <&usb1_pins>;
 755 };
 756
 757 &usb2 {
 758         dr_mode = "host";
 759         pinctrl-names = "default";
 760         pinctrl-0 = <&usb2_pins>;
 761 };
 762
 763 &elm {
 764         status = "okay";
 765 };
 766
 767 &gpmc {
 768         status = "okay";
 769         pinctrl-names = "default";
 770         pinctrl-0 = <&nand_flash_x16>;
 771         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 772         nand@0,0 {
 773                 compatible = "ti,omap2-nand";
 774                 reg = <0 0 4>;          /* device IO registers */
 775                 interrupt-parent = <&gpmc>;
 776                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 777                              <1 IRQ_TYPE_NONE>; /* termcount */
 778                 ti,nand-ecc-opt = "bch8";
 779                 ti,elm-id = <&elm>;
 780                 nand-bus-width = <16>;
 781                 gpmc,device-width = <2>;
 782                 gpmc,sync-clk-ps = <0>;
 783                 gpmc,cs-on-ns = <0>;
 784                 gpmc,cs-rd-off-ns = <80>;
 785                 gpmc,cs-wr-off-ns = <80>;
 786                 gpmc,adv-on-ns = <0>;
 787                 gpmc,adv-rd-off-ns = <60>;
 788                 gpmc,adv-wr-off-ns = <60>;
 789                 gpmc,we-on-ns = <10>;
 790                 gpmc,we-off-ns = <50>;
 791                 gpmc,oe-on-ns = <4>;
 792                 gpmc,oe-off-ns = <40>;
 793                 gpmc,access-ns = <40>;
 794                 gpmc,wr-access-ns = <80>;
 795                 gpmc,rd-cycle-ns = <80>;
 796                 gpmc,wr-cycle-ns = <80>;
 797                 gpmc,bus-turnaround-ns = <0>;
 798                 gpmc,cycle2cycle-delay-ns = <0>;
 799                 gpmc,clk-activation-ns = <0>;
 800                 gpmc,wr-data-mux-bus-ns = <0>;
 801                 /* MTD partition table */
 802                 /* All SPL-* partitions are sized to minimal length
 803                  * which can be independently programmable. For
 804                  * NAND flash this is equal to size of erase-block */
 805                 #address-cells = <1>;
 806                 #size-cells = <1>;
 807                 partition@0 {
 808                         label = "NAND.SPL";
 809                         reg = <0x00000000 0x000020000>;
 810                 };
 811                 partition@1 {
 812                         label = "NAND.SPL.backup1";
 813                         reg = <0x00020000 0x00020000>;
 814                 };
 815                 partition@2 {
 816                         label = "NAND.SPL.backup2";
 817                         reg = <0x00040000 0x00020000>;
 818                 };
 819                 partition@3 {
 820                         label = "NAND.SPL.backup3";
 821                         reg = <0x00060000 0x00020000>;
 822                 };
 823                 partition@4 {
 824                         label = "NAND.u-boot-spl-os";
 825                         reg = <0x00080000 0x00040000>;
 826                 };
 827                 partition@5 {
 828                         label = "NAND.u-boot";
 829                         reg = <0x000c0000 0x00100000>;
 830                 };
 831                 partition@6 {
 832                         label = "NAND.u-boot-env";
 833                         reg = <0x001c0000 0x00020000>;
 834                 };
 835                 partition@7 {
 836                         label = "NAND.u-boot-env.backup1";
 837                         reg = <0x001e0000 0x00020000>;
 838                 };
 839                 partition@8 {
 840                         label = "NAND.kernel";
 841                         reg = <0x00200000 0x00800000>;
 842                 };
 843                 partition@9 {
 844                         label = "NAND.file-system";
 845                         reg = <0x00a00000 0x0f600000>;
 846                 };
 847         };
 848 };
 849
 850 &usb2_phy1 {
 851         phy-supply = <&ldousb_reg>;
 852 };
 853
 854 &usb2_phy2 {
 855         phy-supply = <&ldousb_reg>;
 856 };
 857
 858 &gpio7 {
 859         ti,no-reset-on-init;
 860         ti,no-idle-on-init;
 861 };
 862
 863 &mac {
 864         status = "okay";
 865         pinctrl-names = "default", "sleep";
 866         pinctrl-0 = <&cpsw_default>;
 867         pinctrl-1 = <&cpsw_sleep>;
 868         dual_emac;
 869 };
 870
 871 &cpsw_emac0 {
 872         phy_id = <&davinci_mdio>, <2>;
 873         phy-mode = "rgmii";
 874         dual_emac_res_vlan = <1>;
 875 };
 876
 877 &cpsw_emac1 {
 878         phy_id = <&davinci_mdio>, <3>;
 879         phy-mode = "rgmii";
 880         dual_emac_res_vlan = <2>;
 881 };
 882
 883 &davinci_mdio {
 884         pinctrl-names = "default", "sleep";
 885         pinctrl-0 = <&davinci_mdio_default>;
 886         pinctrl-1 = <&davinci_mdio_sleep>;
 887 };
 888
 889 &dcan1 {
 890         status = "ok";
 891         pinctrl-names = "default", "sleep", "active";
 892         pinctrl-0 = <&dcan1_pins_sleep>;
 893         pinctrl-1 = <&dcan1_pins_sleep>;
 894         pinctrl-2 = <&dcan1_pins_default>;
 895 };
 896
 897 &atl {
 898         pinctrl-names = "default";
 899         pinctrl-0 = <&atl_pins>;
 900
 901         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 902                           <&atl_gfclk_mux>,
 903                           <&dpll_abe_ck>,
 904                           <&dpll_abe_m2x2_ck>,
 905                           <&atl_clkin2_ck>;
 906         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 907         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 908
 909         status = "okay";
 910
 911         atl2 {
 912                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 913                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 914         };
 915 };
 916
 917 &mcasp3 {
 918         #sound-dai-cells = <0>;
 919         pinctrl-names = "default", "sleep";
 920         pinctrl-0 = <&mcasp3_pins>;
 921         pinctrl-1 = <&mcasp3_sleep_pins>;
 922
 923         assigned-clocks = <&mcasp3_ahclkx_mux>;
 924         assigned-clock-parents = <&atl_clkin2_ck>;
 925
 926         status = "okay";
 927
 928         op-mode = <0>;          /* MCASP_IIS_MODE */
 929         tdm-slots = <2>;
 930         /* 4 serializer */
 931         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 932                 1 2 0 0
 933         >;
 934         tx-num-evt = <32>;
 935         rx-num-evt = <32>;
 936 };
 937
 938 &mailbox5 {
 939         status = "okay";
 940         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 941                 status = "okay";
 942         };
 943         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 944                 status = "okay";
 945         };
 946 };
 947
 948 &mailbox6 {
 949         status = "okay";
 950         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 951                 status = "okay";
 952         };
 953         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 954                 status = "okay";
 955         };
 956 };