arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
  22         };
  23
  24         evm_3v3_sd: fixedregulator-sd {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "evm_3v3_sd";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 enable-active-high;
  30                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  31         };
  32
  33         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "evm_3v3_sw";
  36                 vin-supply = <&sysen1>;
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39         };
  40
  41         aic_dvdd: fixedregulator-aic_dvdd {
  42                 /* TPS77018DBVT */
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "aic_dvdd";
  45                 vin-supply = <&evm_3v3_sw>;
  46                 regulator-min-microvolt = <1800000>;
  47                 regulator-max-microvolt = <1800000>;
  48         };
  49
  50         extcon_usb1: extcon_usb1 {
  51                 compatible = "linux,extcon-usb-gpio";
  52                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  53         };
  54
  55         extcon_usb2: extcon_usb2 {
  56                 compatible = "linux,extcon-usb-gpio";
  57                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  58         };
  59
  60         vtt_fixed: fixedregulator-vtt {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "vtt_fixed";
  63                 regulator-min-microvolt = <1350000>;
  64                 regulator-max-microvolt = <1350000>;
  65                 regulator-always-on;
  66                 regulator-boot-on;
  67                 enable-active-high;
  68                 vin-supply = <&sysen2>;
  69                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  70         };
  71
  72         sound0: sound0 {
  73                 compatible = "simple-audio-card";
  74                 simple-audio-card,name = "DRA7xx-EVM";
  75                 simple-audio-card,widgets =
  76                         "Headphone", "Headphone Jack",
  77                         "Line", "Line Out",
  78                         "Microphone", "Mic Jack",
  79                         "Line", "Line In";
  80                 simple-audio-card,routing =
  81                         "Headphone Jack",       "HPLOUT",
  82                         "Headphone Jack",       "HPROUT",
  83                         "Line Out",             "LLOUT",
  84                         "Line Out",             "RLOUT",
  85                         "MIC3L",                "Mic Jack",
  86                         "MIC3R",                "Mic Jack",
  87                         "Mic Jack",             "Mic Bias",
  88                         "LINE1L",               "Line In",
  89                         "LINE1R",               "Line In";
  90                 simple-audio-card,format = "dsp_b";
  91                 simple-audio-card,bitclock-master = <&sound0_master>;
  92                 simple-audio-card,frame-master = <&sound0_master>;
  93                 simple-audio-card,bitclock-inversion;
  94
  95                 sound0_master: simple-audio-card,cpu {
  96                         sound-dai = <&mcasp3>;
  97                         system-clock-frequency = <5644800>;
  98                 };
  99
 100                 simple-audio-card,codec {
 101                         sound-dai = <&tlv320aic3106>;
 102                         clocks = <&atl_clkin2_ck>;
 103                 };
 104         };
 105
 106         leds {
 107                 compatible = "gpio-leds";
 108                 led@0 {
 109                         label = "dra7:usr1";
 110                         gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
 111                         default-state = "off";
 112                 };
 113
 114                 led@1 {
 115                         label = "dra7:usr2";
 116                         gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
 117                         default-state = "off";
 118                 };
 119
 120                 led@2 {
 121                         label = "dra7:usr3";
 122                         gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
 123                         default-state = "off";
 124                 };
 125
 126                 led@3 {
 127                         label = "dra7:usr4";
 128                         gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
 129                         default-state = "off";
 130                 };
 131         };
 132
 133         gpio_keys {
 134                 compatible = "gpio-keys";
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 autorepeat;
 138
 139                 USER1 {
 140                         label = "btnUser1";
 141                         linux,code = <BTN_0>;
 142                         gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
 143                 };
 144
 145                 USER2 {
 146                         label = "btnUser2";
 147                         linux,code = <BTN_1>;
 148                         gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
 149                 };
 150         };
 151 };
 152
 153 &dra7_pmx_core {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&vtt_pin>;
 156
 157         vtt_pin: pinmux_vtt_pin {
 158                 pinctrl-single,pins = <
 159                         DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
 160                 >;
 161         };
 162
 163         i2c1_pins: pinmux_i2c1_pins {
 164                 pinctrl-single,pins = <
 165                         DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
 166                         DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
 167                 >;
 168         };
 169
 170         i2c2_pins: pinmux_i2c2_pins {
 171                 pinctrl-single,pins = <
 172                         DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 173                         DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 174                 >;
 175         };
 176
 177         i2c3_pins: pinmux_i2c3_pins {
 178                 pinctrl-single,pins = <
 179                         DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
 180                         DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
 181                 >;
 182         };
 183
 184         mcspi1_pins: pinmux_mcspi1_pins {
 185                 pinctrl-single,pins = <
 186                         DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
 187                         DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
 188                         DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
 189                         DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
 190                         DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
 191                         DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
 192                 >;
 193         };
 194
 195         mcspi2_pins: pinmux_mcspi2_pins {
 196                 pinctrl-single,pins = <
 197                         DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 198                         DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 199                         DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 200                         DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 201                 >;
 202         };
 203
 204         uart1_pins: pinmux_uart1_pins {
 205                 pinctrl-single,pins = <
 206                         DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 207                         DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 208                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 209                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 210                 >;
 211         };
 212
 213         uart2_pins: pinmux_uart2_pins {
 214                 pinctrl-single,pins = <
 215                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 216                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
 217                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 218                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 219                 >;
 220         };
 221
 222         uart3_pins: pinmux_uart3_pins {
 223                 pinctrl-single,pins = <
 224                         DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 225                         DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 226                 >;
 227         };
 228
 229         qspi1_pins: pinmux_qspi1_pins {
 230                 pinctrl-single,pins = <
 231                         DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 232                         DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 233                         DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 234                         DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 235                         DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 236                         DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 237                         DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 238                         DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 239                         DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 240                         DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 241                 >;
 242         };
 243
 244         usb1_pins: pinmux_usb1_pins {
 245                 pinctrl-single,pins = <
 246                         DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 247                 >;
 248         };
 249
 250         usb2_pins: pinmux_usb2_pins {
 251                 pinctrl-single,pins = <
 252                         DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 253                 >;
 254         };
 255
 256         nand_flash_x16: nand_flash_x16 {
 257                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 258                  * So NAND flash requires following switch settings:
 259                  * SW5.1 (NAND_BOOTn) = ON (LOW)
 260                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 261                  */
 262                 pinctrl-single,pins = <
 263                         DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad0     */
 264                         DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad1     */
 265                         DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad2     */
 266                         DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad3     */
 267                         DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad4     */
 268                         DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad5     */
 269                         DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad6     */
 270                         DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad7     */
 271                         DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad8     */
 272                         DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad9     */
 273                         DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad10    */
 274                         DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad11    */
 275                         DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad12    */
 276                         DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad13    */
 277                         DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad14    */
 278                         DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad15    */
 279                         DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP  | MUX_MODE0)        /* gpmc_wait0   */
 280                         DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0)       /* gpmc_wen     */
 281                         DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* gpmc_csn0    */
 282                         DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0)       /* gpmc_advn_ale */
 283                         DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0)       /* gpmc_oen_ren  */
 284                         DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_be0n_cle */
 285                 >;
 286         };
 287
 288         cpsw_default: cpsw_default {
 289                 pinctrl-single,pins = <
 290                         /* Slave 1 */
 291                         DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txc.rgmii0_txc */
 292                         DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txctl.rgmii0_txctl */
 293                         DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_td3.rgmii0_txd3 */
 294                         DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd2.rgmii0_txd2 */
 295                         DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd1.rgmii0_txd1 */
 296                         DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd0.rgmii0_txd0 */
 297                         DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxc.rgmii0_rxc */
 298                         DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxctl.rgmii0_rxctl */
 299                         DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd3.rgmii0_rxd3 */
 300                         DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd2.rgmii0_rxd2 */
 301                         DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd1.rgmii0_rxd1 */
 302                         DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd0.rgmii0_rxd0 */
 303
 304                         /* Slave 2 */
 305                         DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d12.rgmii1_txc */
 306                         DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d13.rgmii1_tctl */
 307                         DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d14.rgmii1_td3 */
 308                         DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d15.rgmii1_td2 */
 309                         DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d16.rgmii1_td1 */
 310                         DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d17.rgmii1_td0 */
 311                         DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)        /* vin2a_d18.rgmii1_rclk */
 312                         DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)        /* vin2a_d19.rgmii1_rctl */
 313                         DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)        /* vin2a_d20.rgmii1_rd3 */
 314                         DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)        /* vin2a_d21.rgmii1_rd2 */
 315                         DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)        /* vin2a_d22.rgmii1_rd1 */
 316                         DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)        /* vin2a_d23.rgmii1_rd0 */
 317                 >;
 318
 319         };
 320
 321         cpsw_sleep: cpsw_sleep {
 322                 pinctrl-single,pins = <
 323                         /* Slave 1 */
 324                         DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
 325                         DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
 326                         DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
 327                         DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
 328                         DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
 329                         DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
 330                         DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
 331                         DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
 332                         DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
 333                         DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
 334                         DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
 335                         DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
 336
 337                         /* Slave 2 */
 338                         DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
 339                         DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
 340                         DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
 341                         DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
 342                         DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
 343                         DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
 344                         DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
 345                         DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
 346                         DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
 347                         DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
 348                         DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
 349                         DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
 350                 >;
 351         };
 352
 353         davinci_mdio_default: davinci_mdio_default {
 354                 pinctrl-single,pins = <
 355                         DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* mdio_d.mdio_d */
 356                         DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
 357                 >;
 358         };
 359
 360         davinci_mdio_sleep: davinci_mdio_sleep {
 361                 pinctrl-single,pins = <
 362                         DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
 363                         DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
 364                 >;
 365         };
 366
 367         dcan1_pins_default: dcan1_pins_default {
 368                 pinctrl-single,pins = <
 369                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 370                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 371                 >;
 372         };
 373
 374         dcan1_pins_sleep: dcan1_pins_sleep {
 375                 pinctrl-single,pins = <
 376                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 377                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 378                 >;
 379         };
 380
 381         atl_pins: pinmux_atl_pins {
 382                 pinctrl-single,pins = <
 383                         DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)       /* xref_clk1.atl_clk1 */
 384                         DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)       /* xref_clk2.atl_clk2 */
 385                 >;
 386         };
 387
 388         mcasp3_pins: pinmux_mcasp3_pins {
 389                 pinctrl-single,pins = <
 390                         DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_aclkx */
 391                         DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_fsx */
 392                         DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_axr0 */
 393                         DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcasp3_axr1 */
 394                 >;
 395         };
 396
 397         mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
 398                 pinctrl-single,pins = <
 399                         DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
 400                         DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
 401                         DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
 402                         DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
 403                 >;
 404         };
 405 };
 406
 407 &i2c1 {
 408         status = "okay";
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&i2c1_pins>;
 411         clock-frequency = <400000>;
 412
 413         tps659038: tps659038@58 {
 414                 compatible = "ti,tps659038";
 415                 reg = <0x58>;
 416
 417                 tps659038_pmic {
 418                         compatible = "ti,tps659038-pmic";
 419
 420                         regulators {
 421                                 smps123_reg: smps123 {
 422                                         /* VDD_MPU */
 423                                         regulator-name = "smps123";
 424                                         regulator-min-microvolt = < 850000>;
 425                                         regulator-max-microvolt = <1250000>;
 426                                         regulator-always-on;
 427                                         regulator-boot-on;
 428                                 };
 429
 430                                 smps45_reg: smps45 {
 431                                         /* VDD_DSPEVE */
 432                                         regulator-name = "smps45";
 433                                         regulator-min-microvolt = < 850000>;
 434                                         regulator-max-microvolt = <1150000>;
 435                                         regulator-always-on;
 436                                         regulator-boot-on;
 437                                 };
 438
 439                                 smps6_reg: smps6 {
 440                                         /* VDD_GPU - over VDD_SMPS6 */
 441                                         regulator-name = "smps6";
 442                                         regulator-min-microvolt = <850000>;
 443                                         regulator-max-microvolt = <1250000>;
 444                                         regulator-always-on;
 445                                         regulator-boot-on;
 446                                 };
 447
 448                                 smps7_reg: smps7 {
 449                                         /* CORE_VDD */
 450                                         regulator-name = "smps7";
 451                                         regulator-min-microvolt = <850000>;
 452                                         regulator-max-microvolt = <1060000>;
 453                                         regulator-always-on;
 454                                         regulator-boot-on;
 455                                 };
 456
 457                                 smps8_reg: smps8 {
 458                                         /* VDD_IVAHD */
 459                                         regulator-name = "smps8";
 460                                         regulator-min-microvolt = < 850000>;
 461                                         regulator-max-microvolt = <1250000>;
 462                                         regulator-always-on;
 463                                         regulator-boot-on;
 464                                 };
 465
 466                                 smps9_reg: smps9 {
 467                                         /* VDDS1V8 */
 468                                         regulator-name = "smps9";
 469                                         regulator-min-microvolt = <1800000>;
 470                                         regulator-max-microvolt = <1800000>;
 471                                         regulator-always-on;
 472                                         regulator-boot-on;
 473                                 };
 474
 475                                 ldo1_reg: ldo1 {
 476                                         /* LDO1_OUT --> SDIO  */
 477                                         regulator-name = "ldo1";
 478                                         regulator-min-microvolt = <1800000>;
 479                                         regulator-max-microvolt = <3300000>;
 480                                         regulator-always-on;
 481                                         regulator-boot-on;
 482                                 };
 483
 484                                 ldo2_reg: ldo2 {
 485                                         /* VDD_RTCIO */
 486                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 487                                         regulator-name = "ldo2";
 488                                         regulator-min-microvolt = <3300000>;
 489                                         regulator-max-microvolt = <3300000>;
 490                                         regulator-always-on;
 491                                         regulator-boot-on;
 492                                 };
 493
 494                                 ldo3_reg: ldo3 {
 495                                         /* VDDA_1V8_PHY */
 496                                         regulator-name = "ldo3";
 497                                         regulator-min-microvolt = <1800000>;
 498                                         regulator-max-microvolt = <1800000>;
 499                                         regulator-always-on;
 500                                         regulator-boot-on;
 501                                 };
 502
 503                                 ldo9_reg: ldo9 {
 504                                         /* VDD_RTC */
 505                                         regulator-name = "ldo9";
 506                                         regulator-min-microvolt = <1050000>;
 507                                         regulator-max-microvolt = <1050000>;
 508                                         regulator-always-on;
 509                                         regulator-boot-on;
 510                                         regulator-allow-bypass;
 511                                 };
 512
 513                                 ldoln_reg: ldoln {
 514                                         /* VDDA_1V8_PLL */
 515                                         regulator-name = "ldoln";
 516                                         regulator-min-microvolt = <1800000>;
 517                                         regulator-max-microvolt = <1800000>;
 518                                         regulator-always-on;
 519                                         regulator-boot-on;
 520                                 };
 521
 522                                 ldousb_reg: ldousb {
 523                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 524                                         regulator-name = "ldousb";
 525                                         regulator-min-microvolt = <3300000>;
 526                                         regulator-max-microvolt = <3300000>;
 527                                         regulator-boot-on;
 528                                 };
 529
 530                                 /* REGEN1 is unused */
 531
 532                                 regen2: regen2 {
 533                                         /* Needed for PMIC internal resources */
 534                                         regulator-name = "regen2";
 535                                         regulator-boot-on;
 536                                         regulator-always-on;
 537                                 };
 538
 539                                 /* REGEN3 is unused */
 540
 541                                 sysen1: sysen1 {
 542                                         /* PMIC_REGEN_3V3 */
 543                                         regulator-name = "sysen1";
 544                                         regulator-boot-on;
 545                                         regulator-always-on;
 546                                 };
 547
 548                                 sysen2: sysen2 {
 549                                         /* PMIC_REGEN_DDR */
 550                                         regulator-name = "sysen2";
 551                                         regulator-boot-on;
 552                                         regulator-always-on;
 553                                 };
 554                         };
 555                 };
 556         };
 557
 558         pcf_lcd: gpio@20 {
 559                 compatible = "nxp,pcf8575";
 560                 reg = <0x20>;
 561                 gpio-controller;
 562                 #gpio-cells = <2>;
 563                 interrupt-parent = <&gpio6>;
 564                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 565                 interrupt-controller;
 566                 #interrupt-cells = <2>;
 567         };
 568
 569         pcf_gpio_21: gpio@21 {
 570                 compatible = "nxp,pcf8575";
 571                 reg = <0x21>;
 572                 lines-initial-states = <0x1408>;
 573                 gpio-controller;
 574                 #gpio-cells = <2>;
 575                 interrupt-parent = <&gpio6>;
 576                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 577                 interrupt-controller;
 578                 #interrupt-cells = <2>;
 579         };
 580
 581         tlv320aic3106: tlv320aic3106@19 {
 582                 #sound-dai-cells = <0>;
 583                 compatible = "ti,tlv320aic3106";
 584                 reg = <0x19>;
 585                 adc-settle-ms = <40>;
 586                 ai3x-micbias-vg = <1>;          /* 2.0V */
 587                 status = "okay";
 588
 589                 /* Regulators */
 590                 AVDD-supply = <&evm_3v3_sw>;
 591                 IOVDD-supply = <&evm_3v3_sw>;
 592                 DRVDD-supply = <&evm_3v3_sw>;
 593                 DVDD-supply = <&aic_dvdd>;
 594         };
 595 };
 596
 597 &i2c2 {
 598         status = "okay";
 599         pinctrl-names = "default";
 600         pinctrl-0 = <&i2c2_pins>;
 601         clock-frequency = <400000>;
 602
 603         pcf_hdmi: gpio@26 {
 604                 compatible = "nxp,pcf8575";
 605                 reg = <0x26>;
 606                 gpio-controller;
 607                 #gpio-cells = <2>;
 608                 p1 {
 609                         /* vin6_sel_s0: high: VIN6, low: audio */
 610                         gpio-hog;
 611                         gpios = <1 GPIO_ACTIVE_HIGH>;
 612                         output-low;
 613                         line-name = "vin6_sel_s0";
 614                 };
 615         };
 616 };
 617
 618 &i2c3 {
 619         status = "okay";
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&i2c3_pins>;
 622         clock-frequency = <400000>;
 623 };
 624
 625 &mcspi1 {
 626         status = "okay";
 627         pinctrl-names = "default";
 628         pinctrl-0 = <&mcspi1_pins>;
 629 };
 630
 631 &mcspi2 {
 632         status = "okay";
 633         pinctrl-names = "default";
 634         pinctrl-0 = <&mcspi2_pins>;
 635 };
 636
 637 &uart1 {
 638         status = "okay";
 639         pinctrl-names = "default";
 640         pinctrl-0 = <&uart1_pins>;
 641         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 642                               <&dra7_pmx_core 0x3e0>;
 643 };
 644
 645 &uart2 {
 646         status = "okay";
 647         pinctrl-names = "default";
 648         pinctrl-0 = <&uart2_pins>;
 649 };
 650
 651 &uart3 {
 652         status = "okay";
 653         pinctrl-names = "default";
 654         pinctrl-0 = <&uart3_pins>;
 655 };
 656
 657 &mmc1 {
 658         status = "okay";
 659         vmmc-supply = <&evm_3v3_sd>;
 660         vmmc_aux-supply = <&ldo1_reg>;
 661         bus-width = <4>;
 662         /*
 663          * SDCD signal is not being used here - using the fact that GPIO mode
 664          * is always hardwired.
 665          */
 666         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 667 };
 668
 669 &mmc2 {
 670         status = "okay";
 671         vmmc-supply = <&evm_3v3_sw>;
 672         bus-width = <8>;
 673 };
 674
 675 &cpu0 {
 676         cpu0-supply = <&smps123_reg>;
 677 };
 678
 679 &qspi {
 680         status = "okay";
 681         pinctrl-names = "default";
 682         pinctrl-0 = <&qspi1_pins>;
 683
 684         spi-max-frequency = <48000000>;
 685         m25p80@0 {
 686                 compatible = "s25fl256s1";
 687                 spi-max-frequency = <48000000>;
 688                 reg = <0>;
 689                 spi-tx-bus-width = <1>;
 690                 spi-rx-bus-width = <4>;
 691                 spi-cpol;
 692                 spi-cpha;
 693                 #address-cells = <1>;
 694                 #size-cells = <1>;
 695
 696                 /* MTD partition table.
 697                  * The ROM checks the first four physical blocks
 698                  * for a valid file to boot and the flash here is
 699                  * 64KiB block size.
 700                  */
 701                 partition@0 {
 702                         label = "QSPI.SPL";
 703                         reg = <0x00000000 0x000010000>;
 704                 };
 705                 partition@1 {
 706                         label = "QSPI.SPL.backup1";
 707                         reg = <0x00010000 0x00010000>;
 708                 };
 709                 partition@2 {
 710                         label = "QSPI.SPL.backup2";
 711                         reg = <0x00020000 0x00010000>;
 712                 };
 713                 partition@3 {
 714                         label = "QSPI.SPL.backup3";
 715                         reg = <0x00030000 0x00010000>;
 716                 };
 717                 partition@4 {
 718                         label = "QSPI.u-boot";
 719                         reg = <0x00040000 0x00100000>;
 720                 };
 721                 partition@5 {
 722                         label = "QSPI.u-boot-spl-os";
 723                         reg = <0x00140000 0x00080000>;
 724                 };
 725                 partition@6 {
 726                         label = "QSPI.u-boot-env";
 727                         reg = <0x001c0000 0x00010000>;
 728                 };
 729                 partition@7 {
 730                         label = "QSPI.u-boot-env.backup1";
 731                         reg = <0x001d0000 0x0010000>;
 732                 };
 733                 partition@8 {
 734                         label = "QSPI.kernel";
 735                         reg = <0x001e0000 0x0800000>;
 736                 };
 737                 partition@9 {
 738                         label = "QSPI.file-system";
 739                         reg = <0x009e0000 0x01620000>;
 740                 };
 741         };
 742 };
 743
 744 &omap_dwc3_1 {
 745         extcon = <&extcon_usb1>;
 746 };
 747
 748 &omap_dwc3_2 {
 749         extcon = <&extcon_usb2>;
 750 };
 751
 752 &usb1 {
 753         dr_mode = "peripheral";
 754         pinctrl-names = "default";
 755         pinctrl-0 = <&usb1_pins>;
 756 };
 757
 758 &usb2 {
 759         dr_mode = "host";
 760         pinctrl-names = "default";
 761         pinctrl-0 = <&usb2_pins>;
 762 };
 763
 764 &elm {
 765         status = "okay";
 766 };
 767
 768 &gpmc {
 769         status = "okay";
 770         pinctrl-names = "default";
 771         pinctrl-0 = <&nand_flash_x16>;
 772         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 773         nand@0,0 {
 774                 compatible = "ti,omap2-nand";
 775                 reg = <0 0 4>;          /* device IO registers */
 776                 interrupt-parent = <&gpmc>;
 777                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 778                              <1 IRQ_TYPE_NONE>; /* termcount */
 779                 ti,nand-ecc-opt = "bch8";
 780                 ti,elm-id = <&elm>;
 781                 nand-bus-width = <16>;
 782                 gpmc,device-width = <2>;
 783                 gpmc,sync-clk-ps = <0>;
 784                 gpmc,cs-on-ns = <0>;
 785                 gpmc,cs-rd-off-ns = <80>;
 786                 gpmc,cs-wr-off-ns = <80>;
 787                 gpmc,adv-on-ns = <0>;
 788                 gpmc,adv-rd-off-ns = <60>;
 789                 gpmc,adv-wr-off-ns = <60>;
 790                 gpmc,we-on-ns = <10>;
 791                 gpmc,we-off-ns = <50>;
 792                 gpmc,oe-on-ns = <4>;
 793                 gpmc,oe-off-ns = <40>;
 794                 gpmc,access-ns = <40>;
 795                 gpmc,wr-access-ns = <80>;
 796                 gpmc,rd-cycle-ns = <80>;
 797                 gpmc,wr-cycle-ns = <80>;
 798                 gpmc,bus-turnaround-ns = <0>;
 799                 gpmc,cycle2cycle-delay-ns = <0>;
 800                 gpmc,clk-activation-ns = <0>;
 801                 gpmc,wr-data-mux-bus-ns = <0>;
 802                 /* MTD partition table */
 803                 /* All SPL-* partitions are sized to minimal length
 804                  * which can be independently programmable. For
 805                  * NAND flash this is equal to size of erase-block */
 806                 #address-cells = <1>;
 807                 #size-cells = <1>;
 808                 partition@0 {
 809                         label = "NAND.SPL";
 810                         reg = <0x00000000 0x000020000>;
 811                 };
 812                 partition@1 {
 813                         label = "NAND.SPL.backup1";
 814                         reg = <0x00020000 0x00020000>;
 815                 };
 816                 partition@2 {
 817                         label = "NAND.SPL.backup2";
 818                         reg = <0x00040000 0x00020000>;
 819                 };
 820                 partition@3 {
 821                         label = "NAND.SPL.backup3";
 822                         reg = <0x00060000 0x00020000>;
 823                 };
 824                 partition@4 {
 825                         label = "NAND.u-boot-spl-os";
 826                         reg = <0x00080000 0x00040000>;
 827                 };
 828                 partition@5 {
 829                         label = "NAND.u-boot";
 830                         reg = <0x000c0000 0x00100000>;
 831                 };
 832                 partition@6 {
 833                         label = "NAND.u-boot-env";
 834                         reg = <0x001c0000 0x00020000>;
 835                 };
 836                 partition@7 {
 837                         label = "NAND.u-boot-env.backup1";
 838                         reg = <0x001e0000 0x00020000>;
 839                 };
 840                 partition@8 {
 841                         label = "NAND.kernel";
 842                         reg = <0x00200000 0x00800000>;
 843                 };
 844                 partition@9 {
 845                         label = "NAND.file-system";
 846                         reg = <0x00a00000 0x0f600000>;
 847                 };
 848         };
 849 };
 850
 851 &usb2_phy1 {
 852         phy-supply = <&ldousb_reg>;
 853 };
 854
 855 &usb2_phy2 {
 856         phy-supply = <&ldousb_reg>;
 857 };
 858
 859 &gpio7 {
 860         ti,no-reset-on-init;
 861         ti,no-idle-on-init;
 862 };
 863
 864 &mac {
 865         status = "okay";
 866         pinctrl-names = "default", "sleep";
 867         pinctrl-0 = <&cpsw_default>;
 868         pinctrl-1 = <&cpsw_sleep>;
 869         dual_emac;
 870 };
 871
 872 &cpsw_emac0 {
 873         phy_id = <&davinci_mdio>, <2>;
 874         phy-mode = "rgmii";
 875         dual_emac_res_vlan = <1>;
 876 };
 877
 878 &cpsw_emac1 {
 879         phy_id = <&davinci_mdio>, <3>;
 880         phy-mode = "rgmii";
 881         dual_emac_res_vlan = <2>;
 882 };
 883
 884 &davinci_mdio {
 885         pinctrl-names = "default", "sleep";
 886         pinctrl-0 = <&davinci_mdio_default>;
 887         pinctrl-1 = <&davinci_mdio_sleep>;
 888 };
 889
 890 &dcan1 {
 891         status = "ok";
 892         pinctrl-names = "default", "sleep", "active";
 893         pinctrl-0 = <&dcan1_pins_sleep>;
 894         pinctrl-1 = <&dcan1_pins_sleep>;
 895         pinctrl-2 = <&dcan1_pins_default>;
 896 };
 897
 898 &atl {
 899         pinctrl-names = "default";
 900         pinctrl-0 = <&atl_pins>;
 901
 902         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 903                           <&atl_gfclk_mux>,
 904                           <&dpll_abe_ck>,
 905                           <&dpll_abe_m2x2_ck>,
 906                           <&atl_clkin2_ck>;
 907         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 908         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 909
 910         status = "okay";
 911
 912         atl2 {
 913                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 914                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 915         };
 916 };
 917
 918 &mcasp3 {
 919         #sound-dai-cells = <0>;
 920         pinctrl-names = "default", "sleep";
 921         pinctrl-0 = <&mcasp3_pins>;
 922         pinctrl-1 = <&mcasp3_sleep_pins>;
 923
 924         assigned-clocks = <&mcasp3_ahclkx_mux>;
 925         assigned-clock-parents = <&atl_clkin2_ck>;
 926
 927         status = "okay";
 928
 929         op-mode = <0>;          /* MCASP_IIS_MODE */
 930         tdm-slots = <2>;
 931         /* 4 serializer */
 932         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 933                 1 2 0 0
 934         >;
 935         tx-num-evt = <32>;
 936         rx-num-evt = <32>;
 937 };
 938
 939 &mailbox5 {
 940         status = "okay";
 941         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 942                 status = "okay";
 943         };
 944         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 945                 status = "okay";
 946         };
 947 };
 948
 949 &mailbox6 {
 950         status = "okay";
 951         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 952                 status = "okay";
 953         };
 954         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 955                 status = "okay";
 956         };
 957 };