arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         compatible = "ti,dra7xx";
  22         interrupt-parent = <&crossbar_mpu>;
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_emac0;
  41                 ethernet1 = &cpsw_emac1;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&gic>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         wakeupgen: interrupt-controller@48281000 {
  68                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x48281000 0x1000>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         /*
  76          * The soc node represents the soc top level view. It is used for IPs
  77          * that are not memory mapped in the MPU view or for the MPU itself.
  78          */
  79         soc {
  80                 compatible = "ti,omap-infra";
  81                 mpu {
  82                         compatible = "ti,omap5-mpu";
  83                         ti,hwmods = "mpu";
  84                 };
  85         };
  86
  87         /*
  88          * XXX: Use a flat representation of the SOC interconnect.
  89          * The real OMAP interconnect network is quite complex.
  90          * Since it will not bring real advantage to represent that in DT for
  91          * the moment, just use a fake OCP bus entry to represent the whole bus
  92          * hierarchy.
  93          */
  94         ocp {
  95                 compatible = "ti,dra7-l3-noc", "simple-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99                 ti,hwmods = "l3_main_1", "l3_main_2";
 100                 reg = <0x44000000 0x1000000>,
 101                       <0x45000000 0x1000>;
 102                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 104
 105                 l4_cfg: l4@4a000000 {
 106                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         ranges = <0 0x4a000000 0x22c000>;
 110
 111                         scm: scm@2000 {
 112                                 compatible = "ti,dra7-scm-core", "simple-bus";
 113                                 reg = <0x2000 0x2000>;
 114                                 #address-cells = <1>;
 115                                 #size-cells = <1>;
 116                                 ranges = <0 0x2000 0x2000>;
 117
 118                                 scm_conf: scm_conf@0 {
 119                                         compatible = "syscon";
 120                                         reg = <0x0 0x1400>;
 121                                         #address-cells = <1>;
 122                                         #size-cells = <1>;
 123
 124                                         pbias_regulator: pbias_regulator {
 125                                                 compatible = "ti,pbias-omap";
 126                                                 reg = <0xe00 0x4>;
 127                                                 syscon = <&scm_conf>;
 128                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 129                                                         regulator-name = "pbias_mmc_omap5";
 130                                                         regulator-min-microvolt = <1800000>;
 131                                                         regulator-max-microvolt = <3000000>;
 132                                                 };
 133                                         };
 134
 135                                         scm_conf_clocks: clocks {
 136                                                 #address-cells = <1>;
 137                                                 #size-cells = <0>;
 138                                         };
 139                                 };
 140
 141                                 dra7_pmx_core: pinmux@1400 {
 142                                         compatible = "ti,dra7-padconf",
 143                                                      "pinctrl-single";
 144                                         reg = <0x1400 0x0464>;
 145                                         #address-cells = <1>;
 146                                         #size-cells = <0>;
 147                                         #interrupt-cells = <1>;
 148                                         interrupt-controller;
 149                                         pinctrl-single,register-width = <32>;
 150                                         pinctrl-single,function-mask = <0x3fffffff>;
 151                                 };
 152                         };
 153
 154                         cm_core_aon: cm_core_aon@5000 {
 155                                 compatible = "ti,dra7-cm-core-aon";
 156                                 reg = <0x5000 0x2000>;
 157
 158                                 cm_core_aon_clocks: clocks {
 159                                         #address-cells = <1>;
 160                                         #size-cells = <0>;
 161                                 };
 162
 163                                 cm_core_aon_clockdomains: clockdomains {
 164                                 };
 165                         };
 166
 167                         cm_core: cm_core@8000 {
 168                                 compatible = "ti,dra7-cm-core";
 169                                 reg = <0x8000 0x3000>;
 170
 171                                 cm_core_clocks: clocks {
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                 };
 175
 176                                 cm_core_clockdomains: clockdomains {
 177                                 };
 178                         };
 179                 };
 180
 181                 l4_wkup: l4@4ae00000 {
 182                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 183                         #address-cells = <1>;
 184                         #size-cells = <1>;
 185                         ranges = <0 0x4ae00000 0x3f000>;
 186
 187                         counter32k: counter@4000 {
 188                                 compatible = "ti,omap-counter32k";
 189                                 reg = <0x4000 0x40>;
 190                                 ti,hwmods = "counter_32k";
 191                         };
 192
 193                         prm: prm@6000 {
 194                                 compatible = "ti,dra7-prm";
 195                                 reg = <0x6000 0x3000>;
 196                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 197
 198                                 prm_clocks: clocks {
 199                                         #address-cells = <1>;
 200                                         #size-cells = <0>;
 201                                 };
 202
 203                                 prm_clockdomains: clockdomains {
 204                                 };
 205                         };
 206                 };
 207
 208                 axi@0 {
 209                         compatible = "simple-bus";
 210                         #size-cells = <1>;
 211                         #address-cells = <1>;
 212                         ranges = <0x51000000 0x51000000 0x3000
 213                                   0x0        0x20000000 0x10000000>;
 214                         pcie@51000000 {
 215                                 compatible = "ti,dra7-pcie";
 216                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 217                                 reg-names = "rc_dbics", "ti_conf", "config";
 218                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 219                                 #address-cells = <3>;
 220                                 #size-cells = <2>;
 221                                 device_type = "pci";
 222                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 223                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 224                                 #interrupt-cells = <1>;
 225                                 num-lanes = <1>;
 226                                 ti,hwmods = "pcie1";
 227                                 phys = <&pcie1_phy>;
 228                                 phy-names = "pcie-phy0";
 229                                 interrupt-map-mask = <0 0 0 7>;
 230                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 231                                                 <0 0 0 2 &pcie1_intc 2>,
 232                                                 <0 0 0 3 &pcie1_intc 3>,
 233                                                 <0 0 0 4 &pcie1_intc 4>;
 234                                 pcie1_intc: interrupt-controller {
 235                                         interrupt-controller;
 236                                         #address-cells = <0>;
 237                                         #interrupt-cells = <1>;
 238                                 };
 239                         };
 240                 };
 241
 242                 axi@1 {
 243                         compatible = "simple-bus";
 244                         #size-cells = <1>;
 245                         #address-cells = <1>;
 246                         ranges = <0x51800000 0x51800000 0x3000
 247                                   0x0        0x30000000 0x10000000>;
 248                         status = "disabled";
 249                         pcie@51000000 {
 250                                 compatible = "ti,dra7-pcie";
 251                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 252                                 reg-names = "rc_dbics", "ti_conf", "config";
 253                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 254                                 #address-cells = <3>;
 255                                 #size-cells = <2>;
 256                                 device_type = "pci";
 257                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 258                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 259                                 #interrupt-cells = <1>;
 260                                 num-lanes = <1>;
 261                                 ti,hwmods = "pcie2";
 262                                 phys = <&pcie2_phy>;
 263                                 phy-names = "pcie-phy0";
 264                                 interrupt-map-mask = <0 0 0 7>;
 265                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 266                                                 <0 0 0 2 &pcie2_intc 2>,
 267                                                 <0 0 0 3 &pcie2_intc 3>,
 268                                                 <0 0 0 4 &pcie2_intc 4>;
 269                                 pcie2_intc: interrupt-controller {
 270                                         interrupt-controller;
 271                                         #address-cells = <0>;
 272                                         #interrupt-cells = <1>;
 273                                 };
 274                         };
 275                 };
 276
 277                 bandgap: bandgap@4a0021e0 {
 278                         reg = <0x4a0021e0 0xc
 279                                 0x4a00232c 0xc
 280                                 0x4a002380 0x2c
 281                                 0x4a0023C0 0x3c
 282                                 0x4a002564 0x8
 283                                 0x4a002574 0x50>;
 284                                 compatible = "ti,dra752-bandgap";
 285                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 286                                 #thermal-sensor-cells = <1>;
 287                 };
 288
 289                 dra7_ctrl_core: ctrl_core@4a002000 {
 290                         compatible = "syscon";
 291                         reg = <0x4a002000 0x6d0>;
 292                 };
 293
 294                 dra7_ctrl_general: tisyscon@4a002e00 {
 295                         compatible = "syscon";
 296                         reg = <0x4a002e00 0x7c>;
 297                 };
 298
 299                 sdma: dma-controller@4a056000 {
 300                         compatible = "ti,omap4430-sdma";
 301                         reg = <0x4a056000 0x1000>;
 302                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 306                         #dma-cells = <1>;
 307                         dma-channels = <32>;
 308                         dma-requests = <127>;
 309                 };
 310
 311                 sdma_xbar: dma-router@4a002b78 {
 312                         compatible = "ti,dra7-dma-crossbar";
 313                         reg = <0x4a002b78 0xfc>;
 314                         #dma-cells = <1>;
 315                         dma-requests = <205>;
 316                         ti,dma-safe-map = <0>;
 317                         dma-masters = <&sdma>;
 318                 };
 319
 320                 gpio1: gpio@4ae10000 {
 321                         compatible = "ti,omap4-gpio";
 322                         reg = <0x4ae10000 0x200>;
 323                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 324                         ti,hwmods = "gpio1";
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                         interrupt-controller;
 328                         #interrupt-cells = <2>;
 329                 };
 330
 331                 gpio2: gpio@48055000 {
 332                         compatible = "ti,omap4-gpio";
 333                         reg = <0x48055000 0x200>;
 334                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 335                         ti,hwmods = "gpio2";
 336                         gpio-controller;
 337                         #gpio-cells = <2>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                 };
 341
 342                 gpio3: gpio@48057000 {
 343                         compatible = "ti,omap4-gpio";
 344                         reg = <0x48057000 0x200>;
 345                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 346                         ti,hwmods = "gpio3";
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349                         interrupt-controller;
 350                         #interrupt-cells = <2>;
 351                 };
 352
 353                 gpio4: gpio@48059000 {
 354                         compatible = "ti,omap4-gpio";
 355                         reg = <0x48059000 0x200>;
 356                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 357                         ti,hwmods = "gpio4";
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360                         interrupt-controller;
 361                         #interrupt-cells = <2>;
 362                 };
 363
 364                 gpio5: gpio@4805b000 {
 365                         compatible = "ti,omap4-gpio";
 366                         reg = <0x4805b000 0x200>;
 367                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "gpio5";
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         interrupt-controller;
 372                         #interrupt-cells = <2>;
 373                 };
 374
 375                 gpio6: gpio@4805d000 {
 376                         compatible = "ti,omap4-gpio";
 377                         reg = <0x4805d000 0x200>;
 378                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "gpio6";
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385
 386                 gpio7: gpio@48051000 {
 387                         compatible = "ti,omap4-gpio";
 388                         reg = <0x48051000 0x200>;
 389                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 390                         ti,hwmods = "gpio7";
 391                         gpio-controller;
 392                         #gpio-cells = <2>;
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 gpio8: gpio@48053000 {
 398                         compatible = "ti,omap4-gpio";
 399                         reg = <0x48053000 0x200>;
 400                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 401                         ti,hwmods = "gpio8";
 402                         gpio-controller;
 403                         #gpio-cells = <2>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                 };
 407
 408                 uart1: serial@4806a000 {
 409                         compatible = "ti,omap4-uart";
 410                         reg = <0x4806a000 0x100>;
 411                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 412                         ti,hwmods = "uart1";
 413                         clock-frequency = <48000000>;
 414                         status = "disabled";
 415                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 416                         dma-names = "tx", "rx";
 417                 };
 418
 419                 uart2: serial@4806c000 {
 420                         compatible = "ti,omap4-uart";
 421                         reg = <0x4806c000 0x100>;
 422                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 423                         ti,hwmods = "uart2";
 424                         clock-frequency = <48000000>;
 425                         status = "disabled";
 426                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 427                         dma-names = "tx", "rx";
 428                 };
 429
 430                 uart3: serial@48020000 {
 431                         compatible = "ti,omap4-uart";
 432                         reg = <0x48020000 0x100>;
 433                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 434                         ti,hwmods = "uart3";
 435                         clock-frequency = <48000000>;
 436                         status = "disabled";
 437                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 438                         dma-names = "tx", "rx";
 439                 };
 440
 441                 uart4: serial@4806e000 {
 442                         compatible = "ti,omap4-uart";
 443                         reg = <0x4806e000 0x100>;
 444                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 445                         ti,hwmods = "uart4";
 446                         clock-frequency = <48000000>;
 447                         status = "disabled";
 448                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 449                         dma-names = "tx", "rx";
 450                 };
 451
 452                 uart5: serial@48066000 {
 453                         compatible = "ti,omap4-uart";
 454                         reg = <0x48066000 0x100>;
 455                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 456                         ti,hwmods = "uart5";
 457                         clock-frequency = <48000000>;
 458                         status = "disabled";
 459                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 460                         dma-names = "tx", "rx";
 461                 };
 462
 463                 uart6: serial@48068000 {
 464                         compatible = "ti,omap4-uart";
 465                         reg = <0x48068000 0x100>;
 466                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 467                         ti,hwmods = "uart6";
 468                         clock-frequency = <48000000>;
 469                         status = "disabled";
 470                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 471                         dma-names = "tx", "rx";
 472                 };
 473
 474                 uart7: serial@48420000 {
 475                         compatible = "ti,omap4-uart";
 476                         reg = <0x48420000 0x100>;
 477                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 478                         ti,hwmods = "uart7";
 479                         clock-frequency = <48000000>;
 480                         status = "disabled";
 481                 };
 482
 483                 uart8: serial@48422000 {
 484                         compatible = "ti,omap4-uart";
 485                         reg = <0x48422000 0x100>;
 486                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 487                         ti,hwmods = "uart8";
 488                         clock-frequency = <48000000>;
 489                         status = "disabled";
 490                 };
 491
 492                 uart9: serial@48424000 {
 493                         compatible = "ti,omap4-uart";
 494                         reg = <0x48424000 0x100>;
 495                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 496                         ti,hwmods = "uart9";
 497                         clock-frequency = <48000000>;
 498                         status = "disabled";
 499                 };
 500
 501                 uart10: serial@4ae2b000 {
 502                         compatible = "ti,omap4-uart";
 503                         reg = <0x4ae2b000 0x100>;
 504                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 505                         ti,hwmods = "uart10";
 506                         clock-frequency = <48000000>;
 507                         status = "disabled";
 508                 };
 509
 510                 mailbox1: mailbox@4a0f4000 {
 511                         compatible = "ti,omap4-mailbox";
 512                         reg = <0x4a0f4000 0x200>;
 513                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 515                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 516                         ti,hwmods = "mailbox1";
 517                         #mbox-cells = <1>;
 518                         ti,mbox-num-users = <3>;
 519                         ti,mbox-num-fifos = <8>;
 520                         status = "disabled";
 521                 };
 522
 523                 mailbox2: mailbox@4883a000 {
 524                         compatible = "ti,omap4-mailbox";
 525                         reg = <0x4883a000 0x200>;
 526                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 527                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 529                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 530                         ti,hwmods = "mailbox2";
 531                         #mbox-cells = <1>;
 532                         ti,mbox-num-users = <4>;
 533                         ti,mbox-num-fifos = <12>;
 534                         status = "disabled";
 535                 };
 536
 537                 mailbox3: mailbox@4883c000 {
 538                         compatible = "ti,omap4-mailbox";
 539                         reg = <0x4883c000 0x200>;
 540                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 542                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 544                         ti,hwmods = "mailbox3";
 545                         #mbox-cells = <1>;
 546                         ti,mbox-num-users = <4>;
 547                         ti,mbox-num-fifos = <12>;
 548                         status = "disabled";
 549                 };
 550
 551                 mailbox4: mailbox@4883e000 {
 552                         compatible = "ti,omap4-mailbox";
 553                         reg = <0x4883e000 0x200>;
 554                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 556                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 558                         ti,hwmods = "mailbox4";
 559                         #mbox-cells = <1>;
 560                         ti,mbox-num-users = <4>;
 561                         ti,mbox-num-fifos = <12>;
 562                         status = "disabled";
 563                 };
 564
 565                 mailbox5: mailbox@48840000 {
 566                         compatible = "ti,omap4-mailbox";
 567                         reg = <0x48840000 0x200>;
 568                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 569                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 570                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 571                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 572                         ti,hwmods = "mailbox5";
 573                         #mbox-cells = <1>;
 574                         ti,mbox-num-users = <4>;
 575                         ti,mbox-num-fifos = <12>;
 576                         status = "disabled";
 577                 };
 578
 579                 mailbox6: mailbox@48842000 {
 580                         compatible = "ti,omap4-mailbox";
 581                         reg = <0x48842000 0x200>;
 582                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 586                         ti,hwmods = "mailbox6";
 587                         #mbox-cells = <1>;
 588                         ti,mbox-num-users = <4>;
 589                         ti,mbox-num-fifos = <12>;
 590                         status = "disabled";
 591                 };
 592
 593                 mailbox7: mailbox@48844000 {
 594                         compatible = "ti,omap4-mailbox";
 595                         reg = <0x48844000 0x200>;
 596                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 600                         ti,hwmods = "mailbox7";
 601                         #mbox-cells = <1>;
 602                         ti,mbox-num-users = <4>;
 603                         ti,mbox-num-fifos = <12>;
 604                         status = "disabled";
 605                 };
 606
 607                 mailbox8: mailbox@48846000 {
 608                         compatible = "ti,omap4-mailbox";
 609                         reg = <0x48846000 0x200>;
 610                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 612                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 613                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 614                         ti,hwmods = "mailbox8";
 615                         #mbox-cells = <1>;
 616                         ti,mbox-num-users = <4>;
 617                         ti,mbox-num-fifos = <12>;
 618                         status = "disabled";
 619                 };
 620
 621                 mailbox9: mailbox@4885e000 {
 622                         compatible = "ti,omap4-mailbox";
 623                         reg = <0x4885e000 0x200>;
 624                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 625                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 627                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 628                         ti,hwmods = "mailbox9";
 629                         #mbox-cells = <1>;
 630                         ti,mbox-num-users = <4>;
 631                         ti,mbox-num-fifos = <12>;
 632                         status = "disabled";
 633                 };
 634
 635                 mailbox10: mailbox@48860000 {
 636                         compatible = "ti,omap4-mailbox";
 637                         reg = <0x48860000 0x200>;
 638                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 639                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 640                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 642                         ti,hwmods = "mailbox10";
 643                         #mbox-cells = <1>;
 644                         ti,mbox-num-users = <4>;
 645                         ti,mbox-num-fifos = <12>;
 646                         status = "disabled";
 647                 };
 648
 649                 mailbox11: mailbox@48862000 {
 650                         compatible = "ti,omap4-mailbox";
 651                         reg = <0x48862000 0x200>;
 652                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 653                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 654                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 655                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 656                         ti,hwmods = "mailbox11";
 657                         #mbox-cells = <1>;
 658                         ti,mbox-num-users = <4>;
 659                         ti,mbox-num-fifos = <12>;
 660                         status = "disabled";
 661                 };
 662
 663                 mailbox12: mailbox@48864000 {
 664                         compatible = "ti,omap4-mailbox";
 665                         reg = <0x48864000 0x200>;
 666                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 670                         ti,hwmods = "mailbox12";
 671                         #mbox-cells = <1>;
 672                         ti,mbox-num-users = <4>;
 673                         ti,mbox-num-fifos = <12>;
 674                         status = "disabled";
 675                 };
 676
 677                 mailbox13: mailbox@48802000 {
 678                         compatible = "ti,omap4-mailbox";
 679                         reg = <0x48802000 0x200>;
 680                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 684                         ti,hwmods = "mailbox13";
 685                         #mbox-cells = <1>;
 686                         ti,mbox-num-users = <4>;
 687                         ti,mbox-num-fifos = <12>;
 688                         status = "disabled";
 689                 };
 690
 691                 timer1: timer@4ae18000 {
 692                         compatible = "ti,omap5430-timer";
 693                         reg = <0x4ae18000 0x80>;
 694                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "timer1";
 696                         ti,timer-alwon;
 697                 };
 698
 699                 timer2: timer@48032000 {
 700                         compatible = "ti,omap5430-timer";
 701                         reg = <0x48032000 0x80>;
 702                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 703                         ti,hwmods = "timer2";
 704                 };
 705
 706                 timer3: timer@48034000 {
 707                         compatible = "ti,omap5430-timer";
 708                         reg = <0x48034000 0x80>;
 709                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "timer3";
 711                 };
 712
 713                 timer4: timer@48036000 {
 714                         compatible = "ti,omap5430-timer";
 715                         reg = <0x48036000 0x80>;
 716                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 717                         ti,hwmods = "timer4";
 718                 };
 719
 720                 timer5: timer@48820000 {
 721                         compatible = "ti,omap5430-timer";
 722                         reg = <0x48820000 0x80>;
 723                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 724                         ti,hwmods = "timer5";
 725                 };
 726
 727                 timer6: timer@48822000 {
 728                         compatible = "ti,omap5430-timer";
 729                         reg = <0x48822000 0x80>;
 730                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 731                         ti,hwmods = "timer6";
 732                 };
 733
 734                 timer7: timer@48824000 {
 735                         compatible = "ti,omap5430-timer";
 736                         reg = <0x48824000 0x80>;
 737                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 738                         ti,hwmods = "timer7";
 739                 };
 740
 741                 timer8: timer@48826000 {
 742                         compatible = "ti,omap5430-timer";
 743                         reg = <0x48826000 0x80>;
 744                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 745                         ti,hwmods = "timer8";
 746                 };
 747
 748                 timer9: timer@4803e000 {
 749                         compatible = "ti,omap5430-timer";
 750                         reg = <0x4803e000 0x80>;
 751                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 752                         ti,hwmods = "timer9";
 753                 };
 754
 755                 timer10: timer@48086000 {
 756                         compatible = "ti,omap5430-timer";
 757                         reg = <0x48086000 0x80>;
 758                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 759                         ti,hwmods = "timer10";
 760                 };
 761
 762                 timer11: timer@48088000 {
 763                         compatible = "ti,omap5430-timer";
 764                         reg = <0x48088000 0x80>;
 765                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 766                         ti,hwmods = "timer11";
 767                 };
 768
 769                 timer13: timer@48828000 {
 770                         compatible = "ti,omap5430-timer";
 771                         reg = <0x48828000 0x80>;
 772                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 773                         ti,hwmods = "timer13";
 774                         status = "disabled";
 775                 };
 776
 777                 timer14: timer@4882a000 {
 778                         compatible = "ti,omap5430-timer";
 779                         reg = <0x4882a000 0x80>;
 780                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 781                         ti,hwmods = "timer14";
 782                         status = "disabled";
 783                 };
 784
 785                 timer15: timer@4882c000 {
 786                         compatible = "ti,omap5430-timer";
 787                         reg = <0x4882c000 0x80>;
 788                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 789                         ti,hwmods = "timer15";
 790                         status = "disabled";
 791                 };
 792
 793                 timer16: timer@4882e000 {
 794                         compatible = "ti,omap5430-timer";
 795                         reg = <0x4882e000 0x80>;
 796                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 797                         ti,hwmods = "timer16";
 798                         status = "disabled";
 799                 };
 800
 801                 wdt2: wdt@4ae14000 {
 802                         compatible = "ti,omap3-wdt";
 803                         reg = <0x4ae14000 0x80>;
 804                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 805                         ti,hwmods = "wd_timer2";
 806                 };
 807
 808                 hwspinlock: spinlock@4a0f6000 {
 809                         compatible = "ti,omap4-hwspinlock";
 810                         reg = <0x4a0f6000 0x1000>;
 811                         ti,hwmods = "spinlock";
 812                         #hwlock-cells = <1>;
 813                 };
 814
 815                 dmm@4e000000 {
 816                         compatible = "ti,omap5-dmm";
 817                         reg = <0x4e000000 0x800>;
 818                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 819                         ti,hwmods = "dmm";
 820                 };
 821
 822                 i2c1: i2c@48070000 {
 823                         compatible = "ti,omap4-i2c";
 824                         reg = <0x48070000 0x100>;
 825                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828                         ti,hwmods = "i2c1";
 829                         status = "disabled";
 830                 };
 831
 832                 i2c2: i2c@48072000 {
 833                         compatible = "ti,omap4-i2c";
 834                         reg = <0x48072000 0x100>;
 835                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 836                         #address-cells = <1>;
 837                         #size-cells = <0>;
 838                         ti,hwmods = "i2c2";
 839                         status = "disabled";
 840                 };
 841
 842                 i2c3: i2c@48060000 {
 843                         compatible = "ti,omap4-i2c";
 844                         reg = <0x48060000 0x100>;
 845                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 846                         #address-cells = <1>;
 847                         #size-cells = <0>;
 848                         ti,hwmods = "i2c3";
 849                         status = "disabled";
 850                 };
 851
 852                 i2c4: i2c@4807a000 {
 853                         compatible = "ti,omap4-i2c";
 854                         reg = <0x4807a000 0x100>;
 855                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         ti,hwmods = "i2c4";
 859                         status = "disabled";
 860                 };
 861
 862                 i2c5: i2c@4807c000 {
 863                         compatible = "ti,omap4-i2c";
 864                         reg = <0x4807c000 0x100>;
 865                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 866                         #address-cells = <1>;
 867                         #size-cells = <0>;
 868                         ti,hwmods = "i2c5";
 869                         status = "disabled";
 870                 };
 871
 872                 mmc1: mmc@4809c000 {
 873                         compatible = "ti,omap4-hsmmc";
 874                         reg = <0x4809c000 0x400>;
 875                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 876                         ti,hwmods = "mmc1";
 877                         ti,dual-volt;
 878                         ti,needs-special-reset;
 879                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
 880                         dma-names = "tx", "rx";
 881                         status = "disabled";
 882                         pbias-supply = <&pbias_mmc_reg>;
 883                 };
 884
 885                 mmc2: mmc@480b4000 {
 886                         compatible = "ti,omap4-hsmmc";
 887                         reg = <0x480b4000 0x400>;
 888                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 889                         ti,hwmods = "mmc2";
 890                         ti,needs-special-reset;
 891                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
 892                         dma-names = "tx", "rx";
 893                         status = "disabled";
 894                 };
 895
 896                 mmc3: mmc@480ad000 {
 897                         compatible = "ti,omap4-hsmmc";
 898                         reg = <0x480ad000 0x400>;
 899                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 900                         ti,hwmods = "mmc3";
 901                         ti,needs-special-reset;
 902                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
 903                         dma-names = "tx", "rx";
 904                         status = "disabled";
 905                 };
 906
 907                 mmc4: mmc@480d1000 {
 908                         compatible = "ti,omap4-hsmmc";
 909                         reg = <0x480d1000 0x400>;
 910                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 911                         ti,hwmods = "mmc4";
 912                         ti,needs-special-reset;
 913                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
 914                         dma-names = "tx", "rx";
 915                         status = "disabled";
 916                 };
 917
 918                 abb_mpu: regulator-abb-mpu {
 919                         compatible = "ti,abb-v3";
 920                         regulator-name = "abb_mpu";
 921                         #address-cells = <0>;
 922                         #size-cells = <0>;
 923                         clocks = <&sys_clkin1>;
 924                         ti,settling-time = <50>;
 925                         ti,clock-cycles = <16>;
 926
 927                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 928                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 929                               <0x4ae0c158 0x4>;
 930                         reg-names = "setup-address", "control-address",
 931                                     "int-address", "efuse-address",
 932                                     "ldo-address";
 933                         ti,tranxdone-status-mask = <0x80>;
 934                         /* LDOVBBMPU_FBB_MUX_CTRL */
 935                         ti,ldovbb-override-mask = <0x400>;
 936                         /* LDOVBBMPU_FBB_VSET_OUT */
 937                         ti,ldovbb-vset-mask = <0x1F>;
 938
 939                         /*
 940                          * NOTE: only FBB mode used but actual vset will
 941                          * determine final biasing
 942                          */
 943                         ti,abb_info = <
 944                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 945                         1060000         0       0x0     0 0x02000000 0x01F00000
 946                         1160000         0       0x4     0 0x02000000 0x01F00000
 947                         1210000         0       0x8     0 0x02000000 0x01F00000
 948                         >;
 949                 };
 950
 951                 abb_ivahd: regulator-abb-ivahd {
 952                         compatible = "ti,abb-v3";
 953                         regulator-name = "abb_ivahd";
 954                         #address-cells = <0>;
 955                         #size-cells = <0>;
 956                         clocks = <&sys_clkin1>;
 957                         ti,settling-time = <50>;
 958                         ti,clock-cycles = <16>;
 959
 960                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 961                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 962                               <0x4a002470 0x4>;
 963                         reg-names = "setup-address", "control-address",
 964                                     "int-address", "efuse-address",
 965                                     "ldo-address";
 966                         ti,tranxdone-status-mask = <0x40000000>;
 967                         /* LDOVBBIVA_FBB_MUX_CTRL */
 968                         ti,ldovbb-override-mask = <0x400>;
 969                         /* LDOVBBIVA_FBB_VSET_OUT */
 970                         ti,ldovbb-vset-mask = <0x1F>;
 971
 972                         /*
 973                          * NOTE: only FBB mode used but actual vset will
 974                          * determine final biasing
 975                          */
 976                         ti,abb_info = <
 977                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 978                         1055000         0       0x0     0 0x02000000 0x01F00000
 979                         1150000         0       0x4     0 0x02000000 0x01F00000
 980                         1250000         0       0x8     0 0x02000000 0x01F00000
 981                         >;
 982                 };
 983
 984                 abb_dspeve: regulator-abb-dspeve {
 985                         compatible = "ti,abb-v3";
 986                         regulator-name = "abb_dspeve";
 987                         #address-cells = <0>;
 988                         #size-cells = <0>;
 989                         clocks = <&sys_clkin1>;
 990                         ti,settling-time = <50>;
 991                         ti,clock-cycles = <16>;
 992
 993                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 994                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 995                               <0x4a00246c 0x4>;
 996                         reg-names = "setup-address", "control-address",
 997                                     "int-address", "efuse-address",
 998                                     "ldo-address";
 999                         ti,tranxdone-status-mask = <0x20000000>;
1000                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1001                         ti,ldovbb-override-mask = <0x400>;
1002                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1003                         ti,ldovbb-vset-mask = <0x1F>;
1004
1005                         /*
1006                          * NOTE: only FBB mode used but actual vset will
1007                          * determine final biasing
1008                          */
1009                         ti,abb_info = <
1010                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1011                         1055000         0       0x0     0 0x02000000 0x01F00000
1012                         1150000         0       0x4     0 0x02000000 0x01F00000
1013                         1250000         0       0x8     0 0x02000000 0x01F00000
1014                         >;
1015                 };
1016
1017                 abb_gpu: regulator-abb-gpu {
1018                         compatible = "ti,abb-v3";
1019                         regulator-name = "abb_gpu";
1020                         #address-cells = <0>;
1021                         #size-cells = <0>;
1022                         clocks = <&sys_clkin1>;
1023                         ti,settling-time = <50>;
1024                         ti,clock-cycles = <16>;
1025
1026                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1027                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1028                               <0x4ae0c154 0x4>;
1029                         reg-names = "setup-address", "control-address",
1030                                     "int-address", "efuse-address",
1031                                     "ldo-address";
1032                         ti,tranxdone-status-mask = <0x10000000>;
1033                         /* LDOVBBGPU_FBB_MUX_CTRL */
1034                         ti,ldovbb-override-mask = <0x400>;
1035                         /* LDOVBBGPU_FBB_VSET_OUT */
1036                         ti,ldovbb-vset-mask = <0x1F>;
1037
1038                         /*
1039                          * NOTE: only FBB mode used but actual vset will
1040                          * determine final biasing
1041                          */
1042                         ti,abb_info = <
1043                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1044                         1090000         0       0x0     0 0x02000000 0x01F00000
1045                         1210000         0       0x4     0 0x02000000 0x01F00000
1046                         1280000         0       0x8     0 0x02000000 0x01F00000
1047                         >;
1048                 };
1049
1050                 mcspi1: spi@48098000 {
1051                         compatible = "ti,omap4-mcspi";
1052                         reg = <0x48098000 0x200>;
1053                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1054                         #address-cells = <1>;
1055                         #size-cells = <0>;
1056                         ti,hwmods = "mcspi1";
1057                         ti,spi-num-cs = <4>;
1058                         dmas = <&sdma_xbar 35>,
1059                                <&sdma_xbar 36>,
1060                                <&sdma_xbar 37>,
1061                                <&sdma_xbar 38>,
1062                                <&sdma_xbar 39>,
1063                                <&sdma_xbar 40>,
1064                                <&sdma_xbar 41>,
1065                                <&sdma_xbar 42>;
1066                         dma-names = "tx0", "rx0", "tx1", "rx1",
1067                                     "tx2", "rx2", "tx3", "rx3";
1068                         status = "disabled";
1069                 };
1070
1071                 mcspi2: spi@4809a000 {
1072                         compatible = "ti,omap4-mcspi";
1073                         reg = <0x4809a000 0x200>;
1074                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1075                         #address-cells = <1>;
1076                         #size-cells = <0>;
1077                         ti,hwmods = "mcspi2";
1078                         ti,spi-num-cs = <2>;
1079                         dmas = <&sdma_xbar 43>,
1080                                <&sdma_xbar 44>,
1081                                <&sdma_xbar 45>,
1082                                <&sdma_xbar 46>;
1083                         dma-names = "tx0", "rx0", "tx1", "rx1";
1084                         status = "disabled";
1085                 };
1086
1087                 mcspi3: spi@480b8000 {
1088                         compatible = "ti,omap4-mcspi";
1089                         reg = <0x480b8000 0x200>;
1090                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1091                         #address-cells = <1>;
1092                         #size-cells = <0>;
1093                         ti,hwmods = "mcspi3";
1094                         ti,spi-num-cs = <2>;
1095                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1096                         dma-names = "tx0", "rx0";
1097                         status = "disabled";
1098                 };
1099
1100                 mcspi4: spi@480ba000 {
1101                         compatible = "ti,omap4-mcspi";
1102                         reg = <0x480ba000 0x200>;
1103                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1104                         #address-cells = <1>;
1105                         #size-cells = <0>;
1106                         ti,hwmods = "mcspi4";
1107                         ti,spi-num-cs = <1>;
1108                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1109                         dma-names = "tx0", "rx0";
1110                         status = "disabled";
1111                 };
1112
1113                 qspi: qspi@4b300000 {
1114                         compatible = "ti,dra7xxx-qspi";
1115                         reg = <0x4b300000 0x100>;
1116                         reg-names = "qspi_base";
1117                         #address-cells = <1>;
1118                         #size-cells = <0>;
1119                         ti,hwmods = "qspi";
1120                         clocks = <&qspi_gfclk_div>;
1121                         clock-names = "fck";
1122                         num-cs = <4>;
1123                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1124                         status = "disabled";
1125                 };
1126
1127                 omap_control_sata: control-phy@4a002374 {
1128                         compatible = "ti,control-phy-pipe3";
1129                         reg = <0x4a002374 0x4>;
1130                         reg-names = "power";
1131                         clocks = <&sys_clkin1>;
1132                         clock-names = "sysclk";
1133                 };
1134
1135                 /* OCP2SCP3 */
1136                 ocp2scp@4a090000 {
1137                         compatible = "ti,omap-ocp2scp";
1138                         #address-cells = <1>;
1139                         #size-cells = <1>;
1140                         ranges;
1141                         reg = <0x4a090000 0x20>;
1142                         ti,hwmods = "ocp2scp3";
1143                         sata_phy: phy@4A096000 {
1144                                 compatible = "ti,phy-pipe3-sata";
1145                                 reg = <0x4A096000 0x80>, /* phy_rx */
1146                                       <0x4A096400 0x64>, /* phy_tx */
1147                                       <0x4A096800 0x40>; /* pll_ctrl */
1148                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1149                                 ctrl-module = <&omap_control_sata>;
1150                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1151                                 clock-names = "sysclk", "refclk";
1152                                 #phy-cells = <0>;
1153                         };
1154
1155                         pcie1_phy: pciephy@4a094000 {
1156                                 compatible = "ti,phy-pipe3-pcie";
1157                                 reg = <0x4a094000 0x80>, /* phy_rx */
1158                                       <0x4a094400 0x64>; /* phy_tx */
1159                                 reg-names = "phy_rx", "phy_tx";
1160                                 ctrl-module = <&omap_control_pcie1phy>;
1161                                 clocks = <&dpll_pcie_ref_ck>,
1162                                          <&dpll_pcie_ref_m2ldo_ck>,
1163                                          <&optfclk_pciephy1_32khz>,
1164                                          <&optfclk_pciephy1_clk>,
1165                                          <&optfclk_pciephy1_div_clk>,
1166                                          <&optfclk_pciephy_div>;
1167                                 clock-names = "dpll_ref", "dpll_ref_m2",
1168                                               "wkupclk", "refclk",
1169                                               "div-clk", "phy-div";
1170                                 #phy-cells = <0>;
1171                         };
1172
1173                         pcie2_phy: pciephy@4a095000 {
1174                                 compatible = "ti,phy-pipe3-pcie";
1175                                 reg = <0x4a095000 0x80>, /* phy_rx */
1176                                       <0x4a095400 0x64>; /* phy_tx */
1177                                 reg-names = "phy_rx", "phy_tx";
1178                                 ctrl-module = <&omap_control_pcie2phy>;
1179                                 clocks = <&dpll_pcie_ref_ck>,
1180                                          <&dpll_pcie_ref_m2ldo_ck>,
1181                                          <&optfclk_pciephy2_32khz>,
1182                                          <&optfclk_pciephy2_clk>,
1183                                          <&optfclk_pciephy2_div_clk>,
1184                                          <&optfclk_pciephy_div>;
1185                                 clock-names = "dpll_ref", "dpll_ref_m2",
1186                                               "wkupclk", "refclk",
1187                                               "div-clk", "phy-div";
1188                                 #phy-cells = <0>;
1189                                 status = "disabled";
1190                         };
1191                 };
1192
1193                 sata: sata@4a141100 {
1194                         compatible = "snps,dwc-ahci";
1195                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1196                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1197                         phys = <&sata_phy>;
1198                         phy-names = "sata-phy";
1199                         clocks = <&sata_ref_clk>;
1200                         ti,hwmods = "sata";
1201                 };
1202
1203                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1204                         compatible = "ti,control-phy-pcie";
1205                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1206                         reg-names = "power", "control_sma", "pcie_pcs";
1207                         clocks = <&sys_clkin1>;
1208                         clock-names = "sysclk";
1209                 };
1210
1211                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1212                         compatible = "ti,control-phy-pcie";
1213                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1214                         reg-names = "power", "control_sma", "pcie_pcs";
1215                         clocks = <&sys_clkin1>;
1216                         clock-names = "sysclk";
1217                         status = "disabled";
1218                 };
1219
1220                 rtc: rtc@48838000 {
1221                         compatible = "ti,am3352-rtc";
1222                         reg = <0x48838000 0x100>;
1223                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1225                         ti,hwmods = "rtcss";
1226                         clocks = <&sys_32k_ck>;
1227                 };
1228
1229                 omap_control_usb2phy1: control-phy@4a002300 {
1230                         compatible = "ti,control-phy-usb2";
1231                         reg = <0x4a002300 0x4>;
1232                         reg-names = "power";
1233                 };
1234
1235                 omap_control_usb3phy1: control-phy@4a002370 {
1236                         compatible = "ti,control-phy-pipe3";
1237                         reg = <0x4a002370 0x4>;
1238                         reg-names = "power";
1239                 };
1240
1241                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1242                         compatible = "ti,control-phy-usb2-dra7";
1243                         reg = <0x4a002e74 0x4>;
1244                         reg-names = "power";
1245                 };
1246
1247                 /* OCP2SCP1 */
1248                 ocp2scp@4a080000 {
1249                         compatible = "ti,omap-ocp2scp";
1250                         #address-cells = <1>;
1251                         #size-cells = <1>;
1252                         ranges;
1253                         reg = <0x4a080000 0x20>;
1254                         ti,hwmods = "ocp2scp1";
1255
1256                         usb2_phy1: phy@4a084000 {
1257                                 compatible = "ti,omap-usb2";
1258                                 reg = <0x4a084000 0x400>;
1259                                 ctrl-module = <&omap_control_usb2phy1>;
1260                                 clocks = <&usb_phy1_always_on_clk32k>,
1261                                          <&usb_otg_ss1_refclk960m>;
1262                                 clock-names =   "wkupclk",
1263                                                 "refclk";
1264                                 #phy-cells = <0>;
1265                         };
1266
1267                         usb2_phy2: phy@4a085000 {
1268                                 compatible = "ti,omap-usb2";
1269                                 reg = <0x4a085000 0x400>;
1270                                 ctrl-module = <&omap_control_usb2phy2>;
1271                                 clocks = <&usb_phy2_always_on_clk32k>,
1272                                          <&usb_otg_ss2_refclk960m>;
1273                                 clock-names =   "wkupclk",
1274                                                 "refclk";
1275                                 #phy-cells = <0>;
1276                         };
1277
1278                         usb3_phy1: phy@4a084400 {
1279                                 compatible = "ti,omap-usb3";
1280                                 reg = <0x4a084400 0x80>,
1281                                       <0x4a084800 0x64>,
1282                                       <0x4a084c00 0x40>;
1283                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1284                                 ctrl-module = <&omap_control_usb3phy1>;
1285                                 clocks = <&usb_phy3_always_on_clk32k>,
1286                                          <&sys_clkin1>,
1287                                          <&usb_otg_ss1_refclk960m>;
1288                                 clock-names =   "wkupclk",
1289                                                 "sysclk",
1290                                                 "refclk";
1291                                 #phy-cells = <0>;
1292                         };
1293                 };
1294
1295                 omap_dwc3_1: omap_dwc3_1@48880000 {
1296                         compatible = "ti,dwc3";
1297                         ti,hwmods = "usb_otg_ss1";
1298                         reg = <0x48880000 0x10000>;
1299                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1300                         #address-cells = <1>;
1301                         #size-cells = <1>;
1302                         utmi-mode = <2>;
1303                         ranges;
1304                         usb1: usb@48890000 {
1305                                 compatible = "snps,dwc3";
1306                                 reg = <0x48890000 0x17000>;
1307                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1308                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1309                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1310                                 interrupt-names = "peripheral",
1311                                                   "host",
1312                                                   "otg";
1313                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1314                                 phy-names = "usb2-phy", "usb3-phy";
1315                                 tx-fifo-resize;
1316                                 maximum-speed = "super-speed";
1317                                 dr_mode = "otg";
1318                                 snps,dis_u3_susphy_quirk;
1319                                 snps,dis_u2_susphy_quirk;
1320                         };
1321                 };
1322
1323                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1324                         compatible = "ti,dwc3";
1325                         ti,hwmods = "usb_otg_ss2";
1326                         reg = <0x488c0000 0x10000>;
1327                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1328                         #address-cells = <1>;
1329                         #size-cells = <1>;
1330                         utmi-mode = <2>;
1331                         ranges;
1332                         usb2: usb@488d0000 {
1333                                 compatible = "snps,dwc3";
1334                                 reg = <0x488d0000 0x17000>;
1335                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1336                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1337                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1338                                 interrupt-names = "peripheral",
1339                                                   "host",
1340                                                   "otg";
1341                                 phys = <&usb2_phy2>;
1342                                 phy-names = "usb2-phy";
1343                                 tx-fifo-resize;
1344                                 maximum-speed = "high-speed";
1345                                 dr_mode = "otg";
1346                                 snps,dis_u3_susphy_quirk;
1347                                 snps,dis_u2_susphy_quirk;
1348                         };
1349                 };
1350
1351                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1352                 omap_dwc3_3: omap_dwc3_3@48900000 {
1353                         compatible = "ti,dwc3";
1354                         ti,hwmods = "usb_otg_ss3";
1355                         reg = <0x48900000 0x10000>;
1356                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1357                         #address-cells = <1>;
1358                         #size-cells = <1>;
1359                         utmi-mode = <2>;
1360                         ranges;
1361                         status = "disabled";
1362                         usb3: usb@48910000 {
1363                                 compatible = "snps,dwc3";
1364                                 reg = <0x48910000 0x17000>;
1365                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1366                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1367                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1368                                 interrupt-names = "peripheral",
1369                                                   "host",
1370                                                   "otg";
1371                                 tx-fifo-resize;
1372                                 maximum-speed = "high-speed";
1373                                 dr_mode = "otg";
1374                                 snps,dis_u3_susphy_quirk;
1375                                 snps,dis_u2_susphy_quirk;
1376                         };
1377                 };
1378
1379                 elm: elm@48078000 {
1380                         compatible = "ti,am3352-elm";
1381                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1382                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1383                         ti,hwmods = "elm";
1384                         status = "disabled";
1385                 };
1386
1387                 gpmc: gpmc@50000000 {
1388                         compatible = "ti,am3352-gpmc";
1389                         ti,hwmods = "gpmc";
1390                         reg = <0x50000000 0x37c>;      /* device IO registers */
1391                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1392                         gpmc,num-cs = <8>;
1393                         gpmc,num-waitpins = <2>;
1394                         #address-cells = <2>;
1395                         #size-cells = <1>;
1396                         status = "disabled";
1397                 };
1398
1399                 atl: atl@4843c000 {
1400                         compatible = "ti,dra7-atl";
1401                         reg = <0x4843c000 0x3ff>;
1402                         ti,hwmods = "atl";
1403                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1404                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1405                         clocks = <&atl_gfclk_mux>;
1406                         clock-names = "fck";
1407                         status = "disabled";
1408                 };
1409
1410                 crossbar_mpu: crossbar@4a002a48 {
1411                         compatible = "ti,irq-crossbar";
1412                         reg = <0x4a002a48 0x130>;
1413                         interrupt-controller;
1414                         interrupt-parent = <&wakeupgen>;
1415                         #interrupt-cells = <3>;
1416                         ti,max-irqs = <160>;
1417                         ti,max-crossbar-sources = <MAX_SOURCES>;
1418                         ti,reg-size = <2>;
1419                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1420                         ti,irqs-skip = <10 133 139 140>;
1421                         ti,irqs-safe-map = <0>;
1422                 };
1423
1424                 mac: ethernet@4a100000 {
1425                         compatible = "ti,cpsw";
1426                         ti,hwmods = "gmac";
1427                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1428                         clock-names = "fck", "cpts";
1429                         cpdma_channels = <8>;
1430                         ale_entries = <1024>;
1431                         bd_ram_size = <0x2000>;
1432                         no_bd_ram = <0>;
1433                         rx_descs = <64>;
1434                         mac_control = <0x20>;
1435                         slaves = <2>;
1436                         active_slave = <0>;
1437                         cpts_clock_mult = <0x80000000>;
1438                         cpts_clock_shift = <29>;
1439                         reg = <0x48484000 0x1000
1440                                0x48485200 0x2E00>;
1441                         #address-cells = <1>;
1442                         #size-cells = <1>;
1443                         /*
1444                          * rx_thresh_pend
1445                          * rx_pend
1446                          * tx_pend
1447                          * misc_pend
1448                          */
1449                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1450                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1451                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1452                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1453                         ranges;
1454                         status = "disabled";
1455
1456                         davinci_mdio: mdio@48485000 {
1457                                 compatible = "ti,davinci_mdio";
1458                                 #address-cells = <1>;
1459                                 #size-cells = <0>;
1460                                 ti,hwmods = "davinci_mdio";
1461                                 bus_freq = <1000000>;
1462                                 reg = <0x48485000 0x100>;
1463                         };
1464
1465                         cpsw_emac0: slave@48480200 {
1466                                 /* Filled in by U-Boot */
1467                                 mac-address = [ 00 00 00 00 00 00 ];
1468                         };
1469
1470                         cpsw_emac1: slave@48480300 {
1471                                 /* Filled in by U-Boot */
1472                                 mac-address = [ 00 00 00 00 00 00 ];
1473                         };
1474
1475                         phy_sel: cpsw-phy-sel@4a002554 {
1476                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1477                                 reg= <0x4a002554 0x4>;
1478                                 reg-names = "gmii-sel";
1479                         };
1480                 };
1481
1482                 dcan1: can@481cc000 {
1483                         compatible = "ti,dra7-d_can";
1484                         ti,hwmods = "dcan1";
1485                         reg = <0x4ae3c000 0x2000>;
1486                         syscon-raminit = <&scm_conf 0x558 0>;
1487                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1488                         clocks = <&dcan1_sys_clk_mux>;
1489                         status = "disabled";
1490                 };
1491
1492                 dcan2: can@481d0000 {
1493                         compatible = "ti,dra7-d_can";
1494                         ti,hwmods = "dcan2";
1495                         reg = <0x48480000 0x2000>;
1496                         syscon-raminit = <&scm_conf 0x558 1>;
1497                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1498                         clocks = <&sys_clkin1>;
1499                         status = "disabled";
1500                 };
1501
1502                 dss: dss@58000000 {
1503                         compatible = "ti,dra7-dss";
1504                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1505                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1506                         status = "disabled";
1507                         ti,hwmods = "dss_core";
1508                         /* CTRL_CORE_DSS_PLL_CONTROL */
1509                         syscon-pll-ctrl = <&scm_conf 0x538>;
1510                         #address-cells = <1>;
1511                         #size-cells = <1>;
1512                         ranges;
1513
1514                         dispc@58001000 {
1515                                 compatible = "ti,dra7-dispc";
1516                                 reg = <0x58001000 0x1000>;
1517                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1518                                 ti,hwmods = "dss_dispc";
1519                                 clocks = <&dss_dss_clk>;
1520                                 clock-names = "fck";
1521                                 /* CTRL_CORE_SMA_SW_1 */
1522                                 syscon-pol = <&scm_conf 0x534>;
1523                         };
1524
1525                         hdmi: encoder@58060000 {
1526                                 compatible = "ti,dra7-hdmi";
1527                                 reg = <0x58040000 0x200>,
1528                                       <0x58040200 0x80>,
1529                                       <0x58040300 0x80>,
1530                                       <0x58060000 0x19000>;
1531                                 reg-names = "wp", "pll", "phy", "core";
1532                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1533                                 status = "disabled";
1534                                 ti,hwmods = "dss_hdmi";
1535                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1536                                 clock-names = "fck", "sys_clk";
1537                         };
1538                 };
1539         };
1540
1541         thermal_zones: thermal-zones {
1542                 #include "omap4-cpu-thermal.dtsi"
1543                 #include "omap5-gpu-thermal.dtsi"
1544                 #include "omap5-core-thermal.dtsi"
1545         };
1546
1547 };
1548
1549 &cpu_thermal {
1550         polling-delay = <500>; /* milliseconds */
1551 };
1552
1553 /include/ "dra7xx-clocks.dtsi"