arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         compatible = "ti,dra7xx";
  22         interrupt-parent = <&crossbar_mpu>;
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_emac0;
  41                 ethernet1 = &cpsw_emac1;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&gic>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         wakeupgen: interrupt-controller@48281000 {
  68                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x48281000 0x1000>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         /*
  76          * The soc node represents the soc top level view. It is used for IPs
  77          * that are not memory mapped in the MPU view or for the MPU itself.
  78          */
  79         soc {
  80                 compatible = "ti,omap-infra";
  81                 mpu {
  82                         compatible = "ti,omap5-mpu";
  83                         ti,hwmods = "mpu";
  84                 };
  85         };
  86
  87         /*
  88          * XXX: Use a flat representation of the SOC interconnect.
  89          * The real OMAP interconnect network is quite complex.
  90          * Since it will not bring real advantage to represent that in DT for
  91          * the moment, just use a fake OCP bus entry to represent the whole bus
  92          * hierarchy.
  93          */
  94         ocp {
  95                 compatible = "ti,dra7-l3-noc", "simple-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99                 ti,hwmods = "l3_main_1", "l3_main_2";
 100                 reg = <0x44000000 0x1000000>,
 101                       <0x45000000 0x1000>;
 102                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 104
 105                 l4_cfg: l4@4a000000 {
 106                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         ranges = <0 0x4a000000 0x22c000>;
 110
 111                         scm: scm@2000 {
 112                                 compatible = "ti,dra7-scm-core", "simple-bus";
 113                                 reg = <0x2000 0x2000>;
 114                                 #address-cells = <1>;
 115                                 #size-cells = <1>;
 116                                 ranges = <0 0x2000 0x2000>;
 117
 118                                 scm_conf: scm_conf@0 {
 119                                         compatible = "syscon";
 120                                         reg = <0x0 0x1400>;
 121                                         #address-cells = <1>;
 122                                         #size-cells = <1>;
 123
 124                                         pbias_regulator: pbias_regulator {
 125                                                 compatible = "ti,pbias-omap";
 126                                                 reg = <0xe00 0x4>;
 127                                                 syscon = <&scm_conf>;
 128                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 129                                                         regulator-name = "pbias_mmc_omap5";
 130                                                         regulator-min-microvolt = <1800000>;
 131                                                         regulator-max-microvolt = <3000000>;
 132                                                 };
 133                                         };
 134
 135                                         scm_conf_clocks: clocks {
 136                                                 #address-cells = <1>;
 137                                                 #size-cells = <0>;
 138                                         };
 139                                 };
 140
 141                                 dra7_pmx_core: pinmux@1400 {
 142                                         compatible = "ti,dra7-padconf",
 143                                                      "pinctrl-single";
 144                                         reg = <0x1400 0x0468>;
 145                                         #address-cells = <1>;
 146                                         #size-cells = <0>;
 147                                         #interrupt-cells = <1>;
 148                                         interrupt-controller;
 149                                         pinctrl-single,register-width = <32>;
 150                                         pinctrl-single,function-mask = <0x3fffffff>;
 151                                 };
 152                         };
 153
 154                         cm_core_aon: cm_core_aon@5000 {
 155                                 compatible = "ti,dra7-cm-core-aon";
 156                                 reg = <0x5000 0x2000>;
 157
 158                                 cm_core_aon_clocks: clocks {
 159                                         #address-cells = <1>;
 160                                         #size-cells = <0>;
 161                                 };
 162
 163                                 cm_core_aon_clockdomains: clockdomains {
 164                                 };
 165                         };
 166
 167                         cm_core: cm_core@8000 {
 168                                 compatible = "ti,dra7-cm-core";
 169                                 reg = <0x8000 0x3000>;
 170
 171                                 cm_core_clocks: clocks {
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                 };
 175
 176                                 cm_core_clockdomains: clockdomains {
 177                                 };
 178                         };
 179                 };
 180
 181                 l4_wkup: l4@4ae00000 {
 182                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 183                         #address-cells = <1>;
 184                         #size-cells = <1>;
 185                         ranges = <0 0x4ae00000 0x3f000>;
 186
 187                         counter32k: counter@4000 {
 188                                 compatible = "ti,omap-counter32k";
 189                                 reg = <0x4000 0x40>;
 190                                 ti,hwmods = "counter_32k";
 191                         };
 192
 193                         prm: prm@6000 {
 194                                 compatible = "ti,dra7-prm";
 195                                 reg = <0x6000 0x3000>;
 196                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 197
 198                                 prm_clocks: clocks {
 199                                         #address-cells = <1>;
 200                                         #size-cells = <0>;
 201                                 };
 202
 203                                 prm_clockdomains: clockdomains {
 204                                 };
 205                         };
 206                 };
 207
 208                 axi@0 {
 209                         compatible = "simple-bus";
 210                         #size-cells = <1>;
 211                         #address-cells = <1>;
 212                         ranges = <0x51000000 0x51000000 0x3000
 213                                   0x0        0x20000000 0x10000000>;
 214                         pcie@51000000 {
 215                                 compatible = "ti,dra7-pcie";
 216                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 217                                 reg-names = "rc_dbics", "ti_conf", "config";
 218                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 219                                 #address-cells = <3>;
 220                                 #size-cells = <2>;
 221                                 device_type = "pci";
 222                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 223                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 224                                 #interrupt-cells = <1>;
 225                                 num-lanes = <1>;
 226                                 ti,hwmods = "pcie1";
 227                                 phys = <&pcie1_phy>;
 228                                 phy-names = "pcie-phy0";
 229                                 interrupt-map-mask = <0 0 0 7>;
 230                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 231                                                 <0 0 0 2 &pcie1_intc 2>,
 232                                                 <0 0 0 3 &pcie1_intc 3>,
 233                                                 <0 0 0 4 &pcie1_intc 4>;
 234                                 pcie1_intc: interrupt-controller {
 235                                         interrupt-controller;
 236                                         #address-cells = <0>;
 237                                         #interrupt-cells = <1>;
 238                                 };
 239                         };
 240                 };
 241
 242                 axi@1 {
 243                         compatible = "simple-bus";
 244                         #size-cells = <1>;
 245                         #address-cells = <1>;
 246                         ranges = <0x51800000 0x51800000 0x3000
 247                                   0x0        0x30000000 0x10000000>;
 248                         status = "disabled";
 249                         pcie@51000000 {
 250                                 compatible = "ti,dra7-pcie";
 251                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 252                                 reg-names = "rc_dbics", "ti_conf", "config";
 253                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 254                                 #address-cells = <3>;
 255                                 #size-cells = <2>;
 256                                 device_type = "pci";
 257                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 258                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 259                                 #interrupt-cells = <1>;
 260                                 num-lanes = <1>;
 261                                 ti,hwmods = "pcie2";
 262                                 phys = <&pcie2_phy>;
 263                                 phy-names = "pcie-phy0";
 264                                 interrupt-map-mask = <0 0 0 7>;
 265                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 266                                                 <0 0 0 2 &pcie2_intc 2>,
 267                                                 <0 0 0 3 &pcie2_intc 3>,
 268                                                 <0 0 0 4 &pcie2_intc 4>;
 269                                 pcie2_intc: interrupt-controller {
 270                                         interrupt-controller;
 271                                         #address-cells = <0>;
 272                                         #interrupt-cells = <1>;
 273                                 };
 274                         };
 275                 };
 276
 277                 bandgap: bandgap@4a0021e0 {
 278                         reg = <0x4a0021e0 0xc
 279                                 0x4a00232c 0xc
 280                                 0x4a002380 0x2c
 281                                 0x4a0023C0 0x3c
 282                                 0x4a002564 0x8
 283                                 0x4a002574 0x50>;
 284                                 compatible = "ti,dra752-bandgap";
 285                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 286                                 #thermal-sensor-cells = <1>;
 287                 };
 288
 289                 sdma: dma-controller@4a056000 {
 290                         compatible = "ti,omap4430-sdma";
 291                         reg = <0x4a056000 0x1000>;
 292                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 293                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 294                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 296                         #dma-cells = <1>;
 297                         dma-channels = <32>;
 298                         dma-requests = <127>;
 299                 };
 300
 301                 sdma_xbar: dma-router@4a002b78 {
 302                         compatible = "ti,dra7-dma-crossbar";
 303                         reg = <0x4a002b78 0xfc>;
 304                         #dma-cells = <1>;
 305                         dma-requests = <205>;
 306                         ti,dma-safe-map = <0>;
 307                         dma-masters = <&sdma>;
 308                 };
 309
 310                 gpio1: gpio@4ae10000 {
 311                         compatible = "ti,omap4-gpio";
 312                         reg = <0x4ae10000 0x200>;
 313                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 314                         ti,hwmods = "gpio1";
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                 };
 320
 321                 gpio2: gpio@48055000 {
 322                         compatible = "ti,omap4-gpio";
 323                         reg = <0x48055000 0x200>;
 324                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 325                         ti,hwmods = "gpio2";
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                 };
 331
 332                 gpio3: gpio@48057000 {
 333                         compatible = "ti,omap4-gpio";
 334                         reg = <0x48057000 0x200>;
 335                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 336                         ti,hwmods = "gpio3";
 337                         gpio-controller;
 338                         #gpio-cells = <2>;
 339                         interrupt-controller;
 340                         #interrupt-cells = <2>;
 341                 };
 342
 343                 gpio4: gpio@48059000 {
 344                         compatible = "ti,omap4-gpio";
 345                         reg = <0x48059000 0x200>;
 346                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 347                         ti,hwmods = "gpio4";
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                 };
 353
 354                 gpio5: gpio@4805b000 {
 355                         compatible = "ti,omap4-gpio";
 356                         reg = <0x4805b000 0x200>;
 357                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 358                         ti,hwmods = "gpio5";
 359                         gpio-controller;
 360                         #gpio-cells = <2>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                 };
 364
 365                 gpio6: gpio@4805d000 {
 366                         compatible = "ti,omap4-gpio";
 367                         reg = <0x4805d000 0x200>;
 368                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 369                         ti,hwmods = "gpio6";
 370                         gpio-controller;
 371                         #gpio-cells = <2>;
 372                         interrupt-controller;
 373                         #interrupt-cells = <2>;
 374                 };
 375
 376                 gpio7: gpio@48051000 {
 377                         compatible = "ti,omap4-gpio";
 378                         reg = <0x48051000 0x200>;
 379                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 380                         ti,hwmods = "gpio7";
 381                         gpio-controller;
 382                         #gpio-cells = <2>;
 383                         interrupt-controller;
 384                         #interrupt-cells = <2>;
 385                 };
 386
 387                 gpio8: gpio@48053000 {
 388                         compatible = "ti,omap4-gpio";
 389                         reg = <0x48053000 0x200>;
 390                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 391                         ti,hwmods = "gpio8";
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394                         interrupt-controller;
 395                         #interrupt-cells = <2>;
 396                 };
 397
 398                 uart1: serial@4806a000 {
 399                         compatible = "ti,omap4-uart";
 400                         reg = <0x4806a000 0x100>;
 401                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 402                         ti,hwmods = "uart1";
 403                         clock-frequency = <48000000>;
 404                         status = "disabled";
 405                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 406                         dma-names = "tx", "rx";
 407                 };
 408
 409                 uart2: serial@4806c000 {
 410                         compatible = "ti,omap4-uart";
 411                         reg = <0x4806c000 0x100>;
 412                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 413                         ti,hwmods = "uart2";
 414                         clock-frequency = <48000000>;
 415                         status = "disabled";
 416                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 417                         dma-names = "tx", "rx";
 418                 };
 419
 420                 uart3: serial@48020000 {
 421                         compatible = "ti,omap4-uart";
 422                         reg = <0x48020000 0x100>;
 423                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 424                         ti,hwmods = "uart3";
 425                         clock-frequency = <48000000>;
 426                         status = "disabled";
 427                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 428                         dma-names = "tx", "rx";
 429                 };
 430
 431                 uart4: serial@4806e000 {
 432                         compatible = "ti,omap4-uart";
 433                         reg = <0x4806e000 0x100>;
 434                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 435                         ti,hwmods = "uart4";
 436                         clock-frequency = <48000000>;
 437                         status = "disabled";
 438                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 439                         dma-names = "tx", "rx";
 440                 };
 441
 442                 uart5: serial@48066000 {
 443                         compatible = "ti,omap4-uart";
 444                         reg = <0x48066000 0x100>;
 445                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 446                         ti,hwmods = "uart5";
 447                         clock-frequency = <48000000>;
 448                         status = "disabled";
 449                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 450                         dma-names = "tx", "rx";
 451                 };
 452
 453                 uart6: serial@48068000 {
 454                         compatible = "ti,omap4-uart";
 455                         reg = <0x48068000 0x100>;
 456                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 457                         ti,hwmods = "uart6";
 458                         clock-frequency = <48000000>;
 459                         status = "disabled";
 460                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 461                         dma-names = "tx", "rx";
 462                 };
 463
 464                 uart7: serial@48420000 {
 465                         compatible = "ti,omap4-uart";
 466                         reg = <0x48420000 0x100>;
 467                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 468                         ti,hwmods = "uart7";
 469                         clock-frequency = <48000000>;
 470                         status = "disabled";
 471                 };
 472
 473                 uart8: serial@48422000 {
 474                         compatible = "ti,omap4-uart";
 475                         reg = <0x48422000 0x100>;
 476                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 477                         ti,hwmods = "uart8";
 478                         clock-frequency = <48000000>;
 479                         status = "disabled";
 480                 };
 481
 482                 uart9: serial@48424000 {
 483                         compatible = "ti,omap4-uart";
 484                         reg = <0x48424000 0x100>;
 485                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 486                         ti,hwmods = "uart9";
 487                         clock-frequency = <48000000>;
 488                         status = "disabled";
 489                 };
 490
 491                 uart10: serial@4ae2b000 {
 492                         compatible = "ti,omap4-uart";
 493                         reg = <0x4ae2b000 0x100>;
 494                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 495                         ti,hwmods = "uart10";
 496                         clock-frequency = <48000000>;
 497                         status = "disabled";
 498                 };
 499
 500                 mailbox1: mailbox@4a0f4000 {
 501                         compatible = "ti,omap4-mailbox";
 502                         reg = <0x4a0f4000 0x200>;
 503                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 504                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 506                         ti,hwmods = "mailbox1";
 507                         #mbox-cells = <1>;
 508                         ti,mbox-num-users = <3>;
 509                         ti,mbox-num-fifos = <8>;
 510                         status = "disabled";
 511                 };
 512
 513                 mailbox2: mailbox@4883a000 {
 514                         compatible = "ti,omap4-mailbox";
 515                         reg = <0x4883a000 0x200>;
 516                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "mailbox2";
 521                         #mbox-cells = <1>;
 522                         ti,mbox-num-users = <4>;
 523                         ti,mbox-num-fifos = <12>;
 524                         status = "disabled";
 525                 };
 526
 527                 mailbox3: mailbox@4883c000 {
 528                         compatible = "ti,omap4-mailbox";
 529                         reg = <0x4883c000 0x200>;
 530                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 534                         ti,hwmods = "mailbox3";
 535                         #mbox-cells = <1>;
 536                         ti,mbox-num-users = <4>;
 537                         ti,mbox-num-fifos = <12>;
 538                         status = "disabled";
 539                 };
 540
 541                 mailbox4: mailbox@4883e000 {
 542                         compatible = "ti,omap4-mailbox";
 543                         reg = <0x4883e000 0x200>;
 544                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "mailbox4";
 549                         #mbox-cells = <1>;
 550                         ti,mbox-num-users = <4>;
 551                         ti,mbox-num-fifos = <12>;
 552                         status = "disabled";
 553                 };
 554
 555                 mailbox5: mailbox@48840000 {
 556                         compatible = "ti,omap4-mailbox";
 557                         reg = <0x48840000 0x200>;
 558                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "mailbox5";
 563                         #mbox-cells = <1>;
 564                         ti,mbox-num-users = <4>;
 565                         ti,mbox-num-fifos = <12>;
 566                         status = "disabled";
 567                 };
 568
 569                 mailbox6: mailbox@48842000 {
 570                         compatible = "ti,omap4-mailbox";
 571                         reg = <0x48842000 0x200>;
 572                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 575                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 576                         ti,hwmods = "mailbox6";
 577                         #mbox-cells = <1>;
 578                         ti,mbox-num-users = <4>;
 579                         ti,mbox-num-fifos = <12>;
 580                         status = "disabled";
 581                 };
 582
 583                 mailbox7: mailbox@48844000 {
 584                         compatible = "ti,omap4-mailbox";
 585                         reg = <0x48844000 0x200>;
 586                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 590                         ti,hwmods = "mailbox7";
 591                         #mbox-cells = <1>;
 592                         ti,mbox-num-users = <4>;
 593                         ti,mbox-num-fifos = <12>;
 594                         status = "disabled";
 595                 };
 596
 597                 mailbox8: mailbox@48846000 {
 598                         compatible = "ti,omap4-mailbox";
 599                         reg = <0x48846000 0x200>;
 600                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 604                         ti,hwmods = "mailbox8";
 605                         #mbox-cells = <1>;
 606                         ti,mbox-num-users = <4>;
 607                         ti,mbox-num-fifos = <12>;
 608                         status = "disabled";
 609                 };
 610
 611                 mailbox9: mailbox@4885e000 {
 612                         compatible = "ti,omap4-mailbox";
 613                         reg = <0x4885e000 0x200>;
 614                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 618                         ti,hwmods = "mailbox9";
 619                         #mbox-cells = <1>;
 620                         ti,mbox-num-users = <4>;
 621                         ti,mbox-num-fifos = <12>;
 622                         status = "disabled";
 623                 };
 624
 625                 mailbox10: mailbox@48860000 {
 626                         compatible = "ti,omap4-mailbox";
 627                         reg = <0x48860000 0x200>;
 628                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "mailbox10";
 633                         #mbox-cells = <1>;
 634                         ti,mbox-num-users = <4>;
 635                         ti,mbox-num-fifos = <12>;
 636                         status = "disabled";
 637                 };
 638
 639                 mailbox11: mailbox@48862000 {
 640                         compatible = "ti,omap4-mailbox";
 641                         reg = <0x48862000 0x200>;
 642                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 643                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 644                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 646                         ti,hwmods = "mailbox11";
 647                         #mbox-cells = <1>;
 648                         ti,mbox-num-users = <4>;
 649                         ti,mbox-num-fifos = <12>;
 650                         status = "disabled";
 651                 };
 652
 653                 mailbox12: mailbox@48864000 {
 654                         compatible = "ti,omap4-mailbox";
 655                         reg = <0x48864000 0x200>;
 656                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 657                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 658                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 660                         ti,hwmods = "mailbox12";
 661                         #mbox-cells = <1>;
 662                         ti,mbox-num-users = <4>;
 663                         ti,mbox-num-fifos = <12>;
 664                         status = "disabled";
 665                 };
 666
 667                 mailbox13: mailbox@48802000 {
 668                         compatible = "ti,omap4-mailbox";
 669                         reg = <0x48802000 0x200>;
 670                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 674                         ti,hwmods = "mailbox13";
 675                         #mbox-cells = <1>;
 676                         ti,mbox-num-users = <4>;
 677                         ti,mbox-num-fifos = <12>;
 678                         status = "disabled";
 679                 };
 680
 681                 timer1: timer@4ae18000 {
 682                         compatible = "ti,omap5430-timer";
 683                         reg = <0x4ae18000 0x80>;
 684                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 685                         ti,hwmods = "timer1";
 686                         ti,timer-alwon;
 687                 };
 688
 689                 timer2: timer@48032000 {
 690                         compatible = "ti,omap5430-timer";
 691                         reg = <0x48032000 0x80>;
 692                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 693                         ti,hwmods = "timer2";
 694                 };
 695
 696                 timer3: timer@48034000 {
 697                         compatible = "ti,omap5430-timer";
 698                         reg = <0x48034000 0x80>;
 699                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 700                         ti,hwmods = "timer3";
 701                 };
 702
 703                 timer4: timer@48036000 {
 704                         compatible = "ti,omap5430-timer";
 705                         reg = <0x48036000 0x80>;
 706                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 707                         ti,hwmods = "timer4";
 708                 };
 709
 710                 timer5: timer@48820000 {
 711                         compatible = "ti,omap5430-timer";
 712                         reg = <0x48820000 0x80>;
 713                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 714                         ti,hwmods = "timer5";
 715                 };
 716
 717                 timer6: timer@48822000 {
 718                         compatible = "ti,omap5430-timer";
 719                         reg = <0x48822000 0x80>;
 720                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 721                         ti,hwmods = "timer6";
 722                 };
 723
 724                 timer7: timer@48824000 {
 725                         compatible = "ti,omap5430-timer";
 726                         reg = <0x48824000 0x80>;
 727                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "timer7";
 729                 };
 730
 731                 timer8: timer@48826000 {
 732                         compatible = "ti,omap5430-timer";
 733                         reg = <0x48826000 0x80>;
 734                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 735                         ti,hwmods = "timer8";
 736                 };
 737
 738                 timer9: timer@4803e000 {
 739                         compatible = "ti,omap5430-timer";
 740                         reg = <0x4803e000 0x80>;
 741                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 742                         ti,hwmods = "timer9";
 743                 };
 744
 745                 timer10: timer@48086000 {
 746                         compatible = "ti,omap5430-timer";
 747                         reg = <0x48086000 0x80>;
 748                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 749                         ti,hwmods = "timer10";
 750                 };
 751
 752                 timer11: timer@48088000 {
 753                         compatible = "ti,omap5430-timer";
 754                         reg = <0x48088000 0x80>;
 755                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 756                         ti,hwmods = "timer11";
 757                 };
 758
 759                 timer13: timer@48828000 {
 760                         compatible = "ti,omap5430-timer";
 761                         reg = <0x48828000 0x80>;
 762                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 763                         ti,hwmods = "timer13";
 764                         status = "disabled";
 765                 };
 766
 767                 timer14: timer@4882a000 {
 768                         compatible = "ti,omap5430-timer";
 769                         reg = <0x4882a000 0x80>;
 770                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 771                         ti,hwmods = "timer14";
 772                         status = "disabled";
 773                 };
 774
 775                 timer15: timer@4882c000 {
 776                         compatible = "ti,omap5430-timer";
 777                         reg = <0x4882c000 0x80>;
 778                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 779                         ti,hwmods = "timer15";
 780                         status = "disabled";
 781                 };
 782
 783                 timer16: timer@4882e000 {
 784                         compatible = "ti,omap5430-timer";
 785                         reg = <0x4882e000 0x80>;
 786                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 787                         ti,hwmods = "timer16";
 788                         status = "disabled";
 789                 };
 790
 791                 wdt2: wdt@4ae14000 {
 792                         compatible = "ti,omap3-wdt";
 793                         reg = <0x4ae14000 0x80>;
 794                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 795                         ti,hwmods = "wd_timer2";
 796                 };
 797
 798                 hwspinlock: spinlock@4a0f6000 {
 799                         compatible = "ti,omap4-hwspinlock";
 800                         reg = <0x4a0f6000 0x1000>;
 801                         ti,hwmods = "spinlock";
 802                         #hwlock-cells = <1>;
 803                 };
 804
 805                 dmm@4e000000 {
 806                         compatible = "ti,omap5-dmm";
 807                         reg = <0x4e000000 0x800>;
 808                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 809                         ti,hwmods = "dmm";
 810                 };
 811
 812                 i2c1: i2c@48070000 {
 813                         compatible = "ti,omap4-i2c";
 814                         reg = <0x48070000 0x100>;
 815                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818                         ti,hwmods = "i2c1";
 819                         status = "disabled";
 820                 };
 821
 822                 i2c2: i2c@48072000 {
 823                         compatible = "ti,omap4-i2c";
 824                         reg = <0x48072000 0x100>;
 825                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828                         ti,hwmods = "i2c2";
 829                         status = "disabled";
 830                 };
 831
 832                 i2c3: i2c@48060000 {
 833                         compatible = "ti,omap4-i2c";
 834                         reg = <0x48060000 0x100>;
 835                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 836                         #address-cells = <1>;
 837                         #size-cells = <0>;
 838                         ti,hwmods = "i2c3";
 839                         status = "disabled";
 840                 };
 841
 842                 i2c4: i2c@4807a000 {
 843                         compatible = "ti,omap4-i2c";
 844                         reg = <0x4807a000 0x100>;
 845                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 846                         #address-cells = <1>;
 847                         #size-cells = <0>;
 848                         ti,hwmods = "i2c4";
 849                         status = "disabled";
 850                 };
 851
 852                 i2c5: i2c@4807c000 {
 853                         compatible = "ti,omap4-i2c";
 854                         reg = <0x4807c000 0x100>;
 855                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         ti,hwmods = "i2c5";
 859                         status = "disabled";
 860                 };
 861
 862                 mmc1: mmc@4809c000 {
 863                         compatible = "ti,omap4-hsmmc";
 864                         reg = <0x4809c000 0x400>;
 865                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 866                         ti,hwmods = "mmc1";
 867                         ti,dual-volt;
 868                         ti,needs-special-reset;
 869                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
 870                         dma-names = "tx", "rx";
 871                         status = "disabled";
 872                         pbias-supply = <&pbias_mmc_reg>;
 873                 };
 874
 875                 mmc2: mmc@480b4000 {
 876                         compatible = "ti,omap4-hsmmc";
 877                         reg = <0x480b4000 0x400>;
 878                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 879                         ti,hwmods = "mmc2";
 880                         ti,needs-special-reset;
 881                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
 882                         dma-names = "tx", "rx";
 883                         status = "disabled";
 884                 };
 885
 886                 mmc3: mmc@480ad000 {
 887                         compatible = "ti,omap4-hsmmc";
 888                         reg = <0x480ad000 0x400>;
 889                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 890                         ti,hwmods = "mmc3";
 891                         ti,needs-special-reset;
 892                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
 893                         dma-names = "tx", "rx";
 894                         status = "disabled";
 895                 };
 896
 897                 mmc4: mmc@480d1000 {
 898                         compatible = "ti,omap4-hsmmc";
 899                         reg = <0x480d1000 0x400>;
 900                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 901                         ti,hwmods = "mmc4";
 902                         ti,needs-special-reset;
 903                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
 904                         dma-names = "tx", "rx";
 905                         status = "disabled";
 906                 };
 907
 908                 abb_mpu: regulator-abb-mpu {
 909                         compatible = "ti,abb-v3";
 910                         regulator-name = "abb_mpu";
 911                         #address-cells = <0>;
 912                         #size-cells = <0>;
 913                         clocks = <&sys_clkin1>;
 914                         ti,settling-time = <50>;
 915                         ti,clock-cycles = <16>;
 916
 917                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 918                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 919                               <0x4ae0c158 0x4>;
 920                         reg-names = "setup-address", "control-address",
 921                                     "int-address", "efuse-address",
 922                                     "ldo-address";
 923                         ti,tranxdone-status-mask = <0x80>;
 924                         /* LDOVBBMPU_FBB_MUX_CTRL */
 925                         ti,ldovbb-override-mask = <0x400>;
 926                         /* LDOVBBMPU_FBB_VSET_OUT */
 927                         ti,ldovbb-vset-mask = <0x1F>;
 928
 929                         /*
 930                          * NOTE: only FBB mode used but actual vset will
 931                          * determine final biasing
 932                          */
 933                         ti,abb_info = <
 934                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 935                         1060000         0       0x0     0 0x02000000 0x01F00000
 936                         1160000         0       0x4     0 0x02000000 0x01F00000
 937                         1210000         0       0x8     0 0x02000000 0x01F00000
 938                         >;
 939                 };
 940
 941                 abb_ivahd: regulator-abb-ivahd {
 942                         compatible = "ti,abb-v3";
 943                         regulator-name = "abb_ivahd";
 944                         #address-cells = <0>;
 945                         #size-cells = <0>;
 946                         clocks = <&sys_clkin1>;
 947                         ti,settling-time = <50>;
 948                         ti,clock-cycles = <16>;
 949
 950                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 951                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 952                               <0x4a002470 0x4>;
 953                         reg-names = "setup-address", "control-address",
 954                                     "int-address", "efuse-address",
 955                                     "ldo-address";
 956                         ti,tranxdone-status-mask = <0x40000000>;
 957                         /* LDOVBBIVA_FBB_MUX_CTRL */
 958                         ti,ldovbb-override-mask = <0x400>;
 959                         /* LDOVBBIVA_FBB_VSET_OUT */
 960                         ti,ldovbb-vset-mask = <0x1F>;
 961
 962                         /*
 963                          * NOTE: only FBB mode used but actual vset will
 964                          * determine final biasing
 965                          */
 966                         ti,abb_info = <
 967                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 968                         1055000         0       0x0     0 0x02000000 0x01F00000
 969                         1150000         0       0x4     0 0x02000000 0x01F00000
 970                         1250000         0       0x8     0 0x02000000 0x01F00000
 971                         >;
 972                 };
 973
 974                 abb_dspeve: regulator-abb-dspeve {
 975                         compatible = "ti,abb-v3";
 976                         regulator-name = "abb_dspeve";
 977                         #address-cells = <0>;
 978                         #size-cells = <0>;
 979                         clocks = <&sys_clkin1>;
 980                         ti,settling-time = <50>;
 981                         ti,clock-cycles = <16>;
 982
 983                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 984                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 985                               <0x4a00246c 0x4>;
 986                         reg-names = "setup-address", "control-address",
 987                                     "int-address", "efuse-address",
 988                                     "ldo-address";
 989                         ti,tranxdone-status-mask = <0x20000000>;
 990                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 991                         ti,ldovbb-override-mask = <0x400>;
 992                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 993                         ti,ldovbb-vset-mask = <0x1F>;
 994
 995                         /*
 996                          * NOTE: only FBB mode used but actual vset will
 997                          * determine final biasing
 998                          */
 999                         ti,abb_info = <
1000                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1001                         1055000         0       0x0     0 0x02000000 0x01F00000
1002                         1150000         0       0x4     0 0x02000000 0x01F00000
1003                         1250000         0       0x8     0 0x02000000 0x01F00000
1004                         >;
1005                 };
1006
1007                 abb_gpu: regulator-abb-gpu {
1008                         compatible = "ti,abb-v3";
1009                         regulator-name = "abb_gpu";
1010                         #address-cells = <0>;
1011                         #size-cells = <0>;
1012                         clocks = <&sys_clkin1>;
1013                         ti,settling-time = <50>;
1014                         ti,clock-cycles = <16>;
1015
1016                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1017                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1018                               <0x4ae0c154 0x4>;
1019                         reg-names = "setup-address", "control-address",
1020                                     "int-address", "efuse-address",
1021                                     "ldo-address";
1022                         ti,tranxdone-status-mask = <0x10000000>;
1023                         /* LDOVBBGPU_FBB_MUX_CTRL */
1024                         ti,ldovbb-override-mask = <0x400>;
1025                         /* LDOVBBGPU_FBB_VSET_OUT */
1026                         ti,ldovbb-vset-mask = <0x1F>;
1027
1028                         /*
1029                          * NOTE: only FBB mode used but actual vset will
1030                          * determine final biasing
1031                          */
1032                         ti,abb_info = <
1033                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1034                         1090000         0       0x0     0 0x02000000 0x01F00000
1035                         1210000         0       0x4     0 0x02000000 0x01F00000
1036                         1280000         0       0x8     0 0x02000000 0x01F00000
1037                         >;
1038                 };
1039
1040                 mcspi1: spi@48098000 {
1041                         compatible = "ti,omap4-mcspi";
1042                         reg = <0x48098000 0x200>;
1043                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1044                         #address-cells = <1>;
1045                         #size-cells = <0>;
1046                         ti,hwmods = "mcspi1";
1047                         ti,spi-num-cs = <4>;
1048                         dmas = <&sdma_xbar 35>,
1049                                <&sdma_xbar 36>,
1050                                <&sdma_xbar 37>,
1051                                <&sdma_xbar 38>,
1052                                <&sdma_xbar 39>,
1053                                <&sdma_xbar 40>,
1054                                <&sdma_xbar 41>,
1055                                <&sdma_xbar 42>;
1056                         dma-names = "tx0", "rx0", "tx1", "rx1",
1057                                     "tx2", "rx2", "tx3", "rx3";
1058                         status = "disabled";
1059                 };
1060
1061                 mcspi2: spi@4809a000 {
1062                         compatible = "ti,omap4-mcspi";
1063                         reg = <0x4809a000 0x200>;
1064                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1065                         #address-cells = <1>;
1066                         #size-cells = <0>;
1067                         ti,hwmods = "mcspi2";
1068                         ti,spi-num-cs = <2>;
1069                         dmas = <&sdma_xbar 43>,
1070                                <&sdma_xbar 44>,
1071                                <&sdma_xbar 45>,
1072                                <&sdma_xbar 46>;
1073                         dma-names = "tx0", "rx0", "tx1", "rx1";
1074                         status = "disabled";
1075                 };
1076
1077                 mcspi3: spi@480b8000 {
1078                         compatible = "ti,omap4-mcspi";
1079                         reg = <0x480b8000 0x200>;
1080                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1081                         #address-cells = <1>;
1082                         #size-cells = <0>;
1083                         ti,hwmods = "mcspi3";
1084                         ti,spi-num-cs = <2>;
1085                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1086                         dma-names = "tx0", "rx0";
1087                         status = "disabled";
1088                 };
1089
1090                 mcspi4: spi@480ba000 {
1091                         compatible = "ti,omap4-mcspi";
1092                         reg = <0x480ba000 0x200>;
1093                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1094                         #address-cells = <1>;
1095                         #size-cells = <0>;
1096                         ti,hwmods = "mcspi4";
1097                         ti,spi-num-cs = <1>;
1098                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1099                         dma-names = "tx0", "rx0";
1100                         status = "disabled";
1101                 };
1102
1103                 qspi: qspi@4b300000 {
1104                         compatible = "ti,dra7xxx-qspi";
1105                         reg = <0x4b300000 0x100>;
1106                         reg-names = "qspi_base";
1107                         #address-cells = <1>;
1108                         #size-cells = <0>;
1109                         ti,hwmods = "qspi";
1110                         clocks = <&qspi_gfclk_div>;
1111                         clock-names = "fck";
1112                         num-cs = <4>;
1113                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1114                         status = "disabled";
1115                 };
1116
1117                 omap_control_sata: control-phy@4a002374 {
1118                         compatible = "ti,control-phy-pipe3";
1119                         reg = <0x4a002374 0x4>;
1120                         reg-names = "power";
1121                         clocks = <&sys_clkin1>;
1122                         clock-names = "sysclk";
1123                 };
1124
1125                 /* OCP2SCP3 */
1126                 ocp2scp@4a090000 {
1127                         compatible = "ti,omap-ocp2scp";
1128                         #address-cells = <1>;
1129                         #size-cells = <1>;
1130                         ranges;
1131                         reg = <0x4a090000 0x20>;
1132                         ti,hwmods = "ocp2scp3";
1133                         sata_phy: phy@4A096000 {
1134                                 compatible = "ti,phy-pipe3-sata";
1135                                 reg = <0x4A096000 0x80>, /* phy_rx */
1136                                       <0x4A096400 0x64>, /* phy_tx */
1137                                       <0x4A096800 0x40>; /* pll_ctrl */
1138                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1139                                 ctrl-module = <&omap_control_sata>;
1140                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1141                                 clock-names = "sysclk", "refclk";
1142                                 #phy-cells = <0>;
1143                         };
1144
1145                         pcie1_phy: pciephy@4a094000 {
1146                                 compatible = "ti,phy-pipe3-pcie";
1147                                 reg = <0x4a094000 0x80>, /* phy_rx */
1148                                       <0x4a094400 0x64>; /* phy_tx */
1149                                 reg-names = "phy_rx", "phy_tx";
1150                                 ctrl-module = <&omap_control_pcie1phy>;
1151                                 clocks = <&dpll_pcie_ref_ck>,
1152                                          <&dpll_pcie_ref_m2ldo_ck>,
1153                                          <&optfclk_pciephy1_32khz>,
1154                                          <&optfclk_pciephy1_clk>,
1155                                          <&optfclk_pciephy1_div_clk>,
1156                                          <&optfclk_pciephy_div>;
1157                                 clock-names = "dpll_ref", "dpll_ref_m2",
1158                                               "wkupclk", "refclk",
1159                                               "div-clk", "phy-div";
1160                                 #phy-cells = <0>;
1161                         };
1162
1163                         pcie2_phy: pciephy@4a095000 {
1164                                 compatible = "ti,phy-pipe3-pcie";
1165                                 reg = <0x4a095000 0x80>, /* phy_rx */
1166                                       <0x4a095400 0x64>; /* phy_tx */
1167                                 reg-names = "phy_rx", "phy_tx";
1168                                 ctrl-module = <&omap_control_pcie2phy>;
1169                                 clocks = <&dpll_pcie_ref_ck>,
1170                                          <&dpll_pcie_ref_m2ldo_ck>,
1171                                          <&optfclk_pciephy2_32khz>,
1172                                          <&optfclk_pciephy2_clk>,
1173                                          <&optfclk_pciephy2_div_clk>,
1174                                          <&optfclk_pciephy_div>;
1175                                 clock-names = "dpll_ref", "dpll_ref_m2",
1176                                               "wkupclk", "refclk",
1177                                               "div-clk", "phy-div";
1178                                 #phy-cells = <0>;
1179                                 status = "disabled";
1180                         };
1181                 };
1182
1183                 sata: sata@4a141100 {
1184                         compatible = "snps,dwc-ahci";
1185                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1186                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1187                         phys = <&sata_phy>;
1188                         phy-names = "sata-phy";
1189                         clocks = <&sata_ref_clk>;
1190                         ti,hwmods = "sata";
1191                 };
1192
1193                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1194                         compatible = "ti,control-phy-pcie";
1195                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1196                         reg-names = "power", "control_sma", "pcie_pcs";
1197                         clocks = <&sys_clkin1>;
1198                         clock-names = "sysclk";
1199                 };
1200
1201                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1202                         compatible = "ti,control-phy-pcie";
1203                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1204                         reg-names = "power", "control_sma", "pcie_pcs";
1205                         clocks = <&sys_clkin1>;
1206                         clock-names = "sysclk";
1207                         status = "disabled";
1208                 };
1209
1210                 rtc: rtc@48838000 {
1211                         compatible = "ti,am3352-rtc";
1212                         reg = <0x48838000 0x100>;
1213                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1215                         ti,hwmods = "rtcss";
1216                         clocks = <&sys_32k_ck>;
1217                 };
1218
1219                 omap_control_usb2phy1: control-phy@4a002300 {
1220                         compatible = "ti,control-phy-usb2";
1221                         reg = <0x4a002300 0x4>;
1222                         reg-names = "power";
1223                 };
1224
1225                 omap_control_usb3phy1: control-phy@4a002370 {
1226                         compatible = "ti,control-phy-pipe3";
1227                         reg = <0x4a002370 0x4>;
1228                         reg-names = "power";
1229                 };
1230
1231                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1232                         compatible = "ti,control-phy-usb2-dra7";
1233                         reg = <0x4a002e74 0x4>;
1234                         reg-names = "power";
1235                 };
1236
1237                 /* OCP2SCP1 */
1238                 ocp2scp@4a080000 {
1239                         compatible = "ti,omap-ocp2scp";
1240                         #address-cells = <1>;
1241                         #size-cells = <1>;
1242                         ranges;
1243                         reg = <0x4a080000 0x20>;
1244                         ti,hwmods = "ocp2scp1";
1245
1246                         usb2_phy1: phy@4a084000 {
1247                                 compatible = "ti,omap-usb2";
1248                                 reg = <0x4a084000 0x400>;
1249                                 ctrl-module = <&omap_control_usb2phy1>;
1250                                 clocks = <&usb_phy1_always_on_clk32k>,
1251                                          <&usb_otg_ss1_refclk960m>;
1252                                 clock-names =   "wkupclk",
1253                                                 "refclk";
1254                                 #phy-cells = <0>;
1255                         };
1256
1257                         usb2_phy2: phy@4a085000 {
1258                                 compatible = "ti,omap-usb2";
1259                                 reg = <0x4a085000 0x400>;
1260                                 ctrl-module = <&omap_control_usb2phy2>;
1261                                 clocks = <&usb_phy2_always_on_clk32k>,
1262                                          <&usb_otg_ss2_refclk960m>;
1263                                 clock-names =   "wkupclk",
1264                                                 "refclk";
1265                                 #phy-cells = <0>;
1266                         };
1267
1268                         usb3_phy1: phy@4a084400 {
1269                                 compatible = "ti,omap-usb3";
1270                                 reg = <0x4a084400 0x80>,
1271                                       <0x4a084800 0x64>,
1272                                       <0x4a084c00 0x40>;
1273                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1274                                 ctrl-module = <&omap_control_usb3phy1>;
1275                                 clocks = <&usb_phy3_always_on_clk32k>,
1276                                          <&sys_clkin1>,
1277                                          <&usb_otg_ss1_refclk960m>;
1278                                 clock-names =   "wkupclk",
1279                                                 "sysclk",
1280                                                 "refclk";
1281                                 #phy-cells = <0>;
1282                         };
1283                 };
1284
1285                 omap_dwc3_1: omap_dwc3_1@48880000 {
1286                         compatible = "ti,dwc3";
1287                         ti,hwmods = "usb_otg_ss1";
1288                         reg = <0x48880000 0x10000>;
1289                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1290                         #address-cells = <1>;
1291                         #size-cells = <1>;
1292                         utmi-mode = <2>;
1293                         ranges;
1294                         usb1: usb@48890000 {
1295                                 compatible = "snps,dwc3";
1296                                 reg = <0x48890000 0x17000>;
1297                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1298                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1299                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1300                                 interrupt-names = "peripheral",
1301                                                   "host",
1302                                                   "otg";
1303                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1304                                 phy-names = "usb2-phy", "usb3-phy";
1305                                 tx-fifo-resize;
1306                                 maximum-speed = "super-speed";
1307                                 dr_mode = "otg";
1308                                 snps,dis_u3_susphy_quirk;
1309                                 snps,dis_u2_susphy_quirk;
1310                         };
1311                 };
1312
1313                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1314                         compatible = "ti,dwc3";
1315                         ti,hwmods = "usb_otg_ss2";
1316                         reg = <0x488c0000 0x10000>;
1317                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1318                         #address-cells = <1>;
1319                         #size-cells = <1>;
1320                         utmi-mode = <2>;
1321                         ranges;
1322                         usb2: usb@488d0000 {
1323                                 compatible = "snps,dwc3";
1324                                 reg = <0x488d0000 0x17000>;
1325                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1326                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1327                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1328                                 interrupt-names = "peripheral",
1329                                                   "host",
1330                                                   "otg";
1331                                 phys = <&usb2_phy2>;
1332                                 phy-names = "usb2-phy";
1333                                 tx-fifo-resize;
1334                                 maximum-speed = "high-speed";
1335                                 dr_mode = "otg";
1336                                 snps,dis_u3_susphy_quirk;
1337                                 snps,dis_u2_susphy_quirk;
1338                         };
1339                 };
1340
1341                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1342                 omap_dwc3_3: omap_dwc3_3@48900000 {
1343                         compatible = "ti,dwc3";
1344                         ti,hwmods = "usb_otg_ss3";
1345                         reg = <0x48900000 0x10000>;
1346                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1347                         #address-cells = <1>;
1348                         #size-cells = <1>;
1349                         utmi-mode = <2>;
1350                         ranges;
1351                         status = "disabled";
1352                         usb3: usb@48910000 {
1353                                 compatible = "snps,dwc3";
1354                                 reg = <0x48910000 0x17000>;
1355                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1356                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1357                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1358                                 interrupt-names = "peripheral",
1359                                                   "host",
1360                                                   "otg";
1361                                 tx-fifo-resize;
1362                                 maximum-speed = "high-speed";
1363                                 dr_mode = "otg";
1364                                 snps,dis_u3_susphy_quirk;
1365                                 snps,dis_u2_susphy_quirk;
1366                         };
1367                 };
1368
1369                 elm: elm@48078000 {
1370                         compatible = "ti,am3352-elm";
1371                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1372                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1373                         ti,hwmods = "elm";
1374                         status = "disabled";
1375                 };
1376
1377                 gpmc: gpmc@50000000 {
1378                         compatible = "ti,am3352-gpmc";
1379                         ti,hwmods = "gpmc";
1380                         reg = <0x50000000 0x37c>;      /* device IO registers */
1381                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1382                         gpmc,num-cs = <8>;
1383                         gpmc,num-waitpins = <2>;
1384                         #address-cells = <2>;
1385                         #size-cells = <1>;
1386                         status = "disabled";
1387                 };
1388
1389                 atl: atl@4843c000 {
1390                         compatible = "ti,dra7-atl";
1391                         reg = <0x4843c000 0x3ff>;
1392                         ti,hwmods = "atl";
1393                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1394                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1395                         clocks = <&atl_gfclk_mux>;
1396                         clock-names = "fck";
1397                         status = "disabled";
1398                 };
1399
1400                 crossbar_mpu: crossbar@4a002a48 {
1401                         compatible = "ti,irq-crossbar";
1402                         reg = <0x4a002a48 0x130>;
1403                         interrupt-controller;
1404                         interrupt-parent = <&wakeupgen>;
1405                         #interrupt-cells = <3>;
1406                         ti,max-irqs = <160>;
1407                         ti,max-crossbar-sources = <MAX_SOURCES>;
1408                         ti,reg-size = <2>;
1409                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1410                         ti,irqs-skip = <10 133 139 140>;
1411                         ti,irqs-safe-map = <0>;
1412                 };
1413
1414                 mac: ethernet@4a100000 {
1415                         compatible = "ti,cpsw";
1416                         ti,hwmods = "gmac";
1417                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1418                         clock-names = "fck", "cpts";
1419                         cpdma_channels = <8>;
1420                         ale_entries = <1024>;
1421                         bd_ram_size = <0x2000>;
1422                         no_bd_ram = <0>;
1423                         rx_descs = <64>;
1424                         mac_control = <0x20>;
1425                         slaves = <2>;
1426                         active_slave = <0>;
1427                         cpts_clock_mult = <0x80000000>;
1428                         cpts_clock_shift = <29>;
1429                         reg = <0x48484000 0x1000
1430                                0x48485200 0x2E00>;
1431                         #address-cells = <1>;
1432                         #size-cells = <1>;
1433                         /*
1434                          * rx_thresh_pend
1435                          * rx_pend
1436                          * tx_pend
1437                          * misc_pend
1438                          */
1439                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1440                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1441                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1442                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1443                         ranges;
1444                         status = "disabled";
1445
1446                         davinci_mdio: mdio@48485000 {
1447                                 compatible = "ti,davinci_mdio";
1448                                 #address-cells = <1>;
1449                                 #size-cells = <0>;
1450                                 ti,hwmods = "davinci_mdio";
1451                                 bus_freq = <1000000>;
1452                                 reg = <0x48485000 0x100>;
1453                         };
1454
1455                         cpsw_emac0: slave@48480200 {
1456                                 /* Filled in by U-Boot */
1457                                 mac-address = [ 00 00 00 00 00 00 ];
1458                         };
1459
1460                         cpsw_emac1: slave@48480300 {
1461                                 /* Filled in by U-Boot */
1462                                 mac-address = [ 00 00 00 00 00 00 ];
1463                         };
1464
1465                         phy_sel: cpsw-phy-sel@4a002554 {
1466                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1467                                 reg= <0x4a002554 0x4>;
1468                                 reg-names = "gmii-sel";
1469                         };
1470                 };
1471
1472                 dcan1: can@481cc000 {
1473                         compatible = "ti,dra7-d_can";
1474                         ti,hwmods = "dcan1";
1475                         reg = <0x4ae3c000 0x2000>;
1476                         syscon-raminit = <&scm_conf 0x558 0>;
1477                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1478                         clocks = <&dcan1_sys_clk_mux>;
1479                         status = "disabled";
1480                 };
1481
1482                 dcan2: can@481d0000 {
1483                         compatible = "ti,dra7-d_can";
1484                         ti,hwmods = "dcan2";
1485                         reg = <0x48480000 0x2000>;
1486                         syscon-raminit = <&scm_conf 0x558 1>;
1487                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1488                         clocks = <&sys_clkin1>;
1489                         status = "disabled";
1490                 };
1491
1492                 dss: dss@58000000 {
1493                         compatible = "ti,dra7-dss";
1494                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1495                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1496                         status = "disabled";
1497                         ti,hwmods = "dss_core";
1498                         /* CTRL_CORE_DSS_PLL_CONTROL */
1499                         syscon-pll-ctrl = <&scm_conf 0x538>;
1500                         #address-cells = <1>;
1501                         #size-cells = <1>;
1502                         ranges;
1503
1504                         dispc@58001000 {
1505                                 compatible = "ti,dra7-dispc";
1506                                 reg = <0x58001000 0x1000>;
1507                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1508                                 ti,hwmods = "dss_dispc";
1509                                 clocks = <&dss_dss_clk>;
1510                                 clock-names = "fck";
1511                                 /* CTRL_CORE_SMA_SW_1 */
1512                                 syscon-pol = <&scm_conf 0x534>;
1513                         };
1514
1515                         hdmi: encoder@58060000 {
1516                                 compatible = "ti,dra7-hdmi";
1517                                 reg = <0x58040000 0x200>,
1518                                       <0x58040200 0x80>,
1519                                       <0x58040300 0x80>,
1520                                       <0x58060000 0x19000>;
1521                                 reg-names = "wp", "pll", "phy", "core";
1522                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1523                                 status = "disabled";
1524                                 ti,hwmods = "dss_hdmi";
1525                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1526                                 clock-names = "fck", "sys_clk";
1527                         };
1528                 };
1529         };
1530
1531         thermal_zones: thermal-zones {
1532                 #include "omap4-cpu-thermal.dtsi"
1533                 #include "omap5-gpu-thermal.dtsi"
1534                 #include "omap5-core-thermal.dtsi"
1535         };
1536
1537 };
1538
1539 &cpu_thermal {
1540         polling-delay = <500>; /* milliseconds */
1541 };
1542
1543 /include/ "dra7xx-clocks.dtsi"