arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420", "samsung,exynos5";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49                 usbdrdphy0 = &usbdrd_phy0;
  50                 usbdrdphy1 = &usbdrd_phy1;
  51         };
  52
  53         cluster_a15_opp_table: opp_table0 {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56                 opp@1800000000 {
  57                         opp-hz = /bits/ 64 <1800000000>;
  58                         opp-microvolt = <1250000>;
  59                         clock-latency-ns = <140000>;
  60                 };
  61                 opp@1700000000 {
  62                         opp-hz = /bits/ 64 <1700000000>;
  63                         opp-microvolt = <1212500>;
  64                         clock-latency-ns = <140000>;
  65                 };
  66                 opp@1600000000 {
  67                         opp-hz = /bits/ 64 <1600000000>;
  68                         opp-microvolt = <1175000>;
  69                         clock-latency-ns = <140000>;
  70                 };
  71                 opp@1500000000 {
  72                         opp-hz = /bits/ 64 <1500000000>;
  73                         opp-microvolt = <1137500>;
  74                         clock-latency-ns = <140000>;
  75                 };
  76                 opp@1400000000 {
  77                         opp-hz = /bits/ 64 <1400000000>;
  78                         opp-microvolt = <1112500>;
  79                         clock-latency-ns = <140000>;
  80                 };
  81                 opp@1300000000 {
  82                         opp-hz = /bits/ 64 <1300000000>;
  83                         opp-microvolt = <1062500>;
  84                         clock-latency-ns = <140000>;
  85                 };
  86                 opp@1200000000 {
  87                         opp-hz = /bits/ 64 <1200000000>;
  88                         opp-microvolt = <1037500>;
  89                         clock-latency-ns = <140000>;
  90                 };
  91                 opp@1100000000 {
  92                         opp-hz = /bits/ 64 <1100000000>;
  93                         opp-microvolt = <1012500>;
  94                         clock-latency-ns = <140000>;
  95                 };
  96                 opp@1000000000 {
  97                         opp-hz = /bits/ 64 <1000000000>;
  98                         opp-microvolt = < 987500>;
  99                         clock-latency-ns = <140000>;
 100                 };
 101                 opp@900000000 {
 102                         opp-hz = /bits/ 64 <900000000>;
 103                         opp-microvolt = < 962500>;
 104                         clock-latency-ns = <140000>;
 105                 };
 106                 opp@800000000 {
 107                         opp-hz = /bits/ 64 <800000000>;
 108                         opp-microvolt = < 937500>;
 109                         clock-latency-ns = <140000>;
 110                 };
 111                 opp@700000000 {
 112                         opp-hz = /bits/ 64 <700000000>;
 113                         opp-microvolt = < 912500>;
 114                         clock-latency-ns = <140000>;
 115                 };
 116         };
 117
 118         cluster_a7_opp_table: opp_table1 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121                 opp@1300000000 {
 122                         opp-hz = /bits/ 64 <1300000000>;
 123                         opp-microvolt = <1275000>;
 124                         clock-latency-ns = <140000>;
 125                 };
 126                 opp@1200000000 {
 127                         opp-hz = /bits/ 64 <1200000000>;
 128                         opp-microvolt = <1212500>;
 129                         clock-latency-ns = <140000>;
 130                 };
 131                 opp@1100000000 {
 132                         opp-hz = /bits/ 64 <1100000000>;
 133                         opp-microvolt = <1162500>;
 134                         clock-latency-ns = <140000>;
 135                 };
 136                 opp@1000000000 {
 137                         opp-hz = /bits/ 64 <1000000000>;
 138                         opp-microvolt = <1112500>;
 139                         clock-latency-ns = <140000>;
 140                 };
 141                 opp@900000000 {
 142                         opp-hz = /bits/ 64 <900000000>;
 143                         opp-microvolt = <1062500>;
 144                         clock-latency-ns = <140000>;
 145                 };
 146                 opp@800000000 {
 147                         opp-hz = /bits/ 64 <800000000>;
 148                         opp-microvolt = <1025000>;
 149                         clock-latency-ns = <140000>;
 150                 };
 151                 opp@700000000 {
 152                         opp-hz = /bits/ 64 <700000000>;
 153                         opp-microvolt = <975000>;
 154                         clock-latency-ns = <140000>;
 155                 };
 156                 opp@600000000 {
 157                         opp-hz = /bits/ 64 <600000000>;
 158                         opp-microvolt = <937500>;
 159                         clock-latency-ns = <140000>;
 160                 };
 161         };
 162
 163         /*
 164          * The 'cpus' node is not present here but instead it is provided
 165          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
 166          */
 167
 168         cci: cci@10d20000 {
 169                 compatible = "arm,cci-400";
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 reg = <0x10d20000 0x1000>;
 173                 ranges = <0x0 0x10d20000 0x6000>;
 174
 175                 cci_control0: slave-if@4000 {
 176                         compatible = "arm,cci-400-ctrl-if";
 177                         interface-type = "ace";
 178                         reg = <0x4000 0x1000>;
 179                 };
 180                 cci_control1: slave-if@5000 {
 181                         compatible = "arm,cci-400-ctrl-if";
 182                         interface-type = "ace";
 183                         reg = <0x5000 0x1000>;
 184                 };
 185         };
 186
 187         sysram@02020000 {
 188                 compatible = "mmio-sram";
 189                 reg = <0x02020000 0x54000>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 ranges = <0 0x02020000 0x54000>;
 193
 194                 smp-sysram@0 {
 195                         compatible = "samsung,exynos4210-sysram";
 196                         reg = <0x0 0x1000>;
 197                 };
 198
 199                 smp-sysram@53000 {
 200                         compatible = "samsung,exynos4210-sysram-ns";
 201                         reg = <0x53000 0x1000>;
 202                 };
 203         };
 204
 205         clock: clock-controller@10010000 {
 206                 compatible = "samsung,exynos5420-clock";
 207                 reg = <0x10010000 0x30000>;
 208                 #clock-cells = <1>;
 209         };
 210
 211         clock_audss: audss-clock-controller@3810000 {
 212                 compatible = "samsung,exynos5420-audss-clock";
 213                 reg = <0x03810000 0x0C>;
 214                 #clock-cells = <1>;
 215                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 216                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 217                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 218         };
 219
 220         mfc: codec@11000000 {
 221                 compatible = "samsung,mfc-v7";
 222                 reg = <0x11000000 0x10000>;
 223                 interrupts = <0 96 0>;
 224                 clocks = <&clock CLK_MFC>;
 225                 clock-names = "mfc";
 226                 power-domains = <&mfc_pd>;
 227                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 228                 iommu-names = "left", "right";
 229         };
 230
 231         mmc_0: mmc@12200000 {
 232                 compatible = "samsung,exynos5420-dw-mshc-smu";
 233                 interrupts = <0 75 0>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 reg = <0x12200000 0x2000>;
 237                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 238                 clock-names = "biu", "ciu";
 239                 fifo-depth = <0x40>;
 240                 status = "disabled";
 241         };
 242
 243         mmc_1: mmc@12210000 {
 244                 compatible = "samsung,exynos5420-dw-mshc-smu";
 245                 interrupts = <0 76 0>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248                 reg = <0x12210000 0x2000>;
 249                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 250                 clock-names = "biu", "ciu";
 251                 fifo-depth = <0x40>;
 252                 status = "disabled";
 253         };
 254
 255         mmc_2: mmc@12220000 {
 256                 compatible = "samsung,exynos5420-dw-mshc";
 257                 interrupts = <0 77 0>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 reg = <0x12220000 0x1000>;
 261                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 262                 clock-names = "biu", "ciu";
 263                 fifo-depth = <0x40>;
 264                 status = "disabled";
 265         };
 266
 267         mct: mct@101C0000 {
 268                 compatible = "samsung,exynos4210-mct";
 269                 reg = <0x101C0000 0x800>;
 270                 interrupt-controller;
 271                 #interrupt-cells = <1>;
 272                 interrupt-parent = <&mct_map>;
 273                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 274                                 <8>, <9>, <10>, <11>;
 275                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 276                 clock-names = "fin_pll", "mct";
 277
 278                 mct_map: mct-map {
 279                         #interrupt-cells = <1>;
 280                         #address-cells = <0>;
 281                         #size-cells = <0>;
 282                         interrupt-map = <0 &combiner 23 3>,
 283                                         <1 &combiner 23 4>,
 284                                         <2 &combiner 25 2>,
 285                                         <3 &combiner 25 3>,
 286                                         <4 &gic 0 120 0>,
 287                                         <5 &gic 0 121 0>,
 288                                         <6 &gic 0 122 0>,
 289                                         <7 &gic 0 123 0>,
 290                                         <8 &gic 0 128 0>,
 291                                         <9 &gic 0 129 0>,
 292                                         <10 &gic 0 130 0>,
 293                                         <11 &gic 0 131 0>;
 294                 };
 295         };
 296
 297         nocp_mem0_0: nocp@10CA1000 {
 298                 compatible = "samsung,exynos5420-nocp";
 299                 reg = <0x10CA1000 0x200>;
 300                 status = "disabled";
 301         };
 302
 303         nocp_mem0_1: nocp@10CA1400 {
 304                 compatible = "samsung,exynos5420-nocp";
 305                 reg = <0x10CA1400 0x200>;
 306                 status = "disabled";
 307         };
 308
 309         nocp_mem1_0: nocp@10CA1800 {
 310                 compatible = "samsung,exynos5420-nocp";
 311                 reg = <0x10CA1800 0x200>;
 312                 status = "disabled";
 313         };
 314
 315         nocp_mem1_1: nocp@10CA1C00 {
 316                 compatible = "samsung,exynos5420-nocp";
 317                 reg = <0x10CA1C00 0x200>;
 318                 status = "disabled";
 319         };
 320
 321         nocp_g3d_0: nocp@11A51000 {
 322                 compatible = "samsung,exynos5420-nocp";
 323                 reg = <0x11A51000 0x200>;
 324                 status = "disabled";
 325         };
 326
 327         nocp_g3d_1: nocp@11A51400 {
 328                 compatible = "samsung,exynos5420-nocp";
 329                 reg = <0x11A51400 0x200>;
 330                 status = "disabled";
 331         };
 332
 333         gsc_pd: power-domain@10044000 {
 334                 compatible = "samsung,exynos4210-pd";
 335                 reg = <0x10044000 0x20>;
 336                 #power-domain-cells = <0>;
 337                 clocks = <&clock CLK_FIN_PLL>,
 338                          <&clock CLK_MOUT_USER_ACLK300_GSCL>,
 339                          <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 340                 clock-names = "oscclk", "clk0", "asb0", "asb1";
 341         };
 342
 343         isp_pd: power-domain@10044020 {
 344                 compatible = "samsung,exynos4210-pd";
 345                 reg = <0x10044020 0x20>;
 346                 #power-domain-cells = <0>;
 347         };
 348
 349         mfc_pd: power-domain@10044060 {
 350                 compatible = "samsung,exynos4210-pd";
 351                 reg = <0x10044060 0x20>;
 352                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>,
 353                          <&clock CLK_ACLK333>;
 354                 clock-names = "oscclk", "clk0","asb0";
 355                 #power-domain-cells = <0>;
 356         };
 357
 358         msc_pd: power-domain@10044120 {
 359                 compatible = "samsung,exynos4210-pd";
 360                 reg = <0x10044120 0x20>;
 361                 #power-domain-cells = <0>;
 362         };
 363
 364         disp_pd: power-domain@100440C0 {
 365                 compatible = "samsung,exynos4210-pd";
 366                 reg = <0x100440C0 0x20>;
 367                 #power-domain-cells = <0>;
 368                 clocks = <&clock CLK_FIN_PLL>,
 369                          <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 370                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 371                          <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 372                          <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 373                 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 374         };
 375
 376         pinctrl_0: pinctrl@13400000 {
 377                 compatible = "samsung,exynos5420-pinctrl";
 378                 reg = <0x13400000 0x1000>;
 379                 interrupts = <0 45 0>;
 380
 381                 wakeup-interrupt-controller {
 382                         compatible = "samsung,exynos4210-wakeup-eint";
 383                         interrupt-parent = <&gic>;
 384                         interrupts = <0 32 0>;
 385                 };
 386         };
 387
 388         pinctrl_1: pinctrl@13410000 {
 389                 compatible = "samsung,exynos5420-pinctrl";
 390                 reg = <0x13410000 0x1000>;
 391                 interrupts = <0 78 0>;
 392         };
 393
 394         pinctrl_2: pinctrl@14000000 {
 395                 compatible = "samsung,exynos5420-pinctrl";
 396                 reg = <0x14000000 0x1000>;
 397                 interrupts = <0 46 0>;
 398         };
 399
 400         pinctrl_3: pinctrl@14010000 {
 401                 compatible = "samsung,exynos5420-pinctrl";
 402                 reg = <0x14010000 0x1000>;
 403                 interrupts = <0 50 0>;
 404         };
 405
 406         pinctrl_4: pinctrl@03860000 {
 407                 compatible = "samsung,exynos5420-pinctrl";
 408                 reg = <0x03860000 0x1000>;
 409                 interrupts = <0 47 0>;
 410         };
 411
 412         amba {
 413                 #address-cells = <1>;
 414                 #size-cells = <1>;
 415                 compatible = "simple-bus";
 416                 interrupt-parent = <&gic>;
 417                 ranges;
 418
 419                 adma: adma@03880000 {
 420                         compatible = "arm,pl330", "arm,primecell";
 421                         reg = <0x03880000 0x1000>;
 422                         interrupts = <0 110 0>;
 423                         clocks = <&clock_audss EXYNOS_ADMA>;
 424                         clock-names = "apb_pclk";
 425                         #dma-cells = <1>;
 426                         #dma-channels = <6>;
 427                         #dma-requests = <16>;
 428                 };
 429
 430                 pdma0: pdma@121A0000 {
 431                         compatible = "arm,pl330", "arm,primecell";
 432                         reg = <0x121A0000 0x1000>;
 433                         interrupts = <0 34 0>;
 434                         clocks = <&clock CLK_PDMA0>;
 435                         clock-names = "apb_pclk";
 436                         #dma-cells = <1>;
 437                         #dma-channels = <8>;
 438                         #dma-requests = <32>;
 439                 };
 440
 441                 pdma1: pdma@121B0000 {
 442                         compatible = "arm,pl330", "arm,primecell";
 443                         reg = <0x121B0000 0x1000>;
 444                         interrupts = <0 35 0>;
 445                         clocks = <&clock CLK_PDMA1>;
 446                         clock-names = "apb_pclk";
 447                         #dma-cells = <1>;
 448                         #dma-channels = <8>;
 449                         #dma-requests = <32>;
 450                 };
 451
 452                 mdma0: mdma@10800000 {
 453                         compatible = "arm,pl330", "arm,primecell";
 454                         reg = <0x10800000 0x1000>;
 455                         interrupts = <0 33 0>;
 456                         clocks = <&clock CLK_MDMA0>;
 457                         clock-names = "apb_pclk";
 458                         #dma-cells = <1>;
 459                         #dma-channels = <8>;
 460                         #dma-requests = <1>;
 461                 };
 462
 463                 mdma1: mdma@11C10000 {
 464                         compatible = "arm,pl330", "arm,primecell";
 465                         reg = <0x11C10000 0x1000>;
 466                         interrupts = <0 124 0>;
 467                         clocks = <&clock CLK_MDMA1>;
 468                         clock-names = "apb_pclk";
 469                         #dma-cells = <1>;
 470                         #dma-channels = <8>;
 471                         #dma-requests = <1>;
 472                         /*
 473                          * MDMA1 can support both secure and non-secure
 474                          * AXI transactions. When this is enabled in the kernel
 475                          * for boards that run in secure mode, we are getting
 476                          * imprecise external aborts causing the kernel to oops.
 477                          */
 478                         status = "disabled";
 479                 };
 480         };
 481
 482         i2s0: i2s@03830000 {
 483                 compatible = "samsung,exynos5420-i2s";
 484                 reg = <0x03830000 0x100>;
 485                 dmas = <&adma 0
 486                         &adma 2
 487                         &adma 1>;
 488                 dma-names = "tx", "rx", "tx-sec";
 489                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 490                         <&clock_audss EXYNOS_I2S_BUS>,
 491                         <&clock_audss EXYNOS_SCLK_I2S>;
 492                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 493                 #clock-cells = <1>;
 494                 clock-output-names = "i2s_cdclk0";
 495                 #sound-dai-cells = <1>;
 496                 samsung,idma-addr = <0x03000000>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&i2s0_bus>;
 499                 status = "disabled";
 500         };
 501
 502         i2s1: i2s@12D60000 {
 503                 compatible = "samsung,exynos5420-i2s";
 504                 reg = <0x12D60000 0x100>;
 505                 dmas = <&pdma1 12
 506                         &pdma1 11>;
 507                 dma-names = "tx", "rx";
 508                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 509                 clock-names = "iis", "i2s_opclk0";
 510                 #clock-cells = <1>;
 511                 clock-output-names = "i2s_cdclk1";
 512                 #sound-dai-cells = <1>;
 513                 pinctrl-names = "default";
 514                 pinctrl-0 = <&i2s1_bus>;
 515                 status = "disabled";
 516         };
 517
 518         i2s2: i2s@12D70000 {
 519                 compatible = "samsung,exynos5420-i2s";
 520                 reg = <0x12D70000 0x100>;
 521                 dmas = <&pdma0 12
 522                         &pdma0 11>;
 523                 dma-names = "tx", "rx";
 524                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 525                 clock-names = "iis", "i2s_opclk0";
 526                 #clock-cells = <1>;
 527                 clock-output-names = "i2s_cdclk2";
 528                 #sound-dai-cells = <1>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2s2_bus>;
 531                 status = "disabled";
 532         };
 533
 534         spi_0: spi@12d20000 {
 535                 compatible = "samsung,exynos4210-spi";
 536                 reg = <0x12d20000 0x100>;
 537                 interrupts = <0 68 0>;
 538                 dmas = <&pdma0 5
 539                         &pdma0 4>;
 540                 dma-names = "tx", "rx";
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&spi0_bus>;
 545                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 546                 clock-names = "spi", "spi_busclk0";
 547                 status = "disabled";
 548         };
 549
 550         spi_1: spi@12d30000 {
 551                 compatible = "samsung,exynos4210-spi";
 552                 reg = <0x12d30000 0x100>;
 553                 interrupts = <0 69 0>;
 554                 dmas = <&pdma1 5
 555                         &pdma1 4>;
 556                 dma-names = "tx", "rx";
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&spi1_bus>;
 561                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 562                 clock-names = "spi", "spi_busclk0";
 563                 status = "disabled";
 564         };
 565
 566         spi_2: spi@12d40000 {
 567                 compatible = "samsung,exynos4210-spi";
 568                 reg = <0x12d40000 0x100>;
 569                 interrupts = <0 70 0>;
 570                 dmas = <&pdma0 7
 571                         &pdma0 6>;
 572                 dma-names = "tx", "rx";
 573                 #address-cells = <1>;
 574                 #size-cells = <0>;
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&spi2_bus>;
 577                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 578                 clock-names = "spi", "spi_busclk0";
 579                 status = "disabled";
 580         };
 581
 582         pwm: pwm@12dd0000 {
 583                 compatible = "samsung,exynos4210-pwm";
 584                 reg = <0x12dd0000 0x100>;
 585                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 586                 #pwm-cells = <3>;
 587                 clocks = <&clock CLK_PWM>;
 588                 clock-names = "timers";
 589         };
 590
 591         dp_phy: dp-video-phy {
 592                 compatible = "samsung,exynos5420-dp-video-phy";
 593                 samsung,pmu-syscon = <&pmu_system_controller>;
 594                 #phy-cells = <0>;
 595         };
 596
 597         mipi_phy: mipi-video-phy {
 598                 compatible = "samsung,s5pv210-mipi-video-phy";
 599                 syscon = <&pmu_system_controller>;
 600                 #phy-cells = <1>;
 601         };
 602
 603         dsi@14500000 {
 604                 compatible = "samsung,exynos5410-mipi-dsi";
 605                 reg = <0x14500000 0x10000>;
 606                 interrupts = <0 82 0>;
 607                 phys = <&mipi_phy 1>;
 608                 phy-names = "dsim";
 609                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 610                 clock-names = "bus_clk", "pll_clk";
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 status = "disabled";
 614         };
 615
 616         adc: adc@12D10000 {
 617                 compatible = "samsung,exynos-adc-v2";
 618                 reg = <0x12D10000 0x100>;
 619                 interrupts = <0 106 0>;
 620                 clocks = <&clock CLK_TSADC>;
 621                 clock-names = "adc";
 622                 #io-channel-cells = <1>;
 623                 io-channel-ranges;
 624                 samsung,syscon-phandle = <&pmu_system_controller>;
 625                 status = "disabled";
 626         };
 627
 628         i2c_0: i2c@12C60000 {
 629                 compatible = "samsung,s3c2440-i2c";
 630                 reg = <0x12C60000 0x100>;
 631                 interrupts = <0 56 0>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clocks = <&clock CLK_I2C0>;
 635                 clock-names = "i2c";
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&i2c0_bus>;
 638                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 639                 status = "disabled";
 640         };
 641
 642         i2c_1: i2c@12C70000 {
 643                 compatible = "samsung,s3c2440-i2c";
 644                 reg = <0x12C70000 0x100>;
 645                 interrupts = <0 57 0>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 clocks = <&clock CLK_I2C1>;
 649                 clock-names = "i2c";
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&i2c1_bus>;
 652                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 653                 status = "disabled";
 654         };
 655
 656         i2c_2: i2c@12C80000 {
 657                 compatible = "samsung,s3c2440-i2c";
 658                 reg = <0x12C80000 0x100>;
 659                 interrupts = <0 58 0>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 clocks = <&clock CLK_I2C2>;
 663                 clock-names = "i2c";
 664                 pinctrl-names = "default";
 665                 pinctrl-0 = <&i2c2_bus>;
 666                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 667                 status = "disabled";
 668         };
 669
 670         i2c_3: i2c@12C90000 {
 671                 compatible = "samsung,s3c2440-i2c";
 672                 reg = <0x12C90000 0x100>;
 673                 interrupts = <0 59 0>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 clocks = <&clock CLK_I2C3>;
 677                 clock-names = "i2c";
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&i2c3_bus>;
 680                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 681                 status = "disabled";
 682         };
 683
 684         hsi2c_4: i2c@12CA0000 {
 685                 compatible = "samsung,exynos5-hsi2c";
 686                 reg = <0x12CA0000 0x1000>;
 687                 interrupts = <0 60 0>;
 688                 #address-cells = <1>;
 689                 #size-cells = <0>;
 690                 pinctrl-names = "default";
 691                 pinctrl-0 = <&i2c4_hs_bus>;
 692                 clocks = <&clock CLK_USI0>;
 693                 clock-names = "hsi2c";
 694                 status = "disabled";
 695         };
 696
 697         hsi2c_5: i2c@12CB0000 {
 698                 compatible = "samsung,exynos5-hsi2c";
 699                 reg = <0x12CB0000 0x1000>;
 700                 interrupts = <0 61 0>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&i2c5_hs_bus>;
 705                 clocks = <&clock CLK_USI1>;
 706                 clock-names = "hsi2c";
 707                 status = "disabled";
 708         };
 709
 710         hsi2c_6: i2c@12CC0000 {
 711                 compatible = "samsung,exynos5-hsi2c";
 712                 reg = <0x12CC0000 0x1000>;
 713                 interrupts = <0 62 0>;
 714                 #address-cells = <1>;
 715                 #size-cells = <0>;
 716                 pinctrl-names = "default";
 717                 pinctrl-0 = <&i2c6_hs_bus>;
 718                 clocks = <&clock CLK_USI2>;
 719                 clock-names = "hsi2c";
 720                 status = "disabled";
 721         };
 722
 723         hsi2c_7: i2c@12CD0000 {
 724                 compatible = "samsung,exynos5-hsi2c";
 725                 reg = <0x12CD0000 0x1000>;
 726                 interrupts = <0 63 0>;
 727                 #address-cells = <1>;
 728                 #size-cells = <0>;
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&i2c7_hs_bus>;
 731                 clocks = <&clock CLK_USI3>;
 732                 clock-names = "hsi2c";
 733                 status = "disabled";
 734         };
 735
 736         hsi2c_8: i2c@12E00000 {
 737                 compatible = "samsung,exynos5-hsi2c";
 738                 reg = <0x12E00000 0x1000>;
 739                 interrupts = <0 87 0>;
 740                 #address-cells = <1>;
 741                 #size-cells = <0>;
 742                 pinctrl-names = "default";
 743                 pinctrl-0 = <&i2c8_hs_bus>;
 744                 clocks = <&clock CLK_USI4>;
 745                 clock-names = "hsi2c";
 746                 status = "disabled";
 747         };
 748
 749         hsi2c_9: i2c@12E10000 {
 750                 compatible = "samsung,exynos5-hsi2c";
 751                 reg = <0x12E10000 0x1000>;
 752                 interrupts = <0 88 0>;
 753                 #address-cells = <1>;
 754                 #size-cells = <0>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&i2c9_hs_bus>;
 757                 clocks = <&clock CLK_USI5>;
 758                 clock-names = "hsi2c";
 759                 status = "disabled";
 760         };
 761
 762         hsi2c_10: i2c@12E20000 {
 763                 compatible = "samsung,exynos5-hsi2c";
 764                 reg = <0x12E20000 0x1000>;
 765                 interrupts = <0 203 0>;
 766                 #address-cells = <1>;
 767                 #size-cells = <0>;
 768                 pinctrl-names = "default";
 769                 pinctrl-0 = <&i2c10_hs_bus>;
 770                 clocks = <&clock CLK_USI6>;
 771                 clock-names = "hsi2c";
 772                 status = "disabled";
 773         };
 774
 775         hdmi: hdmi@14530000 {
 776                 compatible = "samsung,exynos5420-hdmi";
 777                 reg = <0x14530000 0x70000>;
 778                 interrupts = <0 95 0>;
 779                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 780                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 781                          <&clock CLK_MOUT_HDMI>;
 782                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 783                         "sclk_hdmiphy", "mout_hdmi";
 784                 phy = <&hdmiphy>;
 785                 samsung,syscon-phandle = <&pmu_system_controller>;
 786                 status = "disabled";
 787                 power-domains = <&disp_pd>;
 788         };
 789
 790         hdmiphy: hdmiphy@145D0000 {
 791                 reg = <0x145D0000 0x20>;
 792         };
 793
 794         mixer: mixer@14450000 {
 795                 compatible = "samsung,exynos5420-mixer";
 796                 reg = <0x14450000 0x10000>;
 797                 interrupts = <0 94 0>;
 798                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 799                          <&clock CLK_SCLK_HDMI>;
 800                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 801                 power-domains = <&disp_pd>;
 802                 iommus = <&sysmmu_tv>;
 803         };
 804
 805         rotator: rotator@11C00000 {
 806                 compatible = "samsung,exynos5250-rotator";
 807                 reg = <0x11C00000 0x64>;
 808                 interrupts = <0 84 0>;
 809                 clocks = <&clock CLK_ROTATOR>;
 810                 clock-names = "rotator";
 811                 iommus = <&sysmmu_rotator>;
 812         };
 813
 814         gsc_0: video-scaler@13e00000 {
 815                 compatible = "samsung,exynos5-gsc";
 816                 reg = <0x13e00000 0x1000>;
 817                 interrupts = <0 85 0>;
 818                 clocks = <&clock CLK_GSCL0>;
 819                 clock-names = "gscl";
 820                 power-domains = <&gsc_pd>;
 821                 iommus = <&sysmmu_gscl0>;
 822         };
 823
 824         gsc_1: video-scaler@13e10000 {
 825                 compatible = "samsung,exynos5-gsc";
 826                 reg = <0x13e10000 0x1000>;
 827                 interrupts = <0 86 0>;
 828                 clocks = <&clock CLK_GSCL1>;
 829                 clock-names = "gscl";
 830                 power-domains = <&gsc_pd>;
 831                 iommus = <&sysmmu_gscl1>;
 832         };
 833
 834         jpeg_0: jpeg@11F50000 {
 835                 compatible = "samsung,exynos5420-jpeg";
 836                 reg = <0x11F50000 0x1000>;
 837                 interrupts = <0 89 0>;
 838                 clock-names = "jpeg";
 839                 clocks = <&clock CLK_JPEG>;
 840                 iommus = <&sysmmu_jpeg0>;
 841         };
 842
 843         jpeg_1: jpeg@11F60000 {
 844                 compatible = "samsung,exynos5420-jpeg";
 845                 reg = <0x11F60000 0x1000>;
 846                 interrupts = <0 168 0>;
 847                 clock-names = "jpeg";
 848                 clocks = <&clock CLK_JPEG2>;
 849                 iommus = <&sysmmu_jpeg1>;
 850         };
 851
 852         pmu_system_controller: system-controller@10040000 {
 853                 compatible = "samsung,exynos5420-pmu", "syscon";
 854                 reg = <0x10040000 0x5000>;
 855                 clock-names = "clkout16";
 856                 clocks = <&clock CLK_FIN_PLL>;
 857                 #clock-cells = <1>;
 858                 interrupt-controller;
 859                 #interrupt-cells = <3>;
 860                 interrupt-parent = <&gic>;
 861         };
 862
 863         sysreg_system_controller: syscon@10050000 {
 864                 compatible = "samsung,exynos5-sysreg", "syscon";
 865                 reg = <0x10050000 0x5000>;
 866         };
 867
 868         tmu_cpu0: tmu@10060000 {
 869                 compatible = "samsung,exynos5420-tmu";
 870                 reg = <0x10060000 0x100>;
 871                 interrupts = <0 65 0>;
 872                 clocks = <&clock CLK_TMU>;
 873                 clock-names = "tmu_apbif";
 874                 #include "exynos4412-tmu-sensor-conf.dtsi"
 875         };
 876
 877         tmu_cpu1: tmu@10064000 {
 878                 compatible = "samsung,exynos5420-tmu";
 879                 reg = <0x10064000 0x100>;
 880                 interrupts = <0 183 0>;
 881                 clocks = <&clock CLK_TMU>;
 882                 clock-names = "tmu_apbif";
 883                 #include "exynos4412-tmu-sensor-conf.dtsi"
 884         };
 885
 886         tmu_cpu2: tmu@10068000 {
 887                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 888                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 889                 interrupts = <0 184 0>;
 890                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 891                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 892                 #include "exynos4412-tmu-sensor-conf.dtsi"
 893         };
 894
 895         tmu_cpu3: tmu@1006c000 {
 896                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 897                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 898                 interrupts = <0 185 0>;
 899                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 900                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 901                 #include "exynos4412-tmu-sensor-conf.dtsi"
 902         };
 903
 904         tmu_gpu: tmu@100a0000 {
 905                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 906                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 907                 interrupts = <0 215 0>;
 908                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 909                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 910                 #include "exynos4412-tmu-sensor-conf.dtsi"
 911         };
 912
 913         thermal-zones {
 914                 cpu0_thermal: cpu0-thermal {
 915                         thermal-sensors = <&tmu_cpu0>;
 916                         #include "exynos5420-trip-points.dtsi"
 917                 };
 918                 cpu1_thermal: cpu1-thermal {
 919                        thermal-sensors = <&tmu_cpu1>;
 920                        #include "exynos5420-trip-points.dtsi"
 921                 };
 922                 cpu2_thermal: cpu2-thermal {
 923                        thermal-sensors = <&tmu_cpu2>;
 924                        #include "exynos5420-trip-points.dtsi"
 925                 };
 926                 cpu3_thermal: cpu3-thermal {
 927                        thermal-sensors = <&tmu_cpu3>;
 928                        #include "exynos5420-trip-points.dtsi"
 929                 };
 930                 gpu_thermal: gpu-thermal {
 931                        thermal-sensors = <&tmu_gpu>;
 932                        #include "exynos5420-trip-points.dtsi"
 933                 };
 934         };
 935
 936         watchdog: watchdog@101D0000 {
 937                 compatible = "samsung,exynos5420-wdt";
 938                 reg = <0x101D0000 0x100>;
 939                 interrupts = <0 42 0>;
 940                 clocks = <&clock CLK_WDT>;
 941                 clock-names = "watchdog";
 942                 samsung,syscon-phandle = <&pmu_system_controller>;
 943         };
 944
 945         sss: sss@10830000 {
 946                 compatible = "samsung,exynos4210-secss";
 947                 reg = <0x10830000 0x300>;
 948                 interrupts = <0 112 0>;
 949                 clocks = <&clock CLK_SSS>;
 950                 clock-names = "secss";
 951         };
 952
 953         usbdrd3_0: usb3-0 {
 954                 compatible = "samsung,exynos5250-dwusb3";
 955                 clocks = <&clock CLK_USBD300>;
 956                 clock-names = "usbdrd30";
 957                 #address-cells = <1>;
 958                 #size-cells = <1>;
 959                 ranges;
 960
 961                 usbdrd_dwc3_0: dwc3@12000000 {
 962                         compatible = "snps,dwc3";
 963                         reg = <0x12000000 0x10000>;
 964                         interrupts = <0 72 0>;
 965                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 966                         phy-names = "usb2-phy", "usb3-phy";
 967                 };
 968         };
 969
 970         usbdrd_phy0: phy@12100000 {
 971                 compatible = "samsung,exynos5420-usbdrd-phy";
 972                 reg = <0x12100000 0x100>;
 973                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 974                 clock-names = "phy", "ref";
 975                 samsung,pmu-syscon = <&pmu_system_controller>;
 976                 #phy-cells = <1>;
 977         };
 978
 979         usbdrd3_1: usb3-1 {
 980                 compatible = "samsung,exynos5250-dwusb3";
 981                 clocks = <&clock CLK_USBD301>;
 982                 clock-names = "usbdrd30";
 983                 #address-cells = <1>;
 984                 #size-cells = <1>;
 985                 ranges;
 986
 987                 usbdrd_dwc3_1: dwc3@12400000 {
 988                         compatible = "snps,dwc3";
 989                         reg = <0x12400000 0x10000>;
 990                         interrupts = <0 73 0>;
 991                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 992                         phy-names = "usb2-phy", "usb3-phy";
 993                 };
 994         };
 995
 996         usbdrd_phy1: phy@12500000 {
 997                 compatible = "samsung,exynos5420-usbdrd-phy";
 998                 reg = <0x12500000 0x100>;
 999                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1000                 clock-names = "phy", "ref";
1001                 samsung,pmu-syscon = <&pmu_system_controller>;
1002                 #phy-cells = <1>;
1003         };
1004
1005         usbhost2: usb@12110000 {
1006                 compatible = "samsung,exynos4210-ehci";
1007                 reg = <0x12110000 0x100>;
1008                 interrupts = <0 71 0>;
1009
1010                 clocks = <&clock CLK_USBH20>;
1011                 clock-names = "usbhost";
1012                 #address-cells = <1>;
1013                 #size-cells = <0>;
1014                 port@0 {
1015                         reg = <0>;
1016                         phys = <&usb2_phy 1>;
1017                 };
1018         };
1019
1020         usbhost1: usb@12120000 {
1021                 compatible = "samsung,exynos4210-ohci";
1022                 reg = <0x12120000 0x100>;
1023                 interrupts = <0 71 0>;
1024
1025                 clocks = <&clock CLK_USBH20>;
1026                 clock-names = "usbhost";
1027                 #address-cells = <1>;
1028                 #size-cells = <0>;
1029                 port@0 {
1030                         reg = <0>;
1031                         phys = <&usb2_phy 1>;
1032                 };
1033         };
1034
1035         usb2_phy: phy@12130000 {
1036                 compatible = "samsung,exynos5250-usb2-phy";
1037                 reg = <0x12130000 0x100>;
1038                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1039                 clock-names = "phy", "ref";
1040                 #phy-cells = <1>;
1041                 samsung,sysreg-phandle = <&sysreg_system_controller>;
1042                 samsung,pmureg-phandle = <&pmu_system_controller>;
1043         };
1044
1045         sysmmu_g2dr: sysmmu@0x10A60000 {
1046                 compatible = "samsung,exynos-sysmmu";
1047                 reg = <0x10A60000 0x1000>;
1048                 interrupt-parent = <&combiner>;
1049                 interrupts = <24 5>;
1050                 clock-names = "sysmmu", "master";
1051                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1052                 #iommu-cells = <0>;
1053         };
1054
1055         sysmmu_g2dw: sysmmu@0x10A70000 {
1056                 compatible = "samsung,exynos-sysmmu";
1057                 reg = <0x10A70000 0x1000>;
1058                 interrupt-parent = <&combiner>;
1059                 interrupts = <22 2>;
1060                 clock-names = "sysmmu", "master";
1061                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1062                 #iommu-cells = <0>;
1063         };
1064
1065         sysmmu_tv: sysmmu@0x14650000 {
1066                 compatible = "samsung,exynos-sysmmu";
1067                 reg = <0x14650000 0x1000>;
1068                 interrupt-parent = <&combiner>;
1069                 interrupts = <7 4>;
1070                 clock-names = "sysmmu", "master";
1071                 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1072                 power-domains = <&disp_pd>;
1073                 #iommu-cells = <0>;
1074         };
1075
1076         sysmmu_gscl0: sysmmu@0x13E80000 {
1077                 compatible = "samsung,exynos-sysmmu";
1078                 reg = <0x13E80000 0x1000>;
1079                 interrupt-parent = <&combiner>;
1080                 interrupts = <2 0>;
1081                 clock-names = "sysmmu", "master";
1082                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1083                 power-domains = <&gsc_pd>;
1084                 #iommu-cells = <0>;
1085         };
1086
1087         sysmmu_gscl1: sysmmu@0x13E90000 {
1088                 compatible = "samsung,exynos-sysmmu";
1089                 reg = <0x13E90000 0x1000>;
1090                 interrupt-parent = <&combiner>;
1091                 interrupts = <2 2>;
1092                 clock-names = "sysmmu", "master";
1093                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1094                 power-domains = <&gsc_pd>;
1095                 #iommu-cells = <0>;
1096         };
1097
1098         sysmmu_scaler0r: sysmmu@0x12880000 {
1099                 compatible = "samsung,exynos-sysmmu";
1100                 reg = <0x12880000 0x1000>;
1101                 interrupt-parent = <&combiner>;
1102                 interrupts = <22 4>;
1103                 clock-names = "sysmmu", "master";
1104                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1105                 #iommu-cells = <0>;
1106         };
1107
1108         sysmmu_scaler1r: sysmmu@0x12890000 {
1109                 compatible = "samsung,exynos-sysmmu";
1110                 reg = <0x12890000 0x1000>;
1111                 interrupts = <0 186 0>;
1112                 clock-names = "sysmmu", "master";
1113                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1114                 #iommu-cells = <0>;
1115         };
1116
1117         sysmmu_scaler2r: sysmmu@0x128A0000 {
1118                 compatible = "samsung,exynos-sysmmu";
1119                 reg = <0x128A0000 0x1000>;
1120                 interrupts = <0 188 0>;
1121                 clock-names = "sysmmu", "master";
1122                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1123                 #iommu-cells = <0>;
1124         };
1125
1126         sysmmu_scaler0w: sysmmu@0x128C0000 {
1127                 compatible = "samsung,exynos-sysmmu";
1128                 reg = <0x128C0000 0x1000>;
1129                 interrupt-parent = <&combiner>;
1130                 interrupts = <27 2>;
1131                 clock-names = "sysmmu", "master";
1132                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1133                 #iommu-cells = <0>;
1134         };
1135
1136         sysmmu_scaler1w: sysmmu@0x128D0000 {
1137                 compatible = "samsung,exynos-sysmmu";
1138                 reg = <0x128D0000 0x1000>;
1139                 interrupt-parent = <&combiner>;
1140                 interrupts = <22 6>;
1141                 clock-names = "sysmmu", "master";
1142                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1143                 #iommu-cells = <0>;
1144         };
1145
1146         sysmmu_scaler2w: sysmmu@0x128E0000 {
1147                 compatible = "samsung,exynos-sysmmu";
1148                 reg = <0x128E0000 0x1000>;
1149                 interrupt-parent = <&combiner>;
1150                 interrupts = <19 6>;
1151                 clock-names = "sysmmu", "master";
1152                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1153                 #iommu-cells = <0>;
1154         };
1155
1156         sysmmu_rotator: sysmmu@0x11D40000 {
1157                 compatible = "samsung,exynos-sysmmu";
1158                 reg = <0x11D40000 0x1000>;
1159                 interrupt-parent = <&combiner>;
1160                 interrupts = <4 0>;
1161                 clock-names = "sysmmu", "master";
1162                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1163                 #iommu-cells = <0>;
1164         };
1165
1166         sysmmu_jpeg0: sysmmu@0x11F10000 {
1167                 compatible = "samsung,exynos-sysmmu";
1168                 reg = <0x11F10000 0x1000>;
1169                 interrupt-parent = <&combiner>;
1170                 interrupts = <4 2>;
1171                 clock-names = "sysmmu", "master";
1172                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1173                 #iommu-cells = <0>;
1174         };
1175
1176         sysmmu_jpeg1: sysmmu@0x11F20000 {
1177                 compatible = "samsung,exynos-sysmmu";
1178                 reg = <0x11F20000 0x1000>;
1179                 interrupts = <0 169 0>;
1180                 clock-names = "sysmmu", "master";
1181                 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1182                 #iommu-cells = <0>;
1183         };
1184
1185         sysmmu_mfc_l: sysmmu@0x11200000 {
1186                 compatible = "samsung,exynos-sysmmu";
1187                 reg = <0x11200000 0x1000>;
1188                 interrupt-parent = <&combiner>;
1189                 interrupts = <6 2>;
1190                 clock-names = "sysmmu", "master";
1191                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1192                 power-domains = <&mfc_pd>;
1193                 #iommu-cells = <0>;
1194         };
1195
1196         sysmmu_mfc_r: sysmmu@0x11210000 {
1197                 compatible = "samsung,exynos-sysmmu";
1198                 reg = <0x11210000 0x1000>;
1199                 interrupt-parent = <&combiner>;
1200                 interrupts = <8 5>;
1201                 clock-names = "sysmmu", "master";
1202                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1203                 power-domains = <&mfc_pd>;
1204                 #iommu-cells = <0>;
1205         };
1206
1207         sysmmu_fimd1_0: sysmmu@0x14640000 {
1208                 compatible = "samsung,exynos-sysmmu";
1209                 reg = <0x14640000 0x1000>;
1210                 interrupt-parent = <&combiner>;
1211                 interrupts = <3 2>;
1212                 clock-names = "sysmmu", "master";
1213                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1214                 power-domains = <&disp_pd>;
1215                 #iommu-cells = <0>;
1216         };
1217
1218         sysmmu_fimd1_1: sysmmu@0x14680000 {
1219                 compatible = "samsung,exynos-sysmmu";
1220                 reg = <0x14680000 0x1000>;
1221                 interrupt-parent = <&combiner>;
1222                 interrupts = <3 0>;
1223                 clock-names = "sysmmu", "master";
1224                 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1225                 power-domains = <&disp_pd>;
1226                 #iommu-cells = <0>;
1227         };
1228
1229         bus_wcore: bus_wcore {
1230                 compatible = "samsung,exynos-bus";
1231                 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1232                 clock-names = "bus";
1233                 operating-points-v2 = <&bus_wcore_opp_table>;
1234                 status = "disabled";
1235         };
1236
1237         bus_noc: bus_noc {
1238                 compatible = "samsung,exynos-bus";
1239                 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1240                 clock-names = "bus";
1241                 operating-points-v2 = <&bus_noc_opp_table>;
1242                 status = "disabled";
1243         };
1244
1245         bus_fsys_apb: bus_fsys_apb {
1246                 compatible = "samsung,exynos-bus";
1247                 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1248                 clock-names = "bus";
1249                 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1250                 status = "disabled";
1251         };
1252
1253         bus_fsys: bus_fsys {
1254                 compatible = "samsung,exynos-bus";
1255                 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1256                 clock-names = "bus";
1257                 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1258                 status = "disabled";
1259         };
1260
1261         bus_fsys2: bus_fsys2 {
1262                 compatible = "samsung,exynos-bus";
1263                 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1264                 clock-names = "bus";
1265                 operating-points-v2 = <&bus_fsys2_opp_table>;
1266                 status = "disabled";
1267         };
1268
1269         bus_mfc: bus_mfc {
1270                 compatible = "samsung,exynos-bus";
1271                 clocks = <&clock CLK_DOUT_ACLK333>;
1272                 clock-names = "bus";
1273                 operating-points-v2 = <&bus_mfc_opp_table>;
1274                 status = "disabled";
1275         };
1276
1277         bus_gen: bus_gen {
1278                 compatible = "samsung,exynos-bus";
1279                 clocks = <&clock CLK_DOUT_ACLK266>;
1280                 clock-names = "bus";
1281                 operating-points-v2 = <&bus_gen_opp_table>;
1282                 status = "disabled";
1283         };
1284
1285         bus_peri: bus_peri {
1286                 compatible = "samsung,exynos-bus";
1287                 clocks = <&clock CLK_DOUT_ACLK66>;
1288                 clock-names = "bus";
1289                 operating-points-v2 = <&bus_peri_opp_table>;
1290                 status = "disabled";
1291         };
1292
1293         bus_g2d: bus_g2d {
1294                 compatible = "samsung,exynos-bus";
1295                 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1296                 clock-names = "bus";
1297                 operating-points-v2 = <&bus_g2d_opp_table>;
1298                 status = "disabled";
1299         };
1300
1301         bus_g2d_acp: bus_g2d_acp {
1302                 compatible = "samsung,exynos-bus";
1303                 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1304                 clock-names = "bus";
1305                 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1306                 status = "disabled";
1307         };
1308
1309         bus_jpeg: bus_jpeg {
1310                 compatible = "samsung,exynos-bus";
1311                 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1312                 clock-names = "bus";
1313                 operating-points-v2 = <&bus_jpeg_opp_table>;
1314                 status = "disabled";
1315         };
1316
1317         bus_jpeg_apb: bus_jpeg_apb {
1318                 compatible = "samsung,exynos-bus";
1319                 clocks = <&clock CLK_DOUT_ACLK166>;
1320                 clock-names = "bus";
1321                 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1322                 status = "disabled";
1323         };
1324
1325         bus_disp1_fimd: bus_disp1_fimd {
1326                 compatible = "samsung,exynos-bus";
1327                 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1328                 clock-names = "bus";
1329                 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1330                 status = "disabled";
1331         };
1332
1333         bus_disp1: bus_disp1 {
1334                 compatible = "samsung,exynos-bus";
1335                 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1336                 clock-names = "bus";
1337                 operating-points-v2 = <&bus_disp1_opp_table>;
1338                 status = "disabled";
1339         };
1340
1341         bus_gscl_scaler: bus_gscl_scaler {
1342                 compatible = "samsung,exynos-bus";
1343                 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1344                 clock-names = "bus";
1345                 operating-points-v2 = <&bus_gscl_opp_table>;
1346                 status = "disabled";
1347         };
1348
1349         bus_mscl: bus_mscl {
1350                 compatible = "samsung,exynos-bus";
1351                 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1352                 clock-names = "bus";
1353                 operating-points-v2 = <&bus_mscl_opp_table>;
1354                 status = "disabled";
1355         };
1356
1357         bus_wcore_opp_table: opp_table2 {
1358                 compatible = "operating-points-v2";
1359
1360                 opp00 {
1361                         opp-hz = /bits/ 64 <84000000>;
1362                         opp-microvolt = <925000>;
1363                 };
1364                 opp01 {
1365                         opp-hz = /bits/ 64 <111000000>;
1366                         opp-microvolt = <950000>;
1367                 };
1368                 opp02 {
1369                         opp-hz = /bits/ 64 <222000000>;
1370                         opp-microvolt = <950000>;
1371                 };
1372                 opp03 {
1373                         opp-hz = /bits/ 64 <333000000>;
1374                         opp-microvolt = <950000>;
1375                 };
1376                 opp04 {
1377                         opp-hz = /bits/ 64 <400000000>;
1378                         opp-microvolt = <987500>;
1379                 };
1380         };
1381
1382         bus_noc_opp_table: opp_table3 {
1383                 compatible = "operating-points-v2";
1384
1385                 opp00 {
1386                         opp-hz = /bits/ 64 <67000000>;
1387                 };
1388                 opp01 {
1389                         opp-hz = /bits/ 64 <75000000>;
1390                 };
1391                 opp02 {
1392                         opp-hz = /bits/ 64 <86000000>;
1393                 };
1394                 opp03 {
1395                         opp-hz = /bits/ 64 <100000000>;
1396                 };
1397         };
1398
1399         bus_fsys_apb_opp_table: opp_table4 {
1400                 compatible = "operating-points-v2";
1401                 opp-shared;
1402
1403                 opp00 {
1404                         opp-hz = /bits/ 64 <100000000>;
1405                 };
1406                 opp01 {
1407                         opp-hz = /bits/ 64 <200000000>;
1408                 };
1409         };
1410
1411         bus_fsys2_opp_table: opp_table5 {
1412                 compatible = "operating-points-v2";
1413
1414                 opp00 {
1415                         opp-hz = /bits/ 64 <75000000>;
1416                 };
1417                 opp01 {
1418                         opp-hz = /bits/ 64 <100000000>;
1419                 };
1420                 opp02 {
1421                         opp-hz = /bits/ 64 <150000000>;
1422                 };
1423         };
1424
1425         bus_mfc_opp_table: opp_table6 {
1426                 compatible = "operating-points-v2";
1427
1428                 opp00 {
1429                         opp-hz = /bits/ 64 <96000000>;
1430                 };
1431                 opp01 {
1432                         opp-hz = /bits/ 64 <111000000>;
1433                 };
1434                 opp02 {
1435                         opp-hz = /bits/ 64 <167000000>;
1436                 };
1437                 opp03 {
1438                         opp-hz = /bits/ 64 <222000000>;
1439                 };
1440                 opp04 {
1441                         opp-hz = /bits/ 64 <333000000>;
1442                 };
1443         };
1444
1445         bus_gen_opp_table: opp_table7 {
1446                 compatible = "operating-points-v2";
1447
1448                 opp00 {
1449                         opp-hz = /bits/ 64 <89000000>;
1450                 };
1451                 opp01 {
1452                         opp-hz = /bits/ 64 <133000000>;
1453                 };
1454                 opp02 {
1455                         opp-hz = /bits/ 64 <178000000>;
1456                 };
1457                 opp03 {
1458                         opp-hz = /bits/ 64 <267000000>;
1459                 };
1460         };
1461
1462         bus_peri_opp_table: opp_table8 {
1463                 compatible = "operating-points-v2";
1464
1465                 opp00 {
1466                         opp-hz = /bits/ 64 <67000000>;
1467                 };
1468         };
1469
1470         bus_g2d_opp_table: opp_table9 {
1471                 compatible = "operating-points-v2";
1472
1473                 opp00 {
1474                         opp-hz = /bits/ 64 <84000000>;
1475                 };
1476                 opp01 {
1477                         opp-hz = /bits/ 64 <167000000>;
1478                 };
1479                 opp02 {
1480                         opp-hz = /bits/ 64 <222000000>;
1481                 };
1482                 opp03 {
1483                         opp-hz = /bits/ 64 <300000000>;
1484                 };
1485                 opp04 {
1486                         opp-hz = /bits/ 64 <333000000>;
1487                 };
1488         };
1489
1490         bus_g2d_acp_opp_table: opp_table10 {
1491                 compatible = "operating-points-v2";
1492
1493                 opp00 {
1494                         opp-hz = /bits/ 64 <67000000>;
1495                 };
1496                 opp01 {
1497                         opp-hz = /bits/ 64 <133000000>;
1498                 };
1499                 opp02 {
1500                         opp-hz = /bits/ 64 <178000000>;
1501                 };
1502                 opp03 {
1503                         opp-hz = /bits/ 64 <267000000>;
1504                 };
1505         };
1506
1507         bus_jpeg_opp_table: opp_table11 {
1508                 compatible = "operating-points-v2";
1509
1510                 opp00 {
1511                         opp-hz = /bits/ 64 <75000000>;
1512                 };
1513                 opp01 {
1514                         opp-hz = /bits/ 64 <150000000>;
1515                 };
1516                 opp02 {
1517                         opp-hz = /bits/ 64 <200000000>;
1518                 };
1519                 opp03 {
1520                         opp-hz = /bits/ 64 <300000000>;
1521                 };
1522         };
1523
1524         bus_jpeg_apb_opp_table: opp_table12 {
1525                 compatible = "operating-points-v2";
1526
1527                 opp00 {
1528                         opp-hz = /bits/ 64 <84000000>;
1529                 };
1530                 opp01 {
1531                         opp-hz = /bits/ 64 <111000000>;
1532                 };
1533                 opp02 {
1534                         opp-hz = /bits/ 64 <134000000>;
1535                 };
1536                 opp03 {
1537                         opp-hz = /bits/ 64 <167000000>;
1538                 };
1539         };
1540
1541         bus_disp1_fimd_opp_table: opp_table13 {
1542                 compatible = "operating-points-v2";
1543
1544                 opp00 {
1545                         opp-hz = /bits/ 64 <120000000>;
1546                 };
1547                 opp01 {
1548                         opp-hz = /bits/ 64 <200000000>;
1549                 };
1550         };
1551
1552         bus_disp1_opp_table: opp_table14 {
1553                 compatible = "operating-points-v2";
1554
1555                 opp00 {
1556                         opp-hz = /bits/ 64 <120000000>;
1557                 };
1558                 opp01 {
1559                         opp-hz = /bits/ 64 <200000000>;
1560                 };
1561                 opp02 {
1562                         opp-hz = /bits/ 64 <300000000>;
1563                 };
1564         };
1565
1566         bus_gscl_opp_table: opp_table15 {
1567                 compatible = "operating-points-v2";
1568
1569                 opp00 {
1570                         opp-hz = /bits/ 64 <150000000>;
1571                 };
1572                 opp01 {
1573                         opp-hz = /bits/ 64 <200000000>;
1574                 };
1575                 opp02 {
1576                         opp-hz = /bits/ 64 <300000000>;
1577                 };
1578         };
1579
1580         bus_mscl_opp_table: opp_table16 {
1581                 compatible = "operating-points-v2";
1582
1583                 opp00 {
1584                         opp-hz = /bits/ 64 <84000000>;
1585                 };
1586                 opp01 {
1587                         opp-hz = /bits/ 64 <167000000>;
1588                 };
1589                 opp02 {
1590                         opp-hz = /bits/ 64 <222000000>;
1591                 };
1592                 opp03 {
1593                         opp-hz = /bits/ 64 <333000000>;
1594                 };
1595                 opp04 {
1596                         opp-hz = /bits/ 64 <400000000>;
1597                 };
1598         };
1599 };
1600
1601 &dp {
1602         clocks = <&clock CLK_DP1>;
1603         clock-names = "dp";
1604         phys = <&dp_phy>;
1605         phy-names = "dp";
1606         power-domains = <&disp_pd>;
1607 };
1608
1609 &fimd {
1610         compatible = "samsung,exynos5420-fimd";
1611         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1612         clock-names = "sclk_fimd", "fimd";
1613         power-domains = <&disp_pd>;
1614         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1615         iommu-names = "m0", "m1";
1616 };
1617
1618 &rtc {
1619         clocks = <&clock CLK_RTC>;
1620         clock-names = "rtc";
1621         interrupt-parent = <&pmu_system_controller>;
1622         status = "disabled";
1623 };
1624
1625 &serial_0 {
1626         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1627         clock-names = "uart", "clk_uart_baud0";
1628 };
1629
1630 &serial_1 {
1631         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1632         clock-names = "uart", "clk_uart_baud0";
1633 };
1634
1635 &serial_2 {
1636         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1637         clock-names = "uart", "clk_uart_baud0";
1638 };
1639
1640 &serial_3 {
1641         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1642         clock-names = "uart", "clk_uart_baud0";
1643 };
1644
1645 #include "exynos5420-pinctrl.dtsi"