2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
14 #include "skeleton.dtsi"
20 compatible = "ti,omap5";
21 interrupt-parent = <&wakeupgen>;
43 compatible = "arm,cortex-a15";
52 clocks = <&dpll_mpu_ck>;
55 clock-latency = <300000>; /* From omap-cpufreq driver */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
64 compatible = "arm,cortex-a15";
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
76 compatible = "arm,armv7-timer";
77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
82 interrupt-parent = <&gic>;
86 compatible = "arm,cortex-a15-pmu";
87 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
91 gic: interrupt-controller@48211000 {
92 compatible = "arm,cortex-a15-gic";
94 #interrupt-cells = <3>;
95 reg = <0x48211000 0x1000>,
99 interrupt-parent = <&gic>;
102 wakeupgen: interrupt-controller@48281000 {
103 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0x48281000 0x1000>;
107 interrupt-parent = <&gic>;
111 * The soc node represents the soc top level view. It is used for IPs
112 * that are not memory mapped in the MPU view or for the MPU itself.
115 compatible = "ti,omap-infra";
117 compatible = "ti,omap4-mpu";
124 * XXX: Use a flat representation of the OMAP3 interconnect.
125 * The real OMAP interconnect network is quite complex.
126 * Since it will not bring real advantage to represent that in DT for
127 * the moment, just use a fake OCP bus entry to represent the whole bus
131 compatible = "ti,omap5-l3-noc", "simple-bus";
132 #address-cells = <1>;
135 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
136 reg = <0x44000000 0x2000>,
139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
142 l4_cfg: l4@4a000000 {
143 compatible = "ti,omap5-l4-cfg", "simple-bus";
144 #address-cells = <1>;
146 ranges = <0 0x4a000000 0x22a000>;
149 compatible = "ti,omap5-scm-core", "simple-bus";
150 reg = <0x2000 0x1000>;
151 #address-cells = <1>;
153 ranges = <0 0x2000 0x800>;
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
158 #address-cells = <1>;
163 scm_padconf_core: scm@2800 {
164 compatible = "ti,omap5-scm-padconf-core",
166 #address-cells = <1>;
168 ranges = <0 0x2800 0x800>;
170 omap5_pmx_core: pinmux@40 {
171 compatible = "ti,omap5-padconf",
174 #address-cells = <1>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
182 omap5_padconf_global: omap5_padconf_global@5a0 {
183 compatible = "syscon";
185 #address-cells = <1>;
188 pbias_regulator: pbias_regulator {
189 compatible = "ti,pbias-omap";
191 syscon = <&omap5_padconf_global>;
192 pbias_mmc_reg: pbias_mmc_omap5 {
193 regulator-name = "pbias_mmc_omap5";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <3000000>;
201 cm_core_aon: cm_core_aon@4000 {
202 compatible = "ti,omap5-cm-core-aon";
203 reg = <0x4000 0x2000>;
205 cm_core_aon_clocks: clocks {
206 #address-cells = <1>;
210 cm_core_aon_clockdomains: clockdomains {
214 cm_core: cm_core@8000 {
215 compatible = "ti,omap5-cm-core";
216 reg = <0x8000 0x3000>;
218 cm_core_clocks: clocks {
219 #address-cells = <1>;
223 cm_core_clockdomains: clockdomains {
228 l4_wkup: l4@4ae00000 {
229 compatible = "ti,omap5-l4-wkup", "simple-bus";
230 #address-cells = <1>;
232 ranges = <0 0x4ae00000 0x2b000>;
234 counter32k: counter@4000 {
235 compatible = "ti,omap-counter32k";
237 ti,hwmods = "counter_32k";
241 compatible = "ti,omap5-prm";
242 reg = <0x6000 0x3000>;
243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>;
250 prm_clockdomains: clockdomains {
255 compatible = "ti,omap5-scrm";
256 reg = <0xa000 0x2000>;
258 scrm_clocks: clocks {
259 #address-cells = <1>;
263 scrm_clockdomains: clockdomains {
267 omap5_pmx_wkup: pinmux@c840 {
268 compatible = "ti,omap5-padconf",
270 reg = <0xc840 0x0038>;
271 #address-cells = <1>;
273 #interrupt-cells = <1>;
274 interrupt-controller;
275 pinctrl-single,register-width = <16>;
276 pinctrl-single,function-mask = <0x7fff>;
280 ocmcram: ocmcram@40300000 {
281 compatible = "mmio-sram";
282 reg = <0x40300000 0x20000>; /* 128k */
285 sdma: dma-controller@4a056000 {
286 compatible = "ti,omap4430-sdma";
287 reg = <0x4a056000 0x1000>;
288 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
294 dma-requests = <127>;
297 gpio1: gpio@4ae10000 {
298 compatible = "ti,omap4-gpio";
299 reg = <0x4ae10000 0x200>;
300 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
309 gpio2: gpio@48055000 {
310 compatible = "ti,omap4-gpio";
311 reg = <0x48055000 0x200>;
312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
320 gpio3: gpio@48057000 {
321 compatible = "ti,omap4-gpio";
322 reg = <0x48057000 0x200>;
323 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
331 gpio4: gpio@48059000 {
332 compatible = "ti,omap4-gpio";
333 reg = <0x48059000 0x200>;
334 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
342 gpio5: gpio@4805b000 {
343 compatible = "ti,omap4-gpio";
344 reg = <0x4805b000 0x200>;
345 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
353 gpio6: gpio@4805d000 {
354 compatible = "ti,omap4-gpio";
355 reg = <0x4805d000 0x200>;
356 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
364 gpio7: gpio@48051000 {
365 compatible = "ti,omap4-gpio";
366 reg = <0x48051000 0x200>;
367 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
375 gpio8: gpio@48053000 {
376 compatible = "ti,omap4-gpio";
377 reg = <0x48053000 0x200>;
378 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
386 gpmc: gpmc@50000000 {
387 compatible = "ti,omap4430-gpmc";
388 reg = <0x50000000 0x1000>;
389 #address-cells = <2>;
391 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
393 gpmc,num-waitpins = <4>;
395 clocks = <&l3_iclk_div>;
400 compatible = "ti,omap4-i2c";
401 reg = <0x48070000 0x100>;
402 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
409 compatible = "ti,omap4-i2c";
410 reg = <0x48072000 0x100>;
411 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
418 compatible = "ti,omap4-i2c";
419 reg = <0x48060000 0x100>;
420 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>;
427 compatible = "ti,omap4-i2c";
428 reg = <0x4807a000 0x100>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
436 compatible = "ti,omap4-i2c";
437 reg = <0x4807c000 0x100>;
438 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
444 hwspinlock: spinlock@4a0f6000 {
445 compatible = "ti,omap4-hwspinlock";
446 reg = <0x4a0f6000 0x1000>;
447 ti,hwmods = "spinlock";
451 mcspi1: spi@48098000 {
452 compatible = "ti,omap4-mcspi";
453 reg = <0x48098000 0x200>;
454 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
457 ti,hwmods = "mcspi1";
467 dma-names = "tx0", "rx0", "tx1", "rx1",
468 "tx2", "rx2", "tx3", "rx3";
471 mcspi2: spi@4809a000 {
472 compatible = "ti,omap4-mcspi";
473 reg = <0x4809a000 0x200>;
474 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
477 ti,hwmods = "mcspi2";
483 dma-names = "tx0", "rx0", "tx1", "rx1";
486 mcspi3: spi@480b8000 {
487 compatible = "ti,omap4-mcspi";
488 reg = <0x480b8000 0x200>;
489 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
492 ti,hwmods = "mcspi3";
494 dmas = <&sdma 15>, <&sdma 16>;
495 dma-names = "tx0", "rx0";
498 mcspi4: spi@480ba000 {
499 compatible = "ti,omap4-mcspi";
500 reg = <0x480ba000 0x200>;
501 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
504 ti,hwmods = "mcspi4";
506 dmas = <&sdma 70>, <&sdma 71>;
507 dma-names = "tx0", "rx0";
510 uart1: serial@4806a000 {
511 compatible = "ti,omap4-uart";
512 reg = <0x4806a000 0x100>;
513 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
515 clock-frequency = <48000000>;
518 uart2: serial@4806c000 {
519 compatible = "ti,omap4-uart";
520 reg = <0x4806c000 0x100>;
521 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
523 clock-frequency = <48000000>;
526 uart3: serial@48020000 {
527 compatible = "ti,omap4-uart";
528 reg = <0x48020000 0x100>;
529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
531 clock-frequency = <48000000>;
534 uart4: serial@4806e000 {
535 compatible = "ti,omap4-uart";
536 reg = <0x4806e000 0x100>;
537 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
539 clock-frequency = <48000000>;
542 uart5: serial@48066000 {
543 compatible = "ti,omap4-uart";
544 reg = <0x48066000 0x100>;
545 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
547 clock-frequency = <48000000>;
550 uart6: serial@48068000 {
551 compatible = "ti,omap4-uart";
552 reg = <0x48068000 0x100>;
553 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
555 clock-frequency = <48000000>;
559 compatible = "ti,omap4-hsmmc";
560 reg = <0x4809c000 0x400>;
561 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
564 ti,needs-special-reset;
565 dmas = <&sdma 61>, <&sdma 62>;
566 dma-names = "tx", "rx";
567 pbias-supply = <&pbias_mmc_reg>;
571 compatible = "ti,omap4-hsmmc";
572 reg = <0x480b4000 0x400>;
573 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
575 ti,needs-special-reset;
576 dmas = <&sdma 47>, <&sdma 48>;
577 dma-names = "tx", "rx";
581 compatible = "ti,omap4-hsmmc";
582 reg = <0x480ad000 0x400>;
583 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
585 ti,needs-special-reset;
586 dmas = <&sdma 77>, <&sdma 78>;
587 dma-names = "tx", "rx";
591 compatible = "ti,omap4-hsmmc";
592 reg = <0x480d1000 0x400>;
593 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
595 ti,needs-special-reset;
596 dmas = <&sdma 57>, <&sdma 58>;
597 dma-names = "tx", "rx";
601 compatible = "ti,omap4-hsmmc";
602 reg = <0x480d5000 0x400>;
603 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
605 ti,needs-special-reset;
606 dmas = <&sdma 59>, <&sdma 60>;
607 dma-names = "tx", "rx";
610 mmu_dsp: mmu@4a066000 {
611 compatible = "ti,omap4-iommu";
612 reg = <0x4a066000 0x100>;
613 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
614 ti,hwmods = "mmu_dsp";
617 mmu_ipu: mmu@55082000 {
618 compatible = "ti,omap4-iommu";
619 reg = <0x55082000 0x100>;
620 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
621 ti,hwmods = "mmu_ipu";
622 ti,iommu-bus-err-back;
625 keypad: keypad@4ae1c000 {
626 compatible = "ti,omap4-keypad";
627 reg = <0x4ae1c000 0x400>;
631 mcpdm: mcpdm@40132000 {
632 compatible = "ti,omap4-mcpdm";
633 reg = <0x40132000 0x7f>, /* MPU private access */
634 <0x49032000 0x7f>; /* L3 Interconnect */
635 reg-names = "mpu", "dma";
636 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
640 dma-names = "up_link", "dn_link";
644 dmic: dmic@4012e000 {
645 compatible = "ti,omap4-dmic";
646 reg = <0x4012e000 0x7f>, /* MPU private access */
647 <0x4902e000 0x7f>; /* L3 Interconnect */
648 reg-names = "mpu", "dma";
649 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
652 dma-names = "up_link";
656 mcbsp1: mcbsp@40122000 {
657 compatible = "ti,omap4-mcbsp";
658 reg = <0x40122000 0xff>, /* MPU private access */
659 <0x49022000 0xff>; /* L3 Interconnect */
660 reg-names = "mpu", "dma";
661 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
662 interrupt-names = "common";
663 ti,buffer-size = <128>;
664 ti,hwmods = "mcbsp1";
667 dma-names = "tx", "rx";
671 mcbsp2: mcbsp@40124000 {
672 compatible = "ti,omap4-mcbsp";
673 reg = <0x40124000 0xff>, /* MPU private access */
674 <0x49024000 0xff>; /* L3 Interconnect */
675 reg-names = "mpu", "dma";
676 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "common";
678 ti,buffer-size = <128>;
679 ti,hwmods = "mcbsp2";
682 dma-names = "tx", "rx";
686 mcbsp3: mcbsp@40126000 {
687 compatible = "ti,omap4-mcbsp";
688 reg = <0x40126000 0xff>, /* MPU private access */
689 <0x49026000 0xff>; /* L3 Interconnect */
690 reg-names = "mpu", "dma";
691 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "common";
693 ti,buffer-size = <128>;
694 ti,hwmods = "mcbsp3";
697 dma-names = "tx", "rx";
701 mailbox: mailbox@4a0f4000 {
702 compatible = "ti,omap4-mailbox";
703 reg = <0x4a0f4000 0x200>;
704 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
705 ti,hwmods = "mailbox";
707 ti,mbox-num-users = <3>;
708 ti,mbox-num-fifos = <8>;
710 ti,mbox-tx = <0 0 0>;
711 ti,mbox-rx = <1 0 0>;
714 ti,mbox-tx = <3 0 0>;
715 ti,mbox-rx = <2 0 0>;
719 timer1: timer@4ae18000 {
720 compatible = "ti,omap5430-timer";
721 reg = <0x4ae18000 0x80>;
722 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
723 ti,hwmods = "timer1";
727 timer2: timer@48032000 {
728 compatible = "ti,omap5430-timer";
729 reg = <0x48032000 0x80>;
730 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
731 ti,hwmods = "timer2";
734 timer3: timer@48034000 {
735 compatible = "ti,omap5430-timer";
736 reg = <0x48034000 0x80>;
737 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "timer3";
741 timer4: timer@48036000 {
742 compatible = "ti,omap5430-timer";
743 reg = <0x48036000 0x80>;
744 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
745 ti,hwmods = "timer4";
748 timer5: timer@40138000 {
749 compatible = "ti,omap5430-timer";
750 reg = <0x40138000 0x80>,
752 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
753 ti,hwmods = "timer5";
758 timer6: timer@4013a000 {
759 compatible = "ti,omap5430-timer";
760 reg = <0x4013a000 0x80>,
762 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
763 ti,hwmods = "timer6";
768 timer7: timer@4013c000 {
769 compatible = "ti,omap5430-timer";
770 reg = <0x4013c000 0x80>,
772 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
773 ti,hwmods = "timer7";
777 timer8: timer@4013e000 {
778 compatible = "ti,omap5430-timer";
779 reg = <0x4013e000 0x80>,
781 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
782 ti,hwmods = "timer8";
787 timer9: timer@4803e000 {
788 compatible = "ti,omap5430-timer";
789 reg = <0x4803e000 0x80>;
790 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
791 ti,hwmods = "timer9";
795 timer10: timer@48086000 {
796 compatible = "ti,omap5430-timer";
797 reg = <0x48086000 0x80>;
798 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
799 ti,hwmods = "timer10";
803 timer11: timer@48088000 {
804 compatible = "ti,omap5430-timer";
805 reg = <0x48088000 0x80>;
806 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
807 ti,hwmods = "timer11";
812 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
813 reg = <0x4ae14000 0x80>;
814 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
815 ti,hwmods = "wd_timer2";
819 compatible = "ti,omap5-dmm";
820 reg = <0x4e000000 0x800>;
821 interrupts = <0 113 0x4>;
825 emif1: emif@4c000000 {
826 compatible = "ti,emif-4d5";
829 phy-type = <2>; /* DDR PHY type: Intelli PHY */
830 reg = <0x4c000000 0x400>;
831 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
832 hw-caps-read-idle-ctrl;
833 hw-caps-ll-interface;
837 emif2: emif@4d000000 {
838 compatible = "ti,emif-4d5";
841 phy-type = <2>; /* DDR PHY type: Intelli PHY */
842 reg = <0x4d000000 0x400>;
843 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
844 hw-caps-read-idle-ctrl;
845 hw-caps-ll-interface;
849 omap_control_usb2phy: control-phy@4a002300 {
850 compatible = "ti,control-phy-usb2";
851 reg = <0x4a002300 0x4>;
855 omap_control_usb3phy: control-phy@4a002370 {
856 compatible = "ti,control-phy-pipe3";
857 reg = <0x4a002370 0x4>;
861 usb3: omap_dwc3@4a020000 {
862 compatible = "ti,dwc3";
863 ti,hwmods = "usb_otg_ss";
864 reg = <0x4a020000 0x10000>;
865 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
866 #address-cells = <1>;
871 compatible = "snps,dwc3";
872 reg = <0x4a030000 0x10000>;
873 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
876 interrupt-names = "peripheral",
879 phys = <&usb2_phy>, <&usb3_phy>;
880 phy-names = "usb2-phy", "usb3-phy";
881 dr_mode = "peripheral";
887 compatible = "ti,omap-ocp2scp";
888 #address-cells = <1>;
890 reg = <0x4a080000 0x20>;
892 ti,hwmods = "ocp2scp1";
893 usb2_phy: usb2phy@4a084000 {
894 compatible = "ti,omap-usb2";
895 reg = <0x4a084000 0x7c>;
896 ctrl-module = <&omap_control_usb2phy>;
897 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
898 clock-names = "wkupclk", "refclk";
902 usb3_phy: usb3phy@4a084400 {
903 compatible = "ti,omap-usb3";
904 reg = <0x4a084400 0x80>,
907 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
908 ctrl-module = <&omap_control_usb3phy>;
909 clocks = <&usb_phy_cm_clk32k>,
911 <&usb_otg_ss_refclk960m>;
912 clock-names = "wkupclk",
919 usbhstll: usbhstll@4a062000 {
920 compatible = "ti,usbhs-tll";
921 reg = <0x4a062000 0x1000>;
922 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
923 ti,hwmods = "usb_tll_hs";
926 usbhshost: usbhshost@4a064000 {
927 compatible = "ti,usbhs-host";
928 reg = <0x4a064000 0x800>;
929 ti,hwmods = "usb_host_hs";
930 #address-cells = <1>;
933 clocks = <&l3init_60m_fclk>,
936 clock-names = "refclk_60m_int",
940 usbhsohci: ohci@4a064800 {
941 compatible = "ti,ohci-omap3";
942 reg = <0x4a064800 0x400>;
943 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
946 usbhsehci: ehci@4a064c00 {
947 compatible = "ti,ehci-omap";
948 reg = <0x4a064c00 0x400>;
949 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
953 bandgap: bandgap@4a0021e0 {
954 reg = <0x4a0021e0 0xc
958 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
959 compatible = "ti,omap5430-bandgap";
961 #thermal-sensor-cells = <1>;
964 omap_control_sata: control-phy@4a002374 {
965 compatible = "ti,control-phy-pipe3";
966 reg = <0x4a002374 0x4>;
968 clocks = <&sys_clkin>;
969 clock-names = "sysclk";
974 compatible = "ti,omap-ocp2scp";
975 #address-cells = <1>;
977 reg = <0x4a090000 0x20>;
979 ti,hwmods = "ocp2scp3";
980 sata_phy: phy@4a096000 {
981 compatible = "ti,phy-pipe3-sata";
982 reg = <0x4A096000 0x80>, /* phy_rx */
983 <0x4A096400 0x64>, /* phy_tx */
984 <0x4A096800 0x40>; /* pll_ctrl */
985 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
986 ctrl-module = <&omap_control_sata>;
987 clocks = <&sys_clkin>, <&sata_ref_clk>;
988 clock-names = "sysclk", "refclk";
993 sata: sata@4a141100 {
994 compatible = "snps,dwc-ahci";
995 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
996 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
998 phy-names = "sata-phy";
999 clocks = <&sata_ref_clk>;
1004 compatible = "ti,omap5-dss";
1005 reg = <0x58000000 0x80>;
1006 status = "disabled";
1007 ti,hwmods = "dss_core";
1008 clocks = <&dss_dss_clk>;
1009 clock-names = "fck";
1010 #address-cells = <1>;
1015 compatible = "ti,omap5-dispc";
1016 reg = <0x58001000 0x1000>;
1017 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1018 ti,hwmods = "dss_dispc";
1019 clocks = <&dss_dss_clk>;
1020 clock-names = "fck";
1023 rfbi: encoder@58002000 {
1024 compatible = "ti,omap5-rfbi";
1025 reg = <0x58002000 0x100>;
1026 status = "disabled";
1027 ti,hwmods = "dss_rfbi";
1028 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1029 clock-names = "fck", "ick";
1032 dsi1: encoder@58004000 {
1033 compatible = "ti,omap5-dsi";
1034 reg = <0x58004000 0x200>,
1037 reg-names = "proto", "phy", "pll";
1038 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1039 status = "disabled";
1040 ti,hwmods = "dss_dsi1";
1041 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1042 clock-names = "fck", "sys_clk";
1045 dsi2: encoder@58005000 {
1046 compatible = "ti,omap5-dsi";
1047 reg = <0x58009000 0x200>,
1050 reg-names = "proto", "phy", "pll";
1051 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1052 status = "disabled";
1053 ti,hwmods = "dss_dsi2";
1054 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1055 clock-names = "fck", "sys_clk";
1058 hdmi: encoder@58060000 {
1059 compatible = "ti,omap5-hdmi";
1060 reg = <0x58040000 0x200>,
1063 <0x58060000 0x19000>;
1064 reg-names = "wp", "pll", "phy", "core";
1065 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1066 status = "disabled";
1067 ti,hwmods = "dss_hdmi";
1068 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1069 clock-names = "fck", "sys_clk";
1071 dma-names = "audio_tx";
1075 abb_mpu: regulator-abb-mpu {
1076 compatible = "ti,abb-v2";
1077 regulator-name = "abb_mpu";
1078 #address-cells = <0>;
1080 clocks = <&sys_clkin>;
1081 ti,settling-time = <50>;
1082 ti,clock-cycles = <16>;
1084 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1085 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1086 reg-names = "base-address", "int-address",
1087 "efuse-address", "ldo-address";
1088 ti,tranxdone-status-mask = <0x80>;
1089 /* LDOVBBMPU_MUX_CTRL */
1090 ti,ldovbb-override-mask = <0x400>;
1091 /* LDOVBBMPU_VSET_OUT */
1092 ti,ldovbb-vset-mask = <0x1F>;
1095 * NOTE: only FBB mode used but actual vset will
1096 * determine final biasing
1099 /*uV ABB efuse rbb_m fbb_m vset_m*/
1100 1060000 0 0x0 0 0x02000000 0x01F00000
1101 1250000 0 0x4 0 0x02000000 0x01F00000
1105 abb_mm: regulator-abb-mm {
1106 compatible = "ti,abb-v2";
1107 regulator-name = "abb_mm";
1108 #address-cells = <0>;
1110 clocks = <&sys_clkin>;
1111 ti,settling-time = <50>;
1112 ti,clock-cycles = <16>;
1114 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1115 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1116 reg-names = "base-address", "int-address",
1117 "efuse-address", "ldo-address";
1118 ti,tranxdone-status-mask = <0x80000000>;
1119 /* LDOVBBMM_MUX_CTRL */
1120 ti,ldovbb-override-mask = <0x400>;
1121 /* LDOVBBMM_VSET_OUT */
1122 ti,ldovbb-vset-mask = <0x1F>;
1125 * NOTE: only FBB mode used but actual vset will
1126 * determine final biasing
1129 /*uV ABB efuse rbb_m fbb_m vset_m*/
1130 1025000 0 0x0 0 0x02000000 0x01F00000
1131 1120000 0 0x4 0 0x02000000 0x01F00000
1138 polling-delay = <500>; /* milliseconds */
1141 /include/ "omap54xx-clocks.dtsi"