arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/platform_data/dwc3-exynos.h>
  16 #include <linux/regulator/fixed.h>
  17 #include <linux/regulator/machine.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/smsc911x.h>
  20 #include <linux/delay.h>
  21 #include <linux/i2c.h>
  22 #include <linux/pwm_backlight.h>
  23 #include <linux/mfd/wm8994/pdata.h>
  24 #include <linux/regulator/machine.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/memblock.h>
  27 #include <linux/of_fdt.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_data/ntc_thermistor.h>
  30
  31 #include <asm/mach/arch.h>
  32 #include <asm/hardware/gic.h>
  33 #include <mach/bitfix-snow.h>
  34 #include <mach/map.h>
  35 #include <mach/ppmu.h>
  36 #include <mach/dev.h>
  37 #include <mach/ohci.h>
  38 #include <mach/regs-pmu.h>
  39 #include <mach/sysmmu.h>
  40 #include <mach/ohci.h>
  41 #include <mach/regs-audss.h>
  42 #include <mach/regs-pmu.h>
  43
  44 #include <plat/audio.h>
  45 #include <plat/adc.h>   /* for s3c_adc_register and friends */
  46 #include <plat/cpu.h>
  47 #include <plat/dsim.h>
  48 #include <plat/fb.h>
  49 #include <plat/mipi_dsi.h>
  50 #include <plat/gpio-cfg.h>
  51 #include <plat/regs-fb.h>
  52 #include <plat/regs-serial.h>
  53 #include <plat/regs-srom.h>
  54 #include <plat/backlight.h>
  55 #include <plat/devs.h>
  56 #include <plat/usb-phy.h>
  57 #include <plat/ehci.h>
  58 #include <plat/dp.h>
  59 #include <plat/s3c64xx-spi.h>
  60
  61 #include <video/platform_lcd.h>
  62
  63 #include "drm/exynos_drm.h"
  64 #include "common.h"
  65
  66 static void __init smsc911x_init(int ncs)
  67 {
  68         u32 data;
  69
  70         /* configure nCS1 width to 16 bits */
  71         data = __raw_readl(S5P_SROM_BW) &
  72                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  73         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  74                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  75                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  76         __raw_writel(data, S5P_SROM_BW);
  77
  78         /* set timing for nCS1 suitable for ethernet chip */
  79         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  80                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  81                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  82                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  83                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  84                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  85                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  86                 S5P_SROM_BC0 + (ncs * 4));
  87 }
  88
  89 #ifndef CONFIG_DRM_EXYNOS_FIMD
  90 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  91         .win_mode = {
  92                 .left_margin    = 4,
  93                 .right_margin   = 4,
  94                 .upper_margin   = 4,
  95                 .lower_margin   = 4,
  96                 .hsync_len      = 4,
  97                 .vsync_len      = 4,
  98                 .xres           = 1280,
  99                 .yres           = 800,
 100         },
 101         .virtual_x              = 1280,
 102         .virtual_y              = 800 * 2,
 103         .width                  = 223,
 104         .height                 = 125,
 105         .max_bpp                = 32,
 106         .default_bpp            = 24,
 107 };
 108
 109 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
 110         .win_mode = {
 111                 .left_margin    = 4,
 112                 .right_margin   = 4,
 113                 .upper_margin   = 4,
 114                 .lower_margin   = 4,
 115                 .hsync_len      = 4,
 116                 .vsync_len      = 4,
 117                 .xres           = 1280,
 118                 .yres           = 800,
 119         },
 120         .virtual_x              = 1280,
 121         .virtual_y              = 800 * 2,
 122         .width                  = 223,
 123         .height                 = 125,
 124         .max_bpp                = 32,
 125         .default_bpp            = 24,
 126 };
 127
 128 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 129         .win_mode = {
 130                 .left_margin    = 0x4,
 131                 .right_margin   = 0x4,
 132                 .upper_margin   = 4,
 133                 .lower_margin   = 4,
 134                 .hsync_len      = 4,
 135                 .vsync_len      = 4,
 136                 .xres           = 1280,
 137                 .yres           = 800,
 138         },
 139         .virtual_x              = 1280,
 140         .virtual_y              = 800 * 2,
 141         .width                  = 223,
 142         .height                 = 125,
 143         .max_bpp                = 32,
 144         .default_bpp            = 24,
 145 };
 146 #endif
 147
 148 /*
 149  * - 70250000. / ((1366 + 40 + 40 + 32) * (768 + 10 + 10 + 5))
 150  * - 59.93751141159025
 151  * - 70500000. / ((1366 + 40 + 40 + 32) * (768 + 10 + 10 + 5))
 152  * - 60.150812163944664
 153  * - 70500000. / ((1366 + 40 + 40 + 32) * (768 + 10 + 12 + 6))
 154  *   59.92411312312578
 155  */
 156 static struct fb_videomode snow_fb_window = {
 157                 .left_margin    = 40,
 158                 .right_margin   = 40,
 159                 .upper_margin   = 10,
 160                 .lower_margin   = 12,
 161                 .hsync_len      = 32,
 162                 .vsync_len      = 6,
 163                 .xres           = 1366,
 164                 .yres           = 768,
 165                 .refresh        = 60,
 166                 .pixclock       = 70500000,
 167 };
 168
 169 static void exynos_fimd_gpio_setup_24bpp(void)
 170 {
 171         unsigned int reg = 0;
 172
 173         /*
 174          * Set DISP1BLK_CFG register for Display path selection
 175          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 176          * ---------------------
 177          * 0 | MIE/MDNIE
 178          * 1 | FIMD : selected
 179          */
 180         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 181         reg &= ~(1 << 15);      /* To save other reset values */
 182         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 183 }
 184
 185 static void exynos_dp_gpio_setup_24bpp(void)
 186 {
 187         exynos_fimd_gpio_setup_24bpp();
 188
 189         /* Set Hotplug detect for DP */
 190         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 191         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 192 }
 193
 194 #ifdef CONFIG_DRM_EXYNOS_HDMI
 195 static struct platform_device exynos_drm_hdmi_device = {
 196         .name           = "exynos-drm-hdmi",
 197 };
 198
 199 static struct exynos_drm_hdmi_pdata drm_mixer_pdata = {
 200         .timing = {
 201                 .xres    = 1920,
 202                 .yres    = 1080,
 203                 .refresh = 60,
 204         },
 205         .default_win    = 0,
 206         .bpp            = 32,
 207         .is_v13         = 0,
 208         .is_soc_exynos5 = 1,
 209 };
 210
 211 static struct exynos_drm_hdmi_pdata drm_hdmi_pdata = {
 212         .timing = {
 213                 .xres    = 1920,
 214                 .yres    = 1080,
 215                 .refresh    = 60,
 216         },
 217         .default_win    = 0,
 218         .bpp            = 32,
 219         .is_v13         = 0,
 220         .is_soc_exynos5 = 1,
 221 };
 222 #endif
 223
 224 #ifdef CONFIG_DRM_EXYNOS_FIMD
 225 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 226         .panel = {
 227                 .timing   = {
 228                         .xres           = 1280,
 229                         .yres           = 800,
 230                         .hsync_len      = 4,
 231                         .left_margin    = 0x4,
 232                         .right_margin   = 0x4,
 233                         .vsync_len      = 4,
 234                         .upper_margin   = 4,
 235                         .lower_margin   = 4,
 236                         .refresh        = 60,
 237                 },
 238         },
 239         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 240         .vidcon1        = VIDCON1_INV_VCLK,
 241         .default_win    = 0,
 242         .bpp            = 32,
 243         .clock_rate     = 800 * 1000 * 1000,
 244 };
 245 #else
 246 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 247         .win[0]         = &smdk5250_fb_win0,
 248         .win[1]         = &smdk5250_fb_win1,
 249         .win[2]         = &smdk5250_fb_win2,
 250         .default_win    = 0,
 251         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 252         .vidcon1        = VIDCON1_INV_VCLK,
 253         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 254         .clock_rate     = 800 * 1000 * 1000,
 255 };
 256 #endif
 257
 258 static struct mipi_dsim_config dsim_info = {
 259         .e_interface            = DSIM_VIDEO,
 260         .e_pixel_format         = DSIM_24BPP_888,
 261         /* main frame fifo auto flush at VSYNC pulse */
 262         .auto_flush             = false,
 263         .eot_disable            = false,
 264         .auto_vertical_cnt      = false,
 265         .hse                    = false,
 266         .hfp                    = false,
 267         .hbp                    = false,
 268         .hsa                    = false,
 269
 270         .e_no_data_lane         = DSIM_DATA_LANE_4,
 271         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 272         .e_burst_mode           = DSIM_BURST,
 273
 274         .p                      = 3,
 275         .m                      = 115,
 276         .s                      = 1,
 277
 278         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 279         .pll_stable_time        = 500,
 280
 281         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 282
 283         /* stop state holding counter after bta change count 0 ~ 0xfff */
 284         .stop_holding_cnt       = 0x0f,
 285         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 286         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 287
 288         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 289 };
 290
 291 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 292         .rgb_timing.left_margin         = 0x4,
 293         .rgb_timing.right_margin        = 0x4,
 294         .rgb_timing.upper_margin        = 0x4,
 295         .rgb_timing.lower_margin        =  0x4,
 296         .rgb_timing.hsync_len           = 0x4,
 297         .rgb_timing.vsync_len           = 0x4,
 298         .cpu_timing.cs_setup            = 0,
 299         .cpu_timing.wr_setup            = 1,
 300         .cpu_timing.wr_act              = 0,
 301         .cpu_timing.wr_hold             = 0,
 302         .lcd_size.width                 = 1280,
 303         .lcd_size.height                = 800,
 304 };
 305
 306 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 307         .clk_name               = "dsim0",
 308         .dsim_config            = &dsim_info,
 309         .dsim_lcd_config        = &dsim_lcd_info,
 310
 311         .part_reset             = s5p_dsim_part_reset,
 312         .init_d_phy             = s5p_dsim_init_d_phy,
 313         .get_fb_frame_done      = NULL,
 314         .trigger                = NULL,
 315
 316         /*
 317          * the stable time of needing to write data on SFR
 318          * when the mipi mode becomes LP mode.
 319          */
 320         .delay_for_stabilization = 600,
 321 };
 322
 323 static struct platform_device exynos_drm_device = {
 324         .name           = "exynos-drm",
 325         .dev = {
 326                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 327                 .coherent_dma_mask = 0xffffffffUL,
 328         }
 329 };
 330
 331 static void exynos_wifi_bt_set_power(u32, u32); /* TODO(sleffler) hack */
 332
 333 static void lcd_set_power(struct plat_lcd_data *pd,
 334                         unsigned int power)
 335 {
 336         if (of_machine_is_compatible("google,daisy") ||
 337                         of_machine_is_compatible("google,snow")) {
 338                 struct regulator *lcd_fet;
 339
 340                 lcd_fet = regulator_get(NULL, "lcd_vdd");
 341                 if (!IS_ERR(lcd_fet)) {
 342                         if (power)
 343                                 regulator_enable(lcd_fet);
 344                         else
 345                                 regulator_disable(lcd_fet);
 346
 347                         regulator_put(lcd_fet);
 348                 }
 349         }
 350
 351         if (!of_machine_is_compatible("google,snow")) {
 352                 /* reset */
 353                 gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 354                 mdelay(20);
 355                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 356                 mdelay(20);
 357                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 358                 mdelay(20);
 359                 gpio_free(EXYNOS5_GPX1(5));
 360                 mdelay(20);
 361         }
 362
 363
 364         /* Turn on regulator for backlight */
 365         if (of_machine_is_compatible("google,daisy") ||
 366                         of_machine_is_compatible("google,snow")) {
 367                 struct regulator *backlight_fet;
 368
 369                 backlight_fet = regulator_get(NULL, "vcd_led");
 370                 if (!IS_ERR(backlight_fet)) {
 371                         if (power)
 372                                 regulator_enable(backlight_fet);
 373                         else
 374                                 regulator_disable(backlight_fet);
 375
 376                         regulator_put(backlight_fet);
 377                 }
 378                 /* Wait 10 ms between regulator on and PWM start per spec */
 379                 mdelay(10);
 380         }
 381         exynos_wifi_bt_set_power(0, power);     /* TODO(sleffler) hack */
 382 }
 383
 384 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 385 {
 386         /* Don't call .set_power callback while unblanking */
 387         return 0;
 388 }
 389
 390 static struct plat_lcd_data smdk5250_lcd_data = {
 391         .set_power      = lcd_set_power,
 392         .match_fb       = smdk5250_match_fb,
 393 };
 394
 395 static struct platform_device smdk5250_lcd = {
 396         .name                   = "platform-lcd",
 397         .dev.platform_data      = &smdk5250_lcd_data,
 398 };
 399
 400 static int smdk5250_bl_notify(struct device *unused, int brightness)
 401 {
 402         /* manage lcd_bl_en signal */
 403         if (brightness)
 404                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 405         else
 406                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 407
 408         return brightness;
 409 }
 410
 411 /* LCD Backlight data */
 412 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 413         .no     = EXYNOS5_GPB2(0),
 414         .func   = S3C_GPIO_SFN(2),
 415 };
 416
 417 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 418         .pwm_period_ns  = 1000000,
 419         .notify         = smdk5250_bl_notify,
 420 };
 421
 422 struct platform_device exynos_device_md0 = {
 423         .name = "exynos-mdev",
 424         .id = 0,
 425 };
 426
 427 struct platform_device exynos_device_md1 = {
 428         .name = "exynos-mdev",
 429         .id = 1,
 430 };
 431
 432 struct platform_device exynos_device_md2 = {
 433         .name = "exynos-mdev",
 434         .id = 2,
 435 };
 436
 437 static struct regulator_consumer_supply wm8994_avdd1_supply =
 438         REGULATOR_SUPPLY("AVDD1", "1-001a");
 439
 440 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 441         REGULATOR_SUPPLY("DCVDD", "1-001a");
 442
 443 static struct regulator_init_data wm8994_ldo1_data = {
 444         .constraints    = {
 445                 .name           = "AVDD1",
 446         },
 447         .num_consumer_supplies  = 1,
 448         .consumer_supplies      = &wm8994_avdd1_supply,
 449 };
 450
 451 static struct regulator_init_data wm8994_ldo2_data = {
 452         .constraints    = {
 453         .name                   = "DCVDD",
 454                 },
 455         .num_consumer_supplies  = 1,
 456         .consumer_supplies      = &wm8994_dcvdd_supply,
 457 };
 458
 459 static struct wm8994_pdata wm8994_platform_data = {
 460         /* configure gpio1 function: 0x0001(Logic level input/output) */
 461         .gpio_defaults[0] = 0x0001,
 462         /* If the i2s0 and i2s2 is enabled simultaneously */
 463         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 464         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 465         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 466         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 467         .ldo[0] = { 0, &wm8994_ldo1_data },
 468         .ldo[1] = { 0, &wm8994_ldo2_data },
 469 };
 470
 471 static struct i2c_board_info i2c_devs1[] __initdata = {
 472         {
 473                 I2C_BOARD_INFO("wm8994", 0x1a),
 474                 .platform_data  = &wm8994_platform_data,
 475         },
 476 };
 477
 478 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 479         [0] = {
 480                 .line           = EXYNOS5_GPA2(5),
 481                 .fb_delay       = 0x2,
 482         },
 483 };
 484
 485 static struct spi_board_info spi1_board_info[] __initdata = {
 486         {
 487                 .modalias               = "spidev",
 488                 .platform_data          = NULL,
 489                 .max_speed_hz           = 10*1000*1000,
 490                 .bus_num                = 1,
 491                 .chip_select            = 0,
 492                 .mode                   = SPI_MODE_0,
 493                 .controller_data        = spi1_csi,
 494         }
 495 };
 496
 497 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 498         .dbgname = "mfc_l",
 499         .clockname = "sysmmu",
 500 };
 501
 502 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 503         .dbgname = "mfc_r",
 504         .clockname = "sysmmu",
 505 };
 506
 507 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 508         .dbgname = "gsc",
 509         .clockname = "sysmmu",
 510 };
 511
 512 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 513         .dbgname = "g2d",
 514         .clockname = "sysmmu",
 515 };
 516
 517 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 518         .dbgname = "fimd",
 519         .clockname = "sysmmu",
 520 };
 521
 522 struct sysmmu_platform_data platdata_sysmmu_tv = {
 523         .dbgname = "tv",
 524         .clockname = "sysmmu",
 525 };
 526
 527 #ifdef CONFIG_VIDEO_FIMG2D4X
 528 static struct fimg2d_platdata fimg2d_data __initdata = {
 529         .hw_ver         = 0x42,
 530         .gate_clkname   = "fimg2d",
 531 };
 532 #endif
 533
 534 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 535         .phy_init = s5p_usb_phy_init,
 536         .phy_exit = s5p_usb_phy_exit,
 537 };
 538
 539 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 540         .phy_init = s5p_usb_phy_init,
 541         .phy_exit = s5p_usb_phy_exit,
 542 };
 543
 544 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 545         .phy_type = S5P_USB_PHY_DRD,
 546         .phy_init = s5p_usb_phy_init,
 547         .phy_exit = s5p_usb_phy_exit,
 548         .phyclk_switch = exynos5_dwc_phyclk_switch,
 549         .use_ext_clk = s5p_usb_phy_use_ext_clk,
 550 };
 551
 552 struct exynos_gpio_cfg {
 553         unsigned int    addr;
 554         unsigned int    num;
 555         unsigned int    bit;
 556 };
 557
 558 static const char *rclksrc[] = {
 559         [0] = "busclk",
 560         [1] = "i2sclk",
 561 };
 562
 563 static struct video_info ptn3460_dp_config = {
 564         .name                   = "eDP-LVDS NXP PTN3460",
 565
 566         .h_sync_polarity        = 0,
 567         .v_sync_polarity        = 0,
 568         .interlaced             = 0,
 569
 570         .color_space            = COLOR_RGB,
 571         .dynamic_range          = VESA,
 572         .ycbcr_coeff            = COLOR_YCBCR601,
 573         .color_depth            = COLOR_8,
 574
 575         .link_rate              = LINK_RATE_2_70GBPS,
 576         .lane_count             = LANE_COUNT2,
 577 };
 578
 579 static struct video_info ps8622_dp_config = {
 580         .name                   = "eDP-LVDS Parade PS8622",
 581
 582         .h_sync_polarity        = 0,
 583         .v_sync_polarity        = 0,
 584         .interlaced             = 0,
 585
 586         .color_space            = COLOR_RGB,
 587         .dynamic_range          = VESA,
 588         .ycbcr_coeff            = COLOR_YCBCR601,
 589         .color_depth            = COLOR_8,
 590
 591         .link_rate              = LINK_RATE_2_70GBPS,
 592         .lane_count             = LANE_COUNT1,
 593 };
 594
 595 static struct exynos_dp_platdata smdk5250_dp_data = {
 596         .video_info             = &ptn3460_dp_config,
 597         .training_type          = SW_LINK_TRAINING,
 598         .hpd_gpio               = -ENODEV,
 599         .force_connected        = true,
 600         .phy_init               = s5p_dp_phy_init,
 601         .phy_exit               = s5p_dp_phy_exit,
 602 };
 603
 604 #define S5P_PMU_DEBUG                           S5P_PMUREG(0x0A00)
 605 /* PMU_DEBUG bits [12:8] = 0x10000 selects XXTI clock source */
 606 #define PMU_DEBUG_XXTI                          (0x10 << 8)
 607 /* Mask bit[12:8] for xxti clock selection */
 608 #define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
 609
 610 static void __init enable_xclkout(void)
 611 {
 612        unsigned int tmp;
 613
 614        tmp = readl(S5P_PMU_DEBUG);
 615        tmp &= ~PMU_DEBUG_CLKOUT_SEL_MASK;
 616        tmp |= PMU_DEBUG_XXTI;
 617        writel(tmp, S5P_PMU_DEBUG);
 618 }
 619
 620 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 621 {
 622         int id;
 623         /* configure GPIO for i2s port */
 624         struct exynos_gpio_cfg exynos5_cfg[3] = {
 625                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 626                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 627                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 628         };
 629
 630         if (pdev->dev.of_node) {
 631                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 632                 if (id < 0)
 633                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 634         } else {
 635                 id = pdev->id;
 636         }
 637
 638         if (id < 0 || id > 2) {
 639                 printk(KERN_ERR "Invalid Device %d\n", id);
 640                 return -EINVAL;
 641         }
 642
 643         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 644                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 645
 646         return 0;
 647 }
 648
 649 static struct s3c_audio_pdata i2sv5_pdata = {
 650         .cfg_gpio = exynos_cfg_i2s_gpio,
 651         .type = {
 652                 .i2s = {
 653                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 654                                          | QUIRK_NEED_RSTCLR,
 655                         .src_clk = rclksrc,
 656                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 657                 },
 658         },
 659 };
 660
 661 /*
 662  * Hack to do power-on sequence after the 32khz SLP_CLK is
 663  * running as doing this entirely in the DT is problematic.
 664  * We attach an auxdata record to dw_mmc2 with a set_power
 665  * method that frobs the regulators.  This work is not board
 666  * specific but must be done before the device is recognized
 667  * so cannot go in the driver.
 668  */
 669 static bool enable_mwi87xx(void)
 670 {
 671         struct regulator *wifi_en, *wifi_rst;
 672         bool ok;
 673
 674         wifi_en = regulator_get(NULL, "wifi-en");
 675         wifi_rst = regulator_get(NULL, "wifi-rst-l");
 676         ok = !IS_ERR(wifi_en) && !IS_ERR(wifi_rst);
 677         if (ok) {
 678                 /*
 679                  * This assumes SLP_CLK is enabled and stable by the
 680                  * time we get here.  Also any delay required between
 681                  * RESETn and PDn should be set in startup-delay-us
 682                  * in the DT.
 683                  */
 684                 regulator_enable(wifi_rst);
 685                 regulator_enable(wifi_en);
 686         }
 687
 688         if (!IS_ERR(wifi_rst))
 689                 regulator_put(wifi_rst);
 690         if (!IS_ERR(wifi_en))
 691                 regulator_put(wifi_en);
 692         return ok;
 693 }
 694
 695 static void exynos_wifi_bt_set_power(u32 slot_id, u32 volt)
 696 {
 697         if (volt == 0 || (!of_machine_is_compatible("google,snow") &&
 698                           !of_machine_is_compatible("google,spring") &&
 699                           !of_machine_is_compatible("google,daisy")))
 700                 return;
 701         if (!enable_mwi87xx())
 702                 pr_err("%s: problem enabling WiFi+BT\n", __func__);
 703         /* NB: bt-reset-l is tied to wifi-rst-l so BT should be ready too */
 704 }
 705
 706
 707 /* NTC Thermistor. Attached to S3C-ADC in some Samsung SoC Devices */
 708 struct s3c_adc_client *ntc_adc_clients[4];
 709 struct mutex ntc_adc_locks[] = {
 710         __MUTEX_INITIALIZER(ntc_adc_locks[0]),
 711         __MUTEX_INITIALIZER(ntc_adc_locks[1]),
 712         __MUTEX_INITIALIZER(ntc_adc_locks[2]),
 713         __MUTEX_INITIALIZER(ntc_adc_locks[3]),
 714 };
 715
 716 static int __init s3c_adc_ntc_init(struct platform_device *pdev)
 717 {
 718         struct s3c_adc_client *ntc_adc_client;
 719
 720         ntc_adc_client = s3c_adc_register(pdev, NULL, NULL, 0);
 721         if (IS_ERR(ntc_adc_client))
 722                 return PTR_ERR(ntc_adc_client);
 723
 724         ntc_adc_clients[pdev->id] = ntc_adc_client;
 725
 726         return 0;
 727 }
 728
 729 /*
 730  * read_thermistor_uV: is a call back from ntc_thermistor driver.
 731  * returns the temperature of the thermistor in celsius
 732  */
 733 static int read_thermistor_uV(struct platform_device *pdev)
 734 {
 735         static unsigned int ntc_adc_ports[] = {3, 4, 5, 6};
 736         s64 converted;
 737         unsigned int port = ntc_adc_ports[pdev->id];
 738         struct s3c_adc_client *client = ntc_adc_clients[pdev->id];
 739         struct ntc_thermistor_platform_data *pdata = pdev->dev.platform_data;
 740         struct mutex *lock = ntc_adc_locks + pdev->id;
 741         int ret;
 742
 743         /* Arrays are sized; make sure we haven't blown over */
 744         BUG_ON(pdev->id >= ARRAY_SIZE(ntc_adc_locks));
 745
 746         /*
 747          * s3c_adc_read() assumes two processes aren't using the same client
 748          * at the same time (yes, it's a bad design), so grab a per-client
 749          * mutex to ensure this is OK.
 750          */
 751         mutex_lock(lock);
 752         ret = s3c_adc_read(client, port);
 753         mutex_unlock(lock);
 754
 755         if (ret < 0) {
 756                 dev_warn(&pdev->dev, "Thermistor read err: 0x%08x\n", ret);
 757                 return ret;
 758         }
 759
 760         converted = pdata->pullup_uV * (s64) ret;
 761         converted >>= 12;
 762
 763         return (int) converted;
 764 }
 765
 766 static struct ntc_thermistor_platform_data ntc_adc_pdata = {
 767         .read_uV        = read_thermistor_uV,
 768         .pullup_uV      = 1800000, /* voltage of vdd for ADC */
 769         .pullup_ohm     = 47000,
 770         .pulldown_ohm   = 0,
 771         .connect        = NTC_CONNECTED_GROUND,
 772 };
 773
 774 struct platform_device s3c_device_adc_ntc_thermistor0 = {
 775         .name                   = "ncp15wb473",
 776         .id                     = 0,
 777         .dev                    = {
 778                 .platform_data = &ntc_adc_pdata,
 779         },
 780 };
 781
 782 struct platform_device s3c_device_adc_ntc_thermistor1 = {
 783         .name                   = "ncp15wb473",
 784         .id                     = 1,
 785         .dev                    = {
 786         .platform_data = &ntc_adc_pdata,
 787         },
 788 };
 789
 790 struct platform_device s3c_device_adc_ntc_thermistor2 = {
 791         .name                   = "ncp15wb473",
 792         .id                     = 2,
 793         .dev                    = {
 794                 .platform_data = &ntc_adc_pdata,
 795         },
 796 };
 797
 798 struct platform_device s3c_device_adc_ntc_thermistor3 = {
 799         .name                   = "ncp15wb473",
 800         .id                     = 3,
 801         .dev                    = {
 802                 .platform_data = &ntc_adc_pdata,
 803         },
 804 };
 805
 806 /*
 807  * The following lookup table is used to override device names when devices
 808  * are registered from device tree. This is temporarily added to enable
 809  * device tree support addition for the EXYNOS5 architecture.
 810  *
 811  * For drivers that require platform data to be provided from the machine
 812  * file, a platform data pointer can also be supplied along with the
 813  * devices names. Usually, the platform data elements that cannot be parsed
 814  * from the device tree by the drivers (example: function pointers) are
 815  * supplied. But it should be noted that this is a temporary mechanism and
 816  * at some point, the drivers should be capable of parsing all the platform
 817  * data from the device tree.
 818  */
 819 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 820         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 821                                 "exynos4210-uart.0", NULL),
 822         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 823                                 "exynos4210-uart.1", NULL),
 824         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 825                                 "exynos4210-uart.2", NULL),
 826         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 827                                 "exynos4210-uart.3", NULL),
 828         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 829                                 "s3c2440-i2c.0", NULL),
 830         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 831                                 "s3c2440-i2c.1", NULL),
 832         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 833                                 "s3c2440-i2c.2", NULL),
 834         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
 835                                 "s3c2440-i2c.3", NULL),
 836         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
 837                                 "s3c2440-i2c.4", NULL),
 838         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
 839                                 "s3c2440-i2c.5", NULL),
 840         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
 841                                 "s3c2440-i2c.6", NULL),
 842         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
 843                                 "s3c2440-i2c.7", NULL),
 844         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 845                                 "s3c2440-hdmiphy-i2c", NULL),
 846         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 847                                 "exynos4210-spi.0", NULL),
 848         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 849                                 "exynos4210-spi.1", NULL),
 850         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 851                                 "exynos4210-spi.2", NULL),
 852         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 853                                 "dw_mmc.0", NULL),
 854         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 855                                 "dw_mmc.1", NULL),
 856         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 857                                 "dw_mmc.2", NULL),
 858         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 859                                 "dw_mmc.3", NULL),
 860         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 861         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 862         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 863         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 864                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 865         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 866                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 867         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 868                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 869         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 870                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 871         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 872                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 873         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 874                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 875         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 876                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 877         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 878                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 879         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 880                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 881         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 882                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 883         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 884                                 "s5p-mipi-dsim", &dsim_platform_data),
 885         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 886                                 "s5p-dp", &smdk5250_dp_data),
 887         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 888         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 889                                 "exynos-gsc.0", NULL),
 890         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 891                                 "exynos-gsc.1", NULL),
 892         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 893                                 "exynos-gsc.2", NULL),
 894         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 895                                 "exynos-gsc.3", NULL),
 896 #ifdef CONFIG_VIDEO_FIMG2D4X
 897         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 898                                 "s5p-g2d", &fimg2d_data),
 899 #endif
 900         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 901                                 "exynos-ohci", &smdk5250_ohci_pdata),
 902         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 903                                 "s5p-ehci", &smdk5250_ehci_pdata),
 904         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 905                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 906         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 907                                 "samsung-i2s.0", &i2sv5_pdata),
 908 #ifdef CONFIG_DRM_EXYNOS_HDMI
 909         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 910                                 "exynos5-hdmi", &drm_hdmi_pdata),
 911         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 912                                 "s5p-mixer", &drm_mixer_pdata),
 913 #else
 914         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 915                                 "exynos5-hdmi", NULL),
 916         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 917                                 "s5p-mixer", NULL),
 918 #endif
 919         {},
 920 };
 921
 922 #ifdef CONFIG_BUSFREQ_OPP
 923 /* BUSFREQ to control memory/bus*/
 924 static struct device_domain busfreq;
 925
 926 static struct platform_device exynos5_busfreq = {
 927         .id = -1,
 928         .name = "exynos-busfreq",
 929 };
 930 #endif
 931
 932 static struct platform_device *smdk5250_devices[] __initdata = {
 933         &smdk5250_lcd, /* for platform_lcd device */
 934         &exynos_device_md0, /* for media device framework */
 935         &exynos_device_md1, /* for media device framework */
 936         &exynos_device_md2, /* for media device framework */
 937         &samsung_asoc_dma,  /* for audio dma interface device */
 938         &exynos_drm_device,
 939 #ifdef CONFIG_DRM_EXYNOS_HDMI
 940         &exynos_drm_hdmi_device,
 941 #endif
 942 #ifdef CONFIG_BUSFREQ_OPP
 943         &exynos5_busfreq,
 944 #endif
 945 };
 946
 947 static struct platform_device *thermistor_devices[] __initdata = {
 948         &s3c_device_adc_ntc_thermistor0,
 949         &s3c_device_adc_ntc_thermistor1,
 950         &s3c_device_adc_ntc_thermistor2,
 951         &s3c_device_adc_ntc_thermistor3,
 952 };
 953
 954 static struct regulator_consumer_supply dummy_supplies[] = {
 955         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 956         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 957 };
 958
 959 static void __init exynos5250_dt_map_io(void)
 960 {
 961         exynos_init_io(NULL, 0);
 962         s3c24xx_init_clocks(24000000);
 963 }
 964
 965 static unsigned long ramoops_dt_start, ramoops_dt_size;
 966 static int __init init_dt_scan_ramoops(unsigned long node, const char *uname,
 967                                         int depth, void *data)
 968 {
 969         __be32 *reg, *endp;
 970         unsigned long l;
 971
 972         if (!of_flat_dt_is_compatible(node, "ramoops"))
 973                 return 0;
 974
 975         reg = of_get_flat_dt_prop(node, "reg", &l);
 976         if (!reg)
 977                 return 0;
 978         endp = reg + (l / sizeof(__be32));
 979
 980         /* This architecture uses single cells for address and size.
 981          * Other architectures may differ. */
 982         ramoops_dt_start = be32_to_cpu(reg[0]);
 983         ramoops_dt_size = be32_to_cpu(reg[1]);
 984         return 0;
 985 }
 986
 987 static void __init exynos5_ramoops_reserve(void)
 988 {
 989         unsigned long start, size;
 990
 991         of_scan_flat_dt(init_dt_scan_ramoops, NULL);
 992
 993         /* If necessary, lower start and raise size to align to 1M. */
 994         start = round_down(ramoops_dt_start, SZ_1M);
 995         size = ramoops_dt_size + ramoops_dt_start - start;
 996         size = round_up(size, SZ_1M);
 997
 998         if (memblock_remove(start, size)) {
 999                 pr_err("Failed to remove ramoops %08lx@%08lx from memory\n",
1000                         size, start);
1001         } else {
1002                 pr_info("Ramoops: %08lx - %08lx\n", start, start + size - 1);
1003         }
1004 }
1005
1006 static void __init exynos5_reserve(void)
1007 {
1008         /* required to have enough address range to remap the IOMMU
1009          * allocated buffers */
1010         init_consistent_dma_size(SZ_64M);
1011
1012         exynos5_ramoops_reserve();
1013         bitfix_reserve();
1014 }
1015
1016 static void s5p_tv_setup(void)
1017 {
1018         /* direct HPD to HDMI chip */
1019         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
1020
1021         gpio_direction_input(EXYNOS5_GPX3(7));
1022         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
1023         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
1024 }
1025
1026 static void exynos5_i2c_setup(void)
1027 {
1028         /* Setup the low-speed i2c controller interrupts */
1029         writel(0x0, EXYNOS5_SYS_I2C_CFG);
1030 }
1031
1032 static void __init exynos5250_dt_machine_init(void)
1033 {
1034         struct device_node *srom_np, *np;
1035
1036         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1037
1038         /* Setup pins for any SMSC 911x controller on the SROMC bus */
1039         srom_np = of_find_node_by_path("/sromc-bus");
1040         if (!srom_np) {
1041                 printk(KERN_ERR "No /sromc-bus property.\n");
1042                 goto out;
1043         }
1044         for_each_child_of_node(srom_np, np) {
1045                 if (of_device_is_compatible(np, "smsc,lan9115")) {
1046                         u32 reg;
1047                         of_property_read_u32(np, "reg", &reg);
1048                         smsc911x_init(reg);
1049                 }
1050         }
1051
1052         /*
1053          * Set the backlight on LCD_PWM pin only for boards not using the
1054          * Parade eDP bridge which has an internal PWN for the backlight.
1055          */
1056         if (!of_find_compatible_node(NULL, NULL, "parade,ps8622")) {
1057                 if (of_machine_is_compatible("google,snow")) {
1058                         smdk5250_bl_data.max_brightness = 2800;
1059                         smdk5250_bl_data.dft_brightness = 2800;
1060                 }
1061
1062                 /*
1063                  * Request lcd_bl_en GPIO for smdk5250_bl_notify().
1064                  * TODO: Fix this so we are not at risk of requesting the GPIO
1065                  * multiple times, this should be done with device tree, and
1066                  * likely integrated into the plat-samsung/dev-backlight.c init.
1067                  */
1068                 gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_HIGH,
1069                                  "lcd_bl_en");
1070
1071                 samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
1072         }
1073
1074         /*
1075          * HACK ALERT! TODO: FIXME!
1076          *
1077          * We're going to hack in Daisy LCD info here for bringup purposes.
1078          * Lots of things wrong with what we're doing here, but it works for
1079          * bringup purposes.
1080          */
1081
1082         if (of_machine_is_compatible("google,daisy")) {
1083 #ifdef CONFIG_DRM_EXYNOS_FIMD
1084                 smdk5250_lcd1_pdata.panel.timing.xres = 1366;
1085                 smdk5250_lcd1_pdata.panel.timing.yres = 768;
1086                 smdk5250_lcd1_pdata.panel_type = MIPI_LCD;
1087 #else
1088                 smdk5250_fb_win0.win_mode.xres = 1366;
1089                 smdk5250_fb_win0.win_mode.yres = 768;
1090                 smdk5250_fb_win0.virtual_x = 1366;
1091                 smdk5250_fb_win0.virtual_y = 768 * 2;
1092
1093                 smdk5250_fb_win1.win_mode.xres = 1366;
1094                 smdk5250_fb_win1.win_mode.yres = 768;
1095                 smdk5250_fb_win1.virtual_x = 1366;
1096                 smdk5250_fb_win1.virtual_y = 768 * 2;
1097
1098                 smdk5250_fb_win2.win_mode.xres = 1366;
1099                 smdk5250_fb_win2.win_mode.yres = 768;
1100                 smdk5250_fb_win2.virtual_x = 1366;
1101                 smdk5250_fb_win2.virtual_y = 768 * 2;
1102 #endif
1103                 dsim_lcd_info.lcd_size.width = 1366;
1104                 dsim_lcd_info.lcd_size.height = 768;
1105         } else if ((of_machine_is_compatible("google,snow")) ||
1106                    (of_machine_is_compatible("google,spring"))) {
1107 #ifdef CONFIG_DRM_EXYNOS_FIMD
1108                 smdk5250_lcd1_pdata.panel.timing = snow_fb_window;
1109
1110                 smdk5250_lcd1_pdata.panel_type = DP_LCD;
1111                 smdk5250_lcd1_pdata.vidcon1 = 0;
1112                 smdk5250_lcd1_pdata.clock_rate =
1113                         smdk5250_lcd1_pdata.panel.timing.pixclock;
1114 #endif
1115         }
1116
1117         /* put the DP output configuration matching the eDP-LVDS bridge */
1118         if (of_find_compatible_node(NULL, NULL, "nxp,ptn3460")) {
1119                 smdk5250_dp_data.video_info = &ptn3460_dp_config;
1120         } else {
1121                 struct device_node *node =
1122                         of_find_compatible_node(NULL, NULL, "parade,ps8622");
1123                 if (node) {
1124                         smdk5250_dp_data.video_info = &ps8622_dp_config;
1125                         smdk5250_dp_data.hpd_gpio =
1126                                 of_get_named_gpio(node, "hpd-gpio", 0);
1127                 }
1128         }
1129
1130         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
1131                 "HOST_VBUS_CONTROL")) {
1132                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
1133         } else {
1134                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
1135                 gpio_free(EXYNOS5_GPX2(6));
1136         }
1137
1138         exynos5_i2c_setup();
1139
1140         /*
1141          * MAX77686 PMIC interrupt setup code
1142          * TODO: Convert the device tree wakeup_int domain to support
1143          * pull-up flags
1144          */
1145         s3c_gpio_setpull(EXYNOS5_GPX3(2), S3C_GPIO_PULL_NONE);
1146
1147         /*
1148          * BIG HACK: The wm8994 is not device tree enabled apparently, so
1149          * needs to be added manually.  ...but it's only on SMDK5250.
1150          */
1151         if (of_machine_is_compatible("samsung,smdk5250")) {
1152                 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
1153         }
1154
1155         /* XCLKOUT needs to be moved over to the clock interface, but enable it
1156          * here for now.
1157          */
1158         enable_xclkout();
1159
1160         if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
1161                 printk(KERN_ERR "Spidev ChipSelect unavailable\n");
1162         } else {
1163                 s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
1164                 s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
1165                 s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
1166                 spi_register_board_info(spi1_board_info,
1167                                         ARRAY_SIZE(spi1_board_info));
1168         }
1169
1170         of_platform_populate(NULL, of_default_bus_match_table,
1171                                 exynos5250_auxdata_lookup, NULL);
1172
1173 #ifdef CONFIG_DRM_EXYNOS_FIMD
1174         if (of_machine_is_compatible("google,snow"))
1175                 exynos_dp_gpio_setup_24bpp();
1176         else
1177                 exynos_fimd_gpio_setup_24bpp();
1178 #endif
1179         s5p_tv_setup();
1180
1181         np = of_find_compatible_node(NULL, NULL, "samsung,exynos5-adc");
1182         if (np && of_device_is_available(np)) {
1183                 /* Enable power to ADC */
1184                 __raw_writel(0x1, S5P_ADC_PHY_CONTROL);
1185
1186                 s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor0);
1187                 s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor1);
1188                 s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor2);
1189                 s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor3);
1190
1191                 platform_add_devices(thermistor_devices,
1192                                      ARRAY_SIZE(thermistor_devices));
1193         }
1194
1195 #ifdef CONFIG_BUSFREQ_OPP
1196         dev_add(&busfreq, &exynos5_busfreq.dev);
1197         ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos5_busfreq.dev);
1198         ppmu_init(&exynos_ppmu[PPMU_DDR_C], &exynos5_busfreq.dev);
1199         ppmu_init(&exynos_ppmu[PPMU_DDR_R1], &exynos5_busfreq.dev);
1200         ppmu_init(&exynos_ppmu[PPMU_DDR_L], &exynos5_busfreq.dev);
1201         ppmu_init(&exynos_ppmu[PPMU_RIGHT0_BUS], &exynos5_busfreq.dev);
1202 #endif
1203         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
1204 out:
1205         of_node_put(srom_np);
1206         return;
1207 }
1208
1209 static char const *exynos5250_dt_compat[] __initdata = {
1210         "samsung,exynos5250",
1211         NULL
1212 };
1213
1214 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
1215         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1216         .init_irq       = exynos5_init_irq,
1217         .reserve        = exynos5_reserve,
1218         .map_io         = exynos5250_dt_map_io,
1219         .handle_irq     = gic_handle_irq,
1220         .init_machine   = exynos5250_dt_machine_init,
1221         .timer          = &exynos4_timer,
1222         .dt_compat      = exynos5250_dt_compat,
1223         .restart        = exynos5_restart,
1224 MACHINE_END