2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
73 compatible = "arm,cortex-a53";
75 clocks = <&clockgen 1 0>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a53";
83 clocks = <&clockgen 1 0>;
84 next-level-cache = <&l2>;
89 compatible = "arm,cortex-a53";
91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&l2>;
101 device_type = "memory";
102 reg = <0x0 0x80000000 0 0x80000000>;
103 /* DRAM space 1, size: 2GiB DRAM */
107 compatible = "fixed-clock";
109 clock-frequency = <100000000>;
110 clock-output-names = "sysclk";
114 compatible ="syscon-reboot";
121 compatible = "arm,armv8-timer";
122 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
123 <1 14 0xf08>, /* Physical Non-Secure PPI */
124 <1 11 0xf08>, /* Virtual PPI */
125 <1 10 0xf08>; /* Hypervisor PPI */
130 compatible = "arm,armv8-pmuv3";
131 interrupts = <0 106 0x4>,
135 interrupt-affinity = <&cpu0>,
141 gic: interrupt-controller@1400000 {
142 compatible = "arm,gic-400";
143 #interrupt-cells = <3>;
144 interrupt-controller;
145 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
146 <0x0 0x1402000 0 0x2000>, /* GICC */
147 <0x0 0x1404000 0 0x2000>, /* GICH */
148 <0x0 0x1406000 0 0x2000>; /* GICV */
149 interrupts = <1 9 0xf08>;
153 compatible = "simple-bus";
154 #address-cells = <2>;
158 clockgen: clocking@1ee1000 {
159 compatible = "fsl,ls1043a-clockgen";
160 reg = <0x0 0x1ee1000 0x0 0x1000>;
166 compatible = "fsl,ls1043a-scfg", "syscon";
167 reg = <0x0 0x1570000 0x0 0x10000>;
171 crypto: crypto@1700000 {
172 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
175 #address-cells = <1>;
177 ranges = <0x0 0x00 0x1700000 0x100000>;
178 reg = <0x00 0x1700000 0x0 0x100000>;
179 interrupts = <0 75 0x4>;
182 compatible = "fsl,sec-v5.4-job-ring",
183 "fsl,sec-v5.0-job-ring",
184 "fsl,sec-v4.0-job-ring";
185 reg = <0x10000 0x10000>;
186 interrupts = <0 71 0x4>;
190 compatible = "fsl,sec-v5.4-job-ring",
191 "fsl,sec-v5.0-job-ring",
192 "fsl,sec-v4.0-job-ring";
193 reg = <0x20000 0x10000>;
194 interrupts = <0 72 0x4>;
198 compatible = "fsl,sec-v5.4-job-ring",
199 "fsl,sec-v5.0-job-ring",
200 "fsl,sec-v4.0-job-ring";
201 reg = <0x30000 0x10000>;
202 interrupts = <0 73 0x4>;
206 compatible = "fsl,sec-v5.4-job-ring",
207 "fsl,sec-v5.0-job-ring",
208 "fsl,sec-v4.0-job-ring";
209 reg = <0x40000 0x10000>;
210 interrupts = <0 74 0x4>;
215 compatible = "fsl,ls1043a-dcfg", "syscon";
216 reg = <0x0 0x1ee0000 0x0 0x10000>;
221 compatible = "fsl,ifc", "simple-bus";
222 reg = <0x0 0x1530000 0x0 0x10000>;
223 interrupts = <0 43 0x4>;
226 qspi: quadspi@1550000 {
227 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
228 #address-cells = <1>;
230 reg = <0x0 0x1550000 0x0 0x10000>,
231 <0x0 0x40000000 0x0 0x4000000>;
232 reg-names = "QuadSPI", "QuadSPI-memory";
233 interrupts = <0 99 0x4>;
234 clock-names = "qspi_en", "qspi";
235 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
240 esdhc: esdhc@1560000 {
241 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
242 reg = <0x0 0x1560000 0x0 0x10000>;
243 interrupts = <0 62 0x4>;
244 clock-frequency = <0>;
245 voltage-ranges = <1800 1800 3300 3300>;
251 ddr: memory-controller@1080000 {
252 compatible = "fsl,qoriq-memory-controller";
253 reg = <0x0 0x1080000 0x0 0x1000>;
254 interrupts = <0 144 0x4>;
258 dspi0: dspi@2100000 {
259 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
260 #address-cells = <1>;
262 reg = <0x0 0x2100000 0x0 0x10000>;
263 interrupts = <0 64 0x4>;
264 clock-names = "dspi";
265 clocks = <&clockgen 4 0>;
266 spi-num-chipselects = <5>;
271 dspi1: dspi@2110000 {
272 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
273 #address-cells = <1>;
275 reg = <0x0 0x2110000 0x0 0x10000>;
276 interrupts = <0 65 0x4>;
277 clock-names = "dspi";
278 clocks = <&clockgen 4 0>;
279 spi-num-chipselects = <5>;
285 compatible = "fsl,vf610-i2c";
286 #address-cells = <1>;
288 reg = <0x0 0x2180000 0x0 0x10000>;
289 interrupts = <0 56 0x4>;
291 clocks = <&clockgen 4 0>;
292 dmas = <&edma0 1 39>,
294 dma-names = "tx", "rx";
299 compatible = "fsl,vf610-i2c";
300 #address-cells = <1>;
302 reg = <0x0 0x2190000 0x0 0x10000>;
303 interrupts = <0 57 0x4>;
305 clocks = <&clockgen 4 0>;
310 compatible = "fsl,vf610-i2c";
311 #address-cells = <1>;
313 reg = <0x0 0x21a0000 0x0 0x10000>;
314 interrupts = <0 58 0x4>;
316 clocks = <&clockgen 4 0>;
321 compatible = "fsl,vf610-i2c";
322 #address-cells = <1>;
324 reg = <0x0 0x21b0000 0x0 0x10000>;
325 interrupts = <0 59 0x4>;
327 clocks = <&clockgen 4 0>;
331 duart0: serial@21c0500 {
332 compatible = "fsl,ns16550", "ns16550a";
333 reg = <0x00 0x21c0500 0x0 0x100>;
334 interrupts = <0 54 0x4>;
335 clocks = <&clockgen 4 0>;
338 duart1: serial@21c0600 {
339 compatible = "fsl,ns16550", "ns16550a";
340 reg = <0x00 0x21c0600 0x0 0x100>;
341 interrupts = <0 54 0x4>;
342 clocks = <&clockgen 4 0>;
345 duart2: serial@21d0500 {
346 compatible = "fsl,ns16550", "ns16550a";
347 reg = <0x0 0x21d0500 0x0 0x100>;
348 interrupts = <0 55 0x4>;
349 clocks = <&clockgen 4 0>;
352 duart3: serial@21d0600 {
353 compatible = "fsl,ns16550", "ns16550a";
354 reg = <0x0 0x21d0600 0x0 0x100>;
355 interrupts = <0 55 0x4>;
356 clocks = <&clockgen 4 0>;
359 gpio1: gpio@2300000 {
360 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
361 reg = <0x0 0x2300000 0x0 0x10000>;
362 interrupts = <0 66 0x4>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
369 gpio2: gpio@2310000 {
370 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
371 reg = <0x0 0x2310000 0x0 0x10000>;
372 interrupts = <0 67 0x4>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
379 gpio3: gpio@2320000 {
380 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
381 reg = <0x0 0x2320000 0x0 0x10000>;
382 interrupts = <0 68 0x4>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
389 gpio4: gpio@2330000 {
390 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
391 reg = <0x0 0x2330000 0x0 0x10000>;
392 interrupts = <0 134 0x4>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
399 lpuart0: serial@2950000 {
400 compatible = "fsl,ls1021a-lpuart";
401 reg = <0x0 0x2950000 0x0 0x1000>;
402 interrupts = <0 48 0x4>;
403 clocks = <&clockgen 0 0>;
408 lpuart1: serial@2960000 {
409 compatible = "fsl,ls1021a-lpuart";
410 reg = <0x0 0x2960000 0x0 0x1000>;
411 interrupts = <0 49 0x4>;
412 clocks = <&clockgen 4 0>;
417 lpuart2: serial@2970000 {
418 compatible = "fsl,ls1021a-lpuart";
419 reg = <0x0 0x2970000 0x0 0x1000>;
420 interrupts = <0 50 0x4>;
421 clocks = <&clockgen 4 0>;
426 lpuart3: serial@2980000 {
427 compatible = "fsl,ls1021a-lpuart";
428 reg = <0x0 0x2980000 0x0 0x1000>;
429 interrupts = <0 51 0x4>;
430 clocks = <&clockgen 4 0>;
435 lpuart4: serial@2990000 {
436 compatible = "fsl,ls1021a-lpuart";
437 reg = <0x0 0x2990000 0x0 0x1000>;
438 interrupts = <0 52 0x4>;
439 clocks = <&clockgen 4 0>;
444 lpuart5: serial@29a0000 {
445 compatible = "fsl,ls1021a-lpuart";
446 reg = <0x0 0x29a0000 0x0 0x1000>;
447 interrupts = <0 53 0x4>;
448 clocks = <&clockgen 4 0>;
453 wdog0: wdog@2ad0000 {
454 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
455 reg = <0x0 0x2ad0000 0x0 0x10000>;
456 interrupts = <0 83 0x4>;
457 clocks = <&clockgen 4 0>;
458 clock-names = "wdog";
462 edma0: edma@2c00000 {
464 compatible = "fsl,vf610-edma";
465 reg = <0x0 0x2c00000 0x0 0x10000>,
466 <0x0 0x2c10000 0x0 0x10000>,
467 <0x0 0x2c20000 0x0 0x10000>;
468 interrupts = <0 103 0x4>,
470 interrupt-names = "edma-tx", "edma-err";
473 clock-names = "dmamux0", "dmamux1";
474 clocks = <&clockgen 4 0>,
479 compatible = "snps,dwc3";
480 reg = <0x0 0x2f00000 0x0 0x10000>;
481 interrupts = <0 60 0x4>;
483 snps,quirk-frame-length-adjustment = <0x20>;
484 snps,dis_rxdet_inp3_quirk;
488 compatible = "snps,dwc3";
489 reg = <0x0 0x3000000 0x0 0x10000>;
490 interrupts = <0 61 0x4>;
492 snps,quirk-frame-length-adjustment = <0x20>;
493 snps,dis_rxdet_inp3_quirk;
497 compatible = "snps,dwc3";
498 reg = <0x0 0x3100000 0x0 0x10000>;
499 interrupts = <0 63 0x4>;
501 snps,quirk-frame-length-adjustment = <0x20>;
502 snps,dis_rxdet_inp3_quirk;
506 compatible = "fsl,ls1043a-ahci";
507 reg = <0x0 0x3200000 0x0 0x10000>;
508 interrupts = <0 69 0x4>;
509 clocks = <&clockgen 4 0>;
513 msi1: msi-controller1@1571000 {
514 compatible = "fsl,1s1043a-msi";
515 reg = <0x0 0x1571000 0x0 0x8>;
517 interrupts = <0 116 0x4>;
520 msi2: msi-controller2@1572000 {
521 compatible = "fsl,1s1043a-msi";
522 reg = <0x0 0x1572000 0x0 0x8>;
524 interrupts = <0 126 0x4>;
527 msi3: msi-controller3@1573000 {
528 compatible = "fsl,1s1043a-msi";
529 reg = <0x0 0x1573000 0x0 0x8>;
531 interrupts = <0 160 0x4>;
535 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
536 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
537 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
538 reg-names = "regs", "config";
539 interrupts = <0 118 0x4>, /* controller interrupt */
540 <0 117 0x4>; /* PME interrupt */
541 interrupt-names = "intr", "pme";
542 #address-cells = <3>;
547 bus-range = <0x0 0xff>;
548 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
549 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
550 msi-parent = <&msi1>;
551 #interrupt-cells = <1>;
552 interrupt-map-mask = <0 0 0 7>;
553 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
554 <0000 0 0 2 &gic 0 111 0x4>,
555 <0000 0 0 3 &gic 0 112 0x4>,
556 <0000 0 0 4 &gic 0 113 0x4>;
560 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
561 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
562 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
563 reg-names = "regs", "config";
564 interrupts = <0 128 0x4>,
566 interrupt-names = "intr", "pme";
567 #address-cells = <3>;
572 bus-range = <0x0 0xff>;
573 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
574 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
575 msi-parent = <&msi2>;
576 #interrupt-cells = <1>;
577 interrupt-map-mask = <0 0 0 7>;
578 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
579 <0000 0 0 2 &gic 0 121 0x4>,
580 <0000 0 0 3 &gic 0 122 0x4>,
581 <0000 0 0 4 &gic 0 123 0x4>;
585 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
586 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
587 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
588 reg-names = "regs", "config";
589 interrupts = <0 162 0x4>,
591 interrupt-names = "intr", "pme";
592 #address-cells = <3>;
597 bus-range = <0x0 0xff>;
598 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
599 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
600 msi-parent = <&msi3>;
601 #interrupt-cells = <1>;
602 interrupt-map-mask = <0 0 0 7>;
603 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
604 <0000 0 0 2 &gic 0 155 0x4>,
605 <0000 0 0 3 &gic 0 156 0x4>,
606 <0000 0 0 4 &gic 0 157 0x4>;