arch/mips/boot/dts/brcm/bcm7358.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "brcm,bcm7358";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 mips-hpt-frequency = <375000000>;
  11
  12                 cpu@0 {
  13                         compatible = "brcm,bmips3300";
  14                         device_type = "cpu";
  15                         reg = <0>;
  16                 };
  17         };
  18
  19         aliases {
  20                 uart0 = &uart0;
  21         };
  22
  23         cpu_intc: interrupt-controller {
  24                 #address-cells = <0>;
  25                 compatible = "mti,cpu-interrupt-controller";
  26
  27                 interrupt-controller;
  28                 #interrupt-cells = <1>;
  29         };
  30
  31         clocks {
  32                 uart_clk: uart_clk {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <81000000>;
  36                 };
  37
  38                 upg_clk: upg_clk {
  39                         compatible = "fixed-clock";
  40                         #clock-cells = <0>;
  41                         clock-frequency = <27000000>;
  42                 };
  43         };
  44
  45         rdb {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48
  49                 compatible = "simple-bus";
  50                 ranges = <0 0x10000000 0x01000000>;
  51
  52                 periph_intc: interrupt-controller@411400 {
  53                         compatible = "brcm,bcm7038-l1-intc";
  54                         reg = <0x411400 0x30>;
  55
  56                         interrupt-controller;
  57                         #interrupt-cells = <1>;
  58
  59                         interrupt-parent = <&cpu_intc>;
  60                         interrupts = <2>;
  61                 };
  62
  63                 sun_l2_intc: interrupt-controller@403000 {
  64                         compatible = "brcm,l2-intc";
  65                         reg = <0x403000 0x30>;
  66                         interrupt-controller;
  67                         #interrupt-cells = <1>;
  68                         interrupt-parent = <&periph_intc>;
  69                         interrupts = <48>;
  70                 };
  71
  72                 gisb-arb@400000 {
  73                         compatible = "brcm,bcm7400-gisb-arb";
  74                         reg = <0x400000 0xdc>;
  75                         native-endian;
  76                         interrupt-parent = <&sun_l2_intc>;
  77                         interrupts = <0>, <2>;
  78                         brcm,gisb-arb-master-mask = <0x2f3>;
  79                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  80                                                      "rdc_0", "raaga_0",
  81                                                      "avd_0", "jtag_0";
  82                 };
  83
  84                 upg_irq0_intc: interrupt-controller@406600 {
  85                         compatible = "brcm,bcm7120-l2-intc";
  86                         reg = <0x406600 0x8>;
  87
  88                         brcm,int-map-mask = <0x44>, <0x7000000>;
  89                         brcm,int-fwd-mask = <0x70000>;
  90
  91                         interrupt-controller;
  92                         #interrupt-cells = <1>;
  93
  94                         interrupt-parent = <&periph_intc>;
  95                         interrupts = <56>, <54>;
  96                         interrupt-names = "upg_main", "upg_bsc";
  97                 };
  98
  99                 upg_aon_irq0_intc: interrupt-controller@408b80 {
 100                         compatible = "brcm,bcm7120-l2-intc";
 101                         reg = <0x408b80 0x8>;
 102
 103                         brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
 104                         brcm,int-fwd-mask = <0>;
 105                         brcm,irq-can-wake;
 106
 107                         interrupt-controller;
 108                         #interrupt-cells = <1>;
 109
 110                         interrupt-parent = <&periph_intc>;
 111                         interrupts = <57>, <55>, <59>;
 112                         interrupt-names = "upg_main_aon", "upg_bsc_aon",
 113                                           "upg_spi";
 114                 };
 115
 116                 sun_top_ctrl: syscon@404000 {
 117                         compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
 118                         reg = <0x404000 0x51c>;
 119                         native-endian;
 120                 };
 121
 122                 reboot {
 123                         compatible = "brcm,brcmstb-reboot";
 124                         syscon = <&sun_top_ctrl 0x304 0x308>;
 125                 };
 126
 127                 uart0: serial@406800 {
 128                         compatible = "ns16550a";
 129                         reg = <0x406800 0x20>;
 130                         reg-io-width = <0x4>;
 131                         reg-shift = <0x2>;
 132                         native-endian;
 133                         interrupt-parent = <&periph_intc>;
 134                         interrupts = <61>;
 135                         clocks = <&uart_clk>;
 136                         status = "disabled";
 137                 };
 138
 139                 uart1: serial@406840 {
 140                         compatible = "ns16550a";
 141                         reg = <0x406840 0x20>;
 142                         reg-io-width = <0x4>;
 143                         reg-shift = <0x2>;
 144                         native-endian;
 145                         interrupt-parent = <&periph_intc>;
 146                         interrupts = <62>;
 147                         clocks = <&uart_clk>;
 148                         status = "disabled";
 149                 };
 150
 151                 uart2: serial@406880 {
 152                         compatible = "ns16550a";
 153                         reg = <0x406880 0x20>;
 154                         reg-io-width = <0x4>;
 155                         reg-shift = <0x2>;
 156                         native-endian;
 157                         interrupt-parent = <&periph_intc>;
 158                         interrupts = <63>;
 159                         clocks = <&uart_clk>;
 160                         status = "disabled";
 161                 };
 162
 163                 bsca: i2c@406200 {
 164                       clock-frequency = <390000>;
 165                       compatible = "brcm,brcmstb-i2c";
 166                       interrupt-parent = <&upg_irq0_intc>;
 167                       reg = <0x406200 0x58>;
 168                       interrupts = <24>;
 169                       interrupt-names = "upg_bsca";
 170                       status = "disabled";
 171                 };
 172
 173                 bscb: i2c@406280 {
 174                       clock-frequency = <390000>;
 175                       compatible = "brcm,brcmstb-i2c";
 176                       interrupt-parent = <&upg_irq0_intc>;
 177                       reg = <0x406280 0x58>;
 178                       interrupts = <25>;
 179                       interrupt-names = "upg_bscb";
 180                       status = "disabled";
 181                 };
 182
 183                 bscc: i2c@406300 {
 184                       clock-frequency = <390000>;
 185                       compatible = "brcm,brcmstb-i2c";
 186                       interrupt-parent = <&upg_irq0_intc>;
 187                       reg = <0x406300 0x58>;
 188                       interrupts = <26>;
 189                       interrupt-names = "upg_bscc";
 190                       status = "disabled";
 191                 };
 192
 193                 bscd: i2c@408980 {
 194                       clock-frequency = <390000>;
 195                       compatible = "brcm,brcmstb-i2c";
 196                       interrupt-parent = <&upg_aon_irq0_intc>;
 197                       reg = <0x408980 0x58>;
 198                       interrupts = <27>;
 199                       interrupt-names = "upg_bscd";
 200                       status = "disabled";
 201                 };
 202
 203                 pwma: pwm@406400 {
 204                         compatible = "brcm,bcm7038-pwm";
 205                         reg = <0x406400 0x28>;
 206                         #pwm-cells = <2>;
 207                         clocks = <&upg_clk>;
 208                         status = "disabled";
 209                 };
 210
 211                 pwmb: pwm@406700 {
 212                         compatible = "brcm,bcm7038-pwm";
 213                         reg = <0x406700 0x28>;
 214                         #pwm-cells = <2>;
 215                         clocks = <&upg_clk>;
 216                         status = "disabled";
 217                 };
 218
 219                 aon_pm_l2_intc: interrupt-controller@408240 {
 220                         compatible = "brcm,l2-intc";
 221                         reg = <0x408240 0x30>;
 222                         interrupt-controller;
 223                         #interrupt-cells = <1>;
 224                         interrupt-parent = <&periph_intc>;
 225                         interrupts = <50>;
 226                         brcm,irq-can-wake;
 227                 };
 228
 229                 upg_gio: gpio@406500 {
 230                         compatible = "brcm,brcmstb-gpio";
 231                         reg = <0x406500 0xa0>;
 232                         #gpio-cells = <2>;
 233                         #interrupt-cells = <2>;
 234                         gpio-controller;
 235                         interrupt-controller;
 236                         interrupt-parent = <&upg_irq0_intc>;
 237                         interrupts = <6>;
 238                         brcm,gpio-bank-widths = <32 32 32 29 4>;
 239                 };
 240
 241                 upg_gio_aon: gpio@408c00 {
 242                         compatible = "brcm,brcmstb-gpio";
 243                         reg = <0x408c00 0x60>;
 244                         #gpio-cells = <2>;
 245                         #interrupt-cells = <2>;
 246                         gpio-controller;
 247                         interrupt-controller;
 248                         interrupt-parent = <&upg_aon_irq0_intc>;
 249                         interrupts = <6>;
 250                         interrupts-extended = <&upg_aon_irq0_intc 6>,
 251                                               <&aon_pm_l2_intc 5>;
 252                         wakeup-source;
 253                         brcm,gpio-bank-widths = <21 32 2>;
 254                 };
 255
 256                 enet0: ethernet@430000 {
 257                         phy-mode = "internal";
 258                         phy-handle = <&phy1>;
 259                         mac-address = [ 00 10 18 36 23 1a ];
 260                         compatible = "brcm,genet-v2";
 261                         #address-cells = <0x1>;
 262                         #size-cells = <0x1>;
 263                         reg = <0x430000 0x4c8c>;
 264                         interrupts = <24>, <25>;
 265                         interrupt-parent = <&periph_intc>;
 266                         status = "disabled";
 267
 268                         mdio@e14 {
 269                                 compatible = "brcm,genet-mdio-v2";
 270                                 #address-cells = <0x1>;
 271                                 #size-cells = <0x0>;
 272                                 reg = <0xe14 0x8>;
 273
 274                                 phy1: ethernet-phy@1 {
 275                                         max-speed = <100>;
 276                                         reg = <0x1>;
 277                                         compatible = "brcm,40nm-ephy",
 278                                                 "ethernet-phy-ieee802.3-c22";
 279                                 };
 280                         };
 281                 };
 282
 283                 ehci0: usb@480300 {
 284                         compatible = "brcm,bcm7358-ehci", "generic-ehci";
 285                         reg = <0x480300 0x100>;
 286                         native-endian;
 287                         interrupt-parent = <&periph_intc>;
 288                         interrupts = <65>;
 289                         status = "disabled";
 290                 };
 291
 292                 ohci0: usb@480400 {
 293                         compatible = "brcm,bcm7358-ohci", "generic-ohci";
 294                         reg = <0x480400 0x100>;
 295                         native-endian;
 296                         no-big-frame-no;
 297                         interrupt-parent = <&periph_intc>;
 298                         interrupts = <66>;
 299                         status = "disabled";
 300                 };
 301
 302                 hif_l2_intc: interrupt-controller@411000 {
 303                         compatible = "brcm,l2-intc";
 304                         reg = <0x411000 0x30>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <1>;
 307                         interrupt-parent = <&periph_intc>;
 308                         interrupts = <30>;
 309                 };
 310
 311                 nand: nand@412800 {
 312                         compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         reg-names = "nand";
 316                         reg = <0x412800 0x400>;
 317                         interrupt-parent = <&hif_l2_intc>;
 318                         interrupts = <24>;
 319                         status = "disabled";
 320                 };
 321         };
 322 };