arch/mips/include/asm/mips-cm.h

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #ifndef __MIPS_ASM_MIPS_CM_H__
  12 #define __MIPS_ASM_MIPS_CM_H__
  13
  14 #include <linux/bitops.h>
  15 #include <linux/errno.h>
  16 #include <linux/io.h>
  17 #include <linux/types.h>
  18
  19 /* The base address of the CM GCR block */
  20 extern void __iomem *mips_cm_base;
  21
  22 /* The base address of the CM L2-only sync region */
  23 extern void __iomem *mips_cm_l2sync_base;
  24
  25 /**
  26  * __mips_cm_phys_base - retrieve the physical base address of the CM
  27  *
  28  * This function returns the physical base address of the Coherence Manager
  29  * global control block, or 0 if no Coherence Manager is present. It provides
  30  * a default implementation which reads the CMGCRBase register where available,
  31  * and may be overridden by platforms which determine this address in a
  32  * different way by defining a function with the same prototype except for the
  33  * name mips_cm_phys_base (without underscores).
  34  */
  35 extern phys_addr_t __mips_cm_phys_base(void);
  36
  37 /*
  38  * mips_cm_is64 - determine CM register width
  39  *
  40  * The CM register width is determined by the version of the CM, with CM3
  41  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
  42  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
  43  * or vice-versa. This variable indicates the width of the memory accesses
  44  * that the kernel will perform to GCRs, which may differ from the actual
  45  * width of the GCRs.
  46  *
  47  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
  48  */
  49 extern int mips_cm_is64;
  50
  51 /**
  52  * mips_cm_error_report - Report CM cache errors
  53  */
  54 #ifdef CONFIG_MIPS_CM
  55 extern void mips_cm_error_report(void);
  56 #else
  57 static inline void mips_cm_error_report(void) {}
  58 #endif
  59
  60 /**
  61  * mips_cm_probe - probe for a Coherence Manager
  62  *
  63  * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
  64  * is successfully detected, else -errno.
  65  */
  66 #ifdef CONFIG_MIPS_CM
  67 extern int mips_cm_probe(void);
  68 #else
  69 static inline int mips_cm_probe(void)
  70 {
  71         return -ENODEV;
  72 }
  73 #endif
  74
  75 /**
  76  * mips_cm_present - determine whether a Coherence Manager is present
  77  *
  78  * Returns true if a CM is present in the system, else false.
  79  */
  80 static inline bool mips_cm_present(void)
  81 {
  82 #ifdef CONFIG_MIPS_CM
  83         return mips_cm_base != NULL;
  84 #else
  85         return false;
  86 #endif
  87 }
  88
  89 /**
  90  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
  91  *
  92  * Returns true if the system implements an L2-only sync region, else false.
  93  */
  94 static inline bool mips_cm_has_l2sync(void)
  95 {
  96 #ifdef CONFIG_MIPS_CM
  97         return mips_cm_l2sync_base != NULL;
  98 #else
  99         return false;
 100 #endif
 101 }
 102
 103 /* Offsets to register blocks from the CM base address */
 104 #define MIPS_CM_GCB_OFS         0x0000 /* Global Control Block */
 105 #define MIPS_CM_CLCB_OFS        0x2000 /* Core Local Control Block */
 106 #define MIPS_CM_COCB_OFS        0x4000 /* Core Other Control Block */
 107 #define MIPS_CM_GDB_OFS         0x6000 /* Global Debug Block */
 108
 109 /* Total size of the CM memory mapped registers */
 110 #define MIPS_CM_GCR_SIZE        0x8000
 111
 112 /* Size of the L2-only sync region */
 113 #define MIPS_CM_L2SYNC_SIZE     0x1000
 114
 115 /* Macros to ease the creation of register access functions */
 116 #define BUILD_CM_R_(name, off)                                  \
 117 static inline unsigned long __iomem *addr_gcr_##name(void)      \
 118 {                                                               \
 119         return (unsigned long __iomem *)(mips_cm_base + (off)); \
 120 }                                                               \
 121                                                                 \
 122 static inline u32 read32_gcr_##name(void)                       \
 123 {                                                               \
 124         return __raw_readl(addr_gcr_##name());                  \
 125 }                                                               \
 126                                                                 \
 127 static inline u64 read64_gcr_##name(void)                       \
 128 {                                                               \
 129         void __iomem *addr = addr_gcr_##name();                 \
 130         u64 ret;                                                \
 131                                                                 \
 132         if (mips_cm_is64) {                                     \
 133                 ret = __raw_readq(addr);                        \
 134         } else {                                                \
 135                 ret = __raw_readl(addr);                        \
 136                 ret |= (u64)__raw_readl(addr + 0x4) << 32;      \
 137         }                                                       \
 138                                                                 \
 139         return ret;                                             \
 140 }                                                               \
 141                                                                 \
 142 static inline unsigned long read_gcr_##name(void)               \
 143 {                                                               \
 144         if (mips_cm_is64)                                       \
 145                 return read64_gcr_##name();                     \
 146         else                                                    \
 147                 return read32_gcr_##name();                     \
 148 }
 149
 150 #define BUILD_CM__W(name, off)                                  \
 151 static inline void write32_gcr_##name(u32 value)                \
 152 {                                                               \
 153         __raw_writel(value, addr_gcr_##name());                 \
 154 }                                                               \
 155                                                                 \
 156 static inline void write64_gcr_##name(u64 value)                \
 157 {                                                               \
 158         __raw_writeq(value, addr_gcr_##name());                 \
 159 }                                                               \
 160                                                                 \
 161 static inline void write_gcr_##name(unsigned long value)        \
 162 {                                                               \
 163         if (mips_cm_is64)                                       \
 164                 write64_gcr_##name(value);                      \
 165         else                                                    \
 166                 write32_gcr_##name(value);                      \
 167 }
 168
 169 #define BUILD_CM_RW(name, off)                                  \
 170         BUILD_CM_R_(name, off)                                  \
 171         BUILD_CM__W(name, off)
 172
 173 #define BUILD_CM_Cx_R_(name, off)                               \
 174         BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off))        \
 175         BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
 176
 177 #define BUILD_CM_Cx__W(name, off)                               \
 178         BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off))        \
 179         BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
 180
 181 #define BUILD_CM_Cx_RW(name, off)                               \
 182         BUILD_CM_Cx_R_(name, off)                               \
 183         BUILD_CM_Cx__W(name, off)
 184
 185 /* GCB register accessor functions */
 186 BUILD_CM_R_(config,             MIPS_CM_GCB_OFS + 0x00)
 187 BUILD_CM_RW(base,               MIPS_CM_GCB_OFS + 0x08)
 188 BUILD_CM_RW(access,             MIPS_CM_GCB_OFS + 0x20)
 189 BUILD_CM_R_(rev,                MIPS_CM_GCB_OFS + 0x30)
 190 BUILD_CM_RW(error_mask,         MIPS_CM_GCB_OFS + 0x40)
 191 BUILD_CM_RW(error_cause,        MIPS_CM_GCB_OFS + 0x48)
 192 BUILD_CM_RW(error_addr,         MIPS_CM_GCB_OFS + 0x50)
 193 BUILD_CM_RW(error_mult,         MIPS_CM_GCB_OFS + 0x58)
 194 BUILD_CM_RW(l2_only_sync_base,  MIPS_CM_GCB_OFS + 0x70)
 195 BUILD_CM_RW(gic_base,           MIPS_CM_GCB_OFS + 0x80)
 196 BUILD_CM_RW(cpc_base,           MIPS_CM_GCB_OFS + 0x88)
 197 BUILD_CM_RW(reg0_base,          MIPS_CM_GCB_OFS + 0x90)
 198 BUILD_CM_RW(reg0_mask,          MIPS_CM_GCB_OFS + 0x98)
 199 BUILD_CM_RW(reg1_base,          MIPS_CM_GCB_OFS + 0xa0)
 200 BUILD_CM_RW(reg1_mask,          MIPS_CM_GCB_OFS + 0xa8)
 201 BUILD_CM_RW(reg2_base,          MIPS_CM_GCB_OFS + 0xb0)
 202 BUILD_CM_RW(reg2_mask,          MIPS_CM_GCB_OFS + 0xb8)
 203 BUILD_CM_RW(reg3_base,          MIPS_CM_GCB_OFS + 0xc0)
 204 BUILD_CM_RW(reg3_mask,          MIPS_CM_GCB_OFS + 0xc8)
 205 BUILD_CM_R_(gic_status,         MIPS_CM_GCB_OFS + 0xd0)
 206 BUILD_CM_R_(cpc_status,         MIPS_CM_GCB_OFS + 0xf0)
 207 BUILD_CM_RW(l2_config,          MIPS_CM_GCB_OFS + 0x130)
 208 BUILD_CM_RW(sys_config2,        MIPS_CM_GCB_OFS + 0x150)
 209 BUILD_CM_RW(l2_pft_control,     MIPS_CM_GCB_OFS + 0x300)
 210 BUILD_CM_RW(l2_pft_control_b,   MIPS_CM_GCB_OFS + 0x308)
 211 BUILD_CM_RW(bev_base,           MIPS_CM_GCB_OFS + 0x680)
 212
 213 /* Core Local & Core Other register accessor functions */
 214 BUILD_CM_Cx_RW(reset_release,   0x00)
 215 BUILD_CM_Cx_RW(coherence,       0x08)
 216 BUILD_CM_Cx_R_(config,          0x10)
 217 BUILD_CM_Cx_RW(other,           0x18)
 218 BUILD_CM_Cx_RW(reset_base,      0x20)
 219 BUILD_CM_Cx_R_(id,              0x28)
 220 BUILD_CM_Cx_RW(reset_ext_base,  0x30)
 221 BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
 222 BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
 223 BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
 224 BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
 225 BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
 226 BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
 227 BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
 228 BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
 229 BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
 230
 231 /* GCR_CONFIG register fields */
 232 #define CM_GCR_CONFIG_NUMIOCU_SHF               8
 233 #define CM_GCR_CONFIG_NUMIOCU_MSK               (_ULCAST_(0xf) << 8)
 234 #define CM_GCR_CONFIG_PCORES_SHF                0
 235 #define CM_GCR_CONFIG_PCORES_MSK                (_ULCAST_(0xff) << 0)
 236
 237 /* GCR_BASE register fields */
 238 #define CM_GCR_BASE_GCRBASE_SHF                 15
 239 #define CM_GCR_BASE_GCRBASE_MSK                 (_ULCAST_(0x1ffff) << 15)
 240 #define CM_GCR_BASE_CMDEFTGT_SHF                0
 241 #define CM_GCR_BASE_CMDEFTGT_MSK                (_ULCAST_(0x3) << 0)
 242 #define  CM_GCR_BASE_CMDEFTGT_DISABLED          0
 243 #define  CM_GCR_BASE_CMDEFTGT_MEM               1
 244 #define  CM_GCR_BASE_CMDEFTGT_IOCU0             2
 245 #define  CM_GCR_BASE_CMDEFTGT_IOCU1             3
 246
 247 /* GCR_RESET_EXT_BASE register fields */
 248 #define CM_GCR_RESET_EXT_BASE_EVARESET          BIT(31)
 249 #define CM_GCR_RESET_EXT_BASE_UEB               BIT(30)
 250
 251 /* GCR_ACCESS register fields */
 252 #define CM_GCR_ACCESS_ACCESSEN_SHF              0
 253 #define CM_GCR_ACCESS_ACCESSEN_MSK              (_ULCAST_(0xff) << 0)
 254
 255 /* GCR_REV register fields */
 256 #define CM_GCR_REV_MAJOR_SHF                    8
 257 #define CM_GCR_REV_MAJOR_MSK                    (_ULCAST_(0xff) << 8)
 258 #define CM_GCR_REV_MINOR_SHF                    0
 259 #define CM_GCR_REV_MINOR_MSK                    (_ULCAST_(0xff) << 0)
 260
 261 #define CM_ENCODE_REV(major, minor) \
 262                 (((major) << CM_GCR_REV_MAJOR_SHF) | \
 263                  ((minor) << CM_GCR_REV_MINOR_SHF))
 264
 265 #define CM_REV_CM2                              CM_ENCODE_REV(6, 0)
 266 #define CM_REV_CM2_5                            CM_ENCODE_REV(7, 0)
 267 #define CM_REV_CM3                              CM_ENCODE_REV(8, 0)
 268
 269 /* GCR_ERROR_CAUSE register fields */
 270 #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF          27
 271 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK          (_ULCAST_(0x1f) << 27)
 272 #define CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF         58
 273 #define CM3_GCR_ERROR_CAUSE_ERRTYPE_MSK         GENMASK_ULL(63, 58)
 274 #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF          0
 275 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK          (_ULCAST_(0x7ffffff) << 0)
 276
 277 /* GCR_ERROR_MULT register fields */
 278 #define CM_GCR_ERROR_MULT_ERR2ND_SHF            0
 279 #define CM_GCR_ERROR_MULT_ERR2ND_MSK            (_ULCAST_(0x1f) << 0)
 280
 281 /* GCR_L2_ONLY_SYNC_BASE register fields */
 282 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF   12
 283 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK   (_ULCAST_(0xfffff) << 12)
 284 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF     0
 285 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK     (_ULCAST_(0x1) << 0)
 286
 287 /* GCR_GIC_BASE register fields */
 288 #define CM_GCR_GIC_BASE_GICBASE_SHF             17
 289 #define CM_GCR_GIC_BASE_GICBASE_MSK             (_ULCAST_(0x7fff) << 17)
 290 #define CM_GCR_GIC_BASE_GICEN_SHF               0
 291 #define CM_GCR_GIC_BASE_GICEN_MSK               (_ULCAST_(0x1) << 0)
 292
 293 /* GCR_CPC_BASE register fields */
 294 #define CM_GCR_CPC_BASE_CPCBASE_SHF             15
 295 #define CM_GCR_CPC_BASE_CPCBASE_MSK             (_ULCAST_(0x1ffff) << 15)
 296 #define CM_GCR_CPC_BASE_CPCEN_SHF               0
 297 #define CM_GCR_CPC_BASE_CPCEN_MSK               (_ULCAST_(0x1) << 0)
 298
 299 /* GCR_GIC_STATUS register fields */
 300 #define CM_GCR_GIC_STATUS_GICEX_SHF             0
 301 #define CM_GCR_GIC_STATUS_GICEX_MSK             (_ULCAST_(0x1) << 0)
 302
 303 /* GCR_REGn_BASE register fields */
 304 #define CM_GCR_REGn_BASE_BASEADDR_SHF           16
 305 #define CM_GCR_REGn_BASE_BASEADDR_MSK           (_ULCAST_(0xffff) << 16)
 306
 307 /* GCR_REGn_MASK register fields */
 308 #define CM_GCR_REGn_MASK_ADDRMASK_SHF           16
 309 #define CM_GCR_REGn_MASK_ADDRMASK_MSK           (_ULCAST_(0xffff) << 16)
 310 #define CM_GCR_REGn_MASK_CCAOVR_SHF             5
 311 #define CM_GCR_REGn_MASK_CCAOVR_MSK             (_ULCAST_(0x3) << 5)
 312 #define CM_GCR_REGn_MASK_CCAOVREN_SHF           4
 313 #define CM_GCR_REGn_MASK_CCAOVREN_MSK           (_ULCAST_(0x1) << 4)
 314 #define CM_GCR_REGn_MASK_DROPL2_SHF             2
 315 #define CM_GCR_REGn_MASK_DROPL2_MSK             (_ULCAST_(0x1) << 2)
 316 #define CM_GCR_REGn_MASK_CMTGT_SHF              0
 317 #define CM_GCR_REGn_MASK_CMTGT_MSK              (_ULCAST_(0x3) << 0)
 318 #define  CM_GCR_REGn_MASK_CMTGT_DISABLED        (_ULCAST_(0x0) << 0)
 319 #define  CM_GCR_REGn_MASK_CMTGT_MEM             (_ULCAST_(0x1) << 0)
 320 #define  CM_GCR_REGn_MASK_CMTGT_IOCU0           (_ULCAST_(0x2) << 0)
 321 #define  CM_GCR_REGn_MASK_CMTGT_IOCU1           (_ULCAST_(0x3) << 0)
 322
 323 /* GCR_GIC_STATUS register fields */
 324 #define CM_GCR_GIC_STATUS_EX_SHF                0
 325 #define CM_GCR_GIC_STATUS_EX_MSK                (_ULCAST_(0x1) << 0)
 326
 327 /* GCR_CPC_STATUS register fields */
 328 #define CM_GCR_CPC_STATUS_EX_SHF                0
 329 #define CM_GCR_CPC_STATUS_EX_MSK                (_ULCAST_(0x1) << 0)
 330
 331 /* GCR_L2_CONFIG register fields */
 332 #define CM_GCR_L2_CONFIG_BYPASS_SHF             20
 333 #define CM_GCR_L2_CONFIG_BYPASS_MSK             (_ULCAST_(0x1) << 20)
 334 #define CM_GCR_L2_CONFIG_SET_SIZE_SHF           12
 335 #define CM_GCR_L2_CONFIG_SET_SIZE_MSK           (_ULCAST_(0xf) << 12)
 336 #define CM_GCR_L2_CONFIG_LINE_SIZE_SHF          8
 337 #define CM_GCR_L2_CONFIG_LINE_SIZE_MSK          (_ULCAST_(0xf) << 8)
 338 #define CM_GCR_L2_CONFIG_ASSOC_SHF              0
 339 #define CM_GCR_L2_CONFIG_ASSOC_MSK              (_ULCAST_(0xff) << 0)
 340
 341 /* GCR_SYS_CONFIG2 register fields */
 342 #define CM_GCR_SYS_CONFIG2_MAXVPW_SHF           0
 343 #define CM_GCR_SYS_CONFIG2_MAXVPW_MSK           (_ULCAST_(0xf) << 0)
 344
 345 /* GCR_L2_PFT_CONTROL register fields */
 346 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF      12
 347 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK      (_ULCAST_(0xfffff) << 12)
 348 #define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF         8
 349 #define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK         (_ULCAST_(0x1) << 8)
 350 #define CM_GCR_L2_PFT_CONTROL_NPFT_SHF          0
 351 #define CM_GCR_L2_PFT_CONTROL_NPFT_MSK          (_ULCAST_(0xff) << 0)
 352
 353 /* GCR_L2_PFT_CONTROL_B register fields */
 354 #define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF         8
 355 #define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK         (_ULCAST_(0x1) << 8)
 356 #define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF      0
 357 #define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK      (_ULCAST_(0xff) << 0)
 358
 359 /* GCR_Cx_COHERENCE register fields */
 360 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF     0
 361 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK     (_ULCAST_(0xff) << 0)
 362 #define CM3_GCR_Cx_COHERENCE_COHEN_MSK          (_ULCAST_(0x1) << 0)
 363
 364 /* GCR_Cx_CONFIG register fields */
 365 #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF           10
 366 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK           (_ULCAST_(0x3) << 10)
 367 #define CM_GCR_Cx_CONFIG_PVPE_SHF               0
 368 #define CM_GCR_Cx_CONFIG_PVPE_MSK               (_ULCAST_(0x3ff) << 0)
 369
 370 /* GCR_Cx_OTHER register fields */
 371 #define CM_GCR_Cx_OTHER_CORENUM_SHF             16
 372 #define CM_GCR_Cx_OTHER_CORENUM_MSK             (_ULCAST_(0xffff) << 16)
 373 #define CM3_GCR_Cx_OTHER_CORE_SHF               8
 374 #define CM3_GCR_Cx_OTHER_CORE_MSK               (_ULCAST_(0x3f) << 8)
 375 #define CM3_GCR_Cx_OTHER_VP_SHF                 0
 376 #define CM3_GCR_Cx_OTHER_VP_MSK                 (_ULCAST_(0x7) << 0)
 377
 378 /* GCR_Cx_RESET_BASE register fields */
 379 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF     12
 380 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK     (_ULCAST_(0xfffff) << 12)
 381
 382 /* GCR_Cx_RESET_EXT_BASE register fields */
 383 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF   31
 384 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK   (_ULCAST_(0x1) << 31)
 385 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF        30
 386 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK        (_ULCAST_(0x1) << 30)
 387 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20
 388 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
 389 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF   1
 390 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK   (_ULCAST_(0x7f) << 1)
 391 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF    0
 392 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK    (_ULCAST_(0x1) << 0)
 393
 394 /**
 395  * mips_cm_numcores - return the number of cores present in the system
 396  *
 397  * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
 398  * zero if no Coherence Manager is present.
 399  */
 400 static inline unsigned mips_cm_numcores(void)
 401 {
 402         if (!mips_cm_present())
 403                 return 0;
 404
 405         return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
 406                 >> CM_GCR_CONFIG_PCORES_SHF) + 1;
 407 }
 408
 409 /**
 410  * mips_cm_numiocu - return the number of IOCUs present in the system
 411  *
 412  * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
 413  * if no Coherence Manager is present.
 414  */
 415 static inline unsigned mips_cm_numiocu(void)
 416 {
 417         if (!mips_cm_present())
 418                 return 0;
 419
 420         return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
 421                 >> CM_GCR_CONFIG_NUMIOCU_SHF;
 422 }
 423
 424 /**
 425  * mips_cm_l2sync - perform an L2-only sync operation
 426  *
 427  * If an L2-only sync region is present in the system then this function
 428  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
 429  */
 430 static inline int mips_cm_l2sync(void)
 431 {
 432         if (!mips_cm_has_l2sync())
 433                 return -ENODEV;
 434
 435         writel(0, mips_cm_l2sync_base);
 436         return 0;
 437 }
 438
 439 /**
 440  * mips_cm_revision() - return CM revision
 441  *
 442  * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
 443  * return value should be checked against the CM_REV_* macros.
 444  */
 445 static inline int mips_cm_revision(void)
 446 {
 447         if (!mips_cm_present())
 448                 return 0;
 449
 450         return read_gcr_rev();
 451 }
 452
 453 /**
 454  * mips_cm_max_vp_width() - return the width in bits of VP indices
 455  *
 456  * Return: the width, in bits, of VP indices in fields that combine core & VP
 457  * indices.
 458  */
 459 static inline unsigned int mips_cm_max_vp_width(void)
 460 {
 461         extern int smp_num_siblings;
 462         uint32_t cfg;
 463
 464         if (mips_cm_revision() >= CM_REV_CM3)
 465                 return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
 466
 467         if (mips_cm_present()) {
 468                 /*
 469                  * We presume that all cores in the system will have the same
 470                  * number of VP(E)s, and if that ever changes then this will
 471                  * need revisiting.
 472                  */
 473                 cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
 474                 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
 475         }
 476
 477         if (IS_ENABLED(CONFIG_SMP))
 478                 return smp_num_siblings;
 479
 480         return 1;
 481 }
 482
 483 /**
 484  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
 485  * @cpu: the CPU whose VP ID to calculate
 486  *
 487  * Hardware such as the GIC uses identifiers for VPs which may not match the
 488  * CPU numbers used by Linux. This function calculates the hardware VP
 489  * identifier corresponding to a given CPU.
 490  *
 491  * Return: the VP ID for the CPU.
 492  */
 493 static inline unsigned int mips_cm_vp_id(unsigned int cpu)
 494 {
 495         unsigned int core = cpu_data[cpu].core;
 496         unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
 497
 498         return (core * mips_cm_max_vp_width()) + vp;
 499 }
 500
 501 #ifdef CONFIG_MIPS_CM
 502
 503 /**
 504  * mips_cm_lock_other - lock access to another core
 505  * @core: the other core to be accessed
 506  * @vp: the VP within the other core to be accessed
 507  *
 508  * Call before operating upon a core via the 'other' register region in
 509  * order to prevent the region being moved during access. Must be followed
 510  * by a call to mips_cm_unlock_other.
 511  */
 512 extern void mips_cm_lock_other(unsigned int core, unsigned int vp);
 513
 514 /**
 515  * mips_cm_unlock_other - unlock access to another core
 516  *
 517  * Call after operating upon another core via the 'other' register region.
 518  * Must be called after mips_cm_lock_other.
 519  */
 520 extern void mips_cm_unlock_other(void);
 521
 522 #else /* !CONFIG_MIPS_CM */
 523
 524 static inline void mips_cm_lock_other(unsigned int core, unsigned int vp) { }
 525 static inline void mips_cm_unlock_other(void) { }
 526
 527 #endif /* !CONFIG_MIPS_CM */
 528
 529 #endif /* __MIPS_ASM_MIPS_CM_H__ */