arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_SEGCTL0 $5, 2
  52 #define CP0_SEGCTL1 $5, 3
  53 #define CP0_SEGCTL2 $5, 4
  54 #define CP0_WIRED $6
  55 #define CP0_INFO $7
  56 #define CP0_HWRENA $7, 0
  57 #define CP0_BADVADDR $8
  58 #define CP0_BADINSTR $8, 1
  59 #define CP0_COUNT $9
  60 #define CP0_ENTRYHI $10
  61 #define CP0_GUESTCTL1 $10, 4
  62 #define CP0_GUESTCTL2 $10, 5
  63 #define CP0_GUESTCTL3 $10, 6
  64 #define CP0_COMPARE $11
  65 #define CP0_GUESTCTL0EXT $11, 4
  66 #define CP0_STATUS $12
  67 #define CP0_GUESTCTL0 $12, 6
  68 #define CP0_GTOFFSET $12, 7
  69 #define CP0_CAUSE $13
  70 #define CP0_EPC $14
  71 #define CP0_PRID $15
  72 #define CP0_EBASE $15, 1
  73 #define CP0_CMGCRBASE $15, 3
  74 #define CP0_CONFIG $16
  75 #define CP0_CONFIG3 $16, 3
  76 #define CP0_CONFIG5 $16, 5
  77 #define CP0_LLADDR $17
  78 #define CP0_WATCHLO $18
  79 #define CP0_WATCHHI $19
  80 #define CP0_XCONTEXT $20
  81 #define CP0_FRAMEMASK $21
  82 #define CP0_DIAGNOSTIC $22
  83 #define CP0_DEBUG $23
  84 #define CP0_DEPC $24
  85 #define CP0_PERFORMANCE $25
  86 #define CP0_ECC $26
  87 #define CP0_CACHEERR $27
  88 #define CP0_TAGLO $28
  89 #define CP0_TAGHI $29
  90 #define CP0_ERROREPC $30
  91 #define CP0_DESAVE $31
  92
  93 /*
  94  * R4640/R4650 cp0 register names.  These registers are listed
  95  * here only for completeness; without MMU these CPUs are not useable
  96  * by Linux.  A future ELKS port might take make Linux run on them
  97  * though ...
  98  */
  99 #define CP0_IBASE $0
 100 #define CP0_IBOUND $1
 101 #define CP0_DBASE $2
 102 #define CP0_DBOUND $3
 103 #define CP0_CALG $17
 104 #define CP0_IWATCH $18
 105 #define CP0_DWATCH $19
 106
 107 /*
 108  * Coprocessor 0 Set 1 register names
 109  */
 110 #define CP0_S1_DERRADDR0  $26
 111 #define CP0_S1_DERRADDR1  $27
 112 #define CP0_S1_INTCONTROL $20
 113
 114 /*
 115  * Coprocessor 0 Set 2 register names
 116  */
 117 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 118
 119 /*
 120  * Coprocessor 0 Set 3 register names
 121  */
 122 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 123
 124 /*
 125  *  TX39 Series
 126  */
 127 #define CP0_TX39_CACHE  $7
 128
 129
 130 /* Generic EntryLo bit definitions */
 131 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 132 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 133 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 134 #define ENTRYLO_C_SHIFT         3
 135 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 136
 137 /* R3000 EntryLo bit definitions */
 138 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 139 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 140 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 141 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 142
 143 /* MIPS32/64 EntryLo bit definitions */
 144 #define MIPS_ENTRYLO_PFN_SHIFT  6
 145 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 146 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 147
 148 /*
 149  * Values for PageMask register
 150  */
 151 #ifdef CONFIG_CPU_VR41XX
 152
 153 /* Why doesn't stupidity hurt ... */
 154
 155 #define PM_1K           0x00000000
 156 #define PM_4K           0x00001800
 157 #define PM_16K          0x00007800
 158 #define PM_64K          0x0001f800
 159 #define PM_256K         0x0007f800
 160
 161 #else
 162
 163 #define PM_4K           0x00000000
 164 #define PM_8K           0x00002000
 165 #define PM_16K          0x00006000
 166 #define PM_32K          0x0000e000
 167 #define PM_64K          0x0001e000
 168 #define PM_128K         0x0003e000
 169 #define PM_256K         0x0007e000
 170 #define PM_512K         0x000fe000
 171 #define PM_1M           0x001fe000
 172 #define PM_2M           0x003fe000
 173 #define PM_4M           0x007fe000
 174 #define PM_8M           0x00ffe000
 175 #define PM_16M          0x01ffe000
 176 #define PM_32M          0x03ffe000
 177 #define PM_64M          0x07ffe000
 178 #define PM_256M         0x1fffe000
 179 #define PM_1G           0x7fffe000
 180
 181 #endif
 182
 183 /*
 184  * Default page size for a given kernel configuration
 185  */
 186 #ifdef CONFIG_PAGE_SIZE_4KB
 187 #define PM_DEFAULT_MASK PM_4K
 188 #elif defined(CONFIG_PAGE_SIZE_8KB)
 189 #define PM_DEFAULT_MASK PM_8K
 190 #elif defined(CONFIG_PAGE_SIZE_16KB)
 191 #define PM_DEFAULT_MASK PM_16K
 192 #elif defined(CONFIG_PAGE_SIZE_32KB)
 193 #define PM_DEFAULT_MASK PM_32K
 194 #elif defined(CONFIG_PAGE_SIZE_64KB)
 195 #define PM_DEFAULT_MASK PM_64K
 196 #else
 197 #error Bad page size configuration!
 198 #endif
 199
 200 /*
 201  * Default huge tlb size for a given kernel configuration
 202  */
 203 #ifdef CONFIG_PAGE_SIZE_4KB
 204 #define PM_HUGE_MASK    PM_1M
 205 #elif defined(CONFIG_PAGE_SIZE_8KB)
 206 #define PM_HUGE_MASK    PM_4M
 207 #elif defined(CONFIG_PAGE_SIZE_16KB)
 208 #define PM_HUGE_MASK    PM_16M
 209 #elif defined(CONFIG_PAGE_SIZE_32KB)
 210 #define PM_HUGE_MASK    PM_64M
 211 #elif defined(CONFIG_PAGE_SIZE_64KB)
 212 #define PM_HUGE_MASK    PM_256M
 213 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 214 #error Bad page size configuration for hugetlbfs!
 215 #endif
 216
 217 /*
 218  * Values used for computation of new tlb entries
 219  */
 220 #define PL_4K           12
 221 #define PL_16K          14
 222 #define PL_64K          16
 223 #define PL_256K         18
 224 #define PL_1M           20
 225 #define PL_4M           22
 226 #define PL_16M          24
 227 #define PL_64M          26
 228 #define PL_256M         28
 229
 230 /*
 231  * PageGrain bits
 232  */
 233 #define PG_RIE          (_ULCAST_(1) <<  31)
 234 #define PG_XIE          (_ULCAST_(1) <<  30)
 235 #define PG_ELPA         (_ULCAST_(1) <<  29)
 236 #define PG_ESP          (_ULCAST_(1) <<  28)
 237 #define PG_IEC          (_ULCAST_(1) <<  27)
 238
 239 /* MIPS32/64 EntryHI bit definitions */
 240 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 241 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 242 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 243
 244 /*
 245  * R4x00 interrupt enable / cause bits
 246  */
 247 #define IE_SW0          (_ULCAST_(1) <<  8)
 248 #define IE_SW1          (_ULCAST_(1) <<  9)
 249 #define IE_IRQ0         (_ULCAST_(1) << 10)
 250 #define IE_IRQ1         (_ULCAST_(1) << 11)
 251 #define IE_IRQ2         (_ULCAST_(1) << 12)
 252 #define IE_IRQ3         (_ULCAST_(1) << 13)
 253 #define IE_IRQ4         (_ULCAST_(1) << 14)
 254 #define IE_IRQ5         (_ULCAST_(1) << 15)
 255
 256 /*
 257  * R4x00 interrupt cause bits
 258  */
 259 #define C_SW0           (_ULCAST_(1) <<  8)
 260 #define C_SW1           (_ULCAST_(1) <<  9)
 261 #define C_IRQ0          (_ULCAST_(1) << 10)
 262 #define C_IRQ1          (_ULCAST_(1) << 11)
 263 #define C_IRQ2          (_ULCAST_(1) << 12)
 264 #define C_IRQ3          (_ULCAST_(1) << 13)
 265 #define C_IRQ4          (_ULCAST_(1) << 14)
 266 #define C_IRQ5          (_ULCAST_(1) << 15)
 267
 268 /*
 269  * Bitfields in the R4xx0 cp0 status register
 270  */
 271 #define ST0_IE                  0x00000001
 272 #define ST0_EXL                 0x00000002
 273 #define ST0_ERL                 0x00000004
 274 #define ST0_KSU                 0x00000018
 275 #  define KSU_USER              0x00000010
 276 #  define KSU_SUPERVISOR        0x00000008
 277 #  define KSU_KERNEL            0x00000000
 278 #define ST0_UX                  0x00000020
 279 #define ST0_SX                  0x00000040
 280 #define ST0_KX                  0x00000080
 281 #define ST0_DE                  0x00010000
 282 #define ST0_CE                  0x00020000
 283
 284 /*
 285  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 286  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 287  * processors.
 288  */
 289 #define ST0_CO                  0x08000000
 290
 291 /*
 292  * Bitfields in the R[23]000 cp0 status register.
 293  */
 294 #define ST0_IEC                 0x00000001
 295 #define ST0_KUC                 0x00000002
 296 #define ST0_IEP                 0x00000004
 297 #define ST0_KUP                 0x00000008
 298 #define ST0_IEO                 0x00000010
 299 #define ST0_KUO                 0x00000020
 300 /* bits 6 & 7 are reserved on R[23]000 */
 301 #define ST0_ISC                 0x00010000
 302 #define ST0_SWC                 0x00020000
 303 #define ST0_CM                  0x00080000
 304
 305 /*
 306  * Bits specific to the R4640/R4650
 307  */
 308 #define ST0_UM                  (_ULCAST_(1) <<  4)
 309 #define ST0_IL                  (_ULCAST_(1) << 23)
 310 #define ST0_DL                  (_ULCAST_(1) << 24)
 311
 312 /*
 313  * Enable the MIPS MDMX and DSP ASEs
 314  */
 315 #define ST0_MX                  0x01000000
 316
 317 /*
 318  * Status register bits available in all MIPS CPUs.
 319  */
 320 #define ST0_IM                  0x0000ff00
 321 #define  STATUSB_IP0            8
 322 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 323 #define  STATUSB_IP1            9
 324 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 325 #define  STATUSB_IP2            10
 326 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 327 #define  STATUSB_IP3            11
 328 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 329 #define  STATUSB_IP4            12
 330 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 331 #define  STATUSB_IP5            13
 332 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 333 #define  STATUSB_IP6            14
 334 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 335 #define  STATUSB_IP7            15
 336 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 337 #define  STATUSB_IP8            0
 338 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 339 #define  STATUSB_IP9            1
 340 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 341 #define  STATUSB_IP10           2
 342 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 343 #define  STATUSB_IP11           3
 344 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 345 #define  STATUSB_IP12           4
 346 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 347 #define  STATUSB_IP13           5
 348 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 349 #define  STATUSB_IP14           6
 350 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 351 #define  STATUSB_IP15           7
 352 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 353 #define ST0_CH                  0x00040000
 354 #define ST0_NMI                 0x00080000
 355 #define ST0_SR                  0x00100000
 356 #define ST0_TS                  0x00200000
 357 #define ST0_BEV                 0x00400000
 358 #define ST0_RE                  0x02000000
 359 #define ST0_FR                  0x04000000
 360 #define ST0_CU                  0xf0000000
 361 #define ST0_CU0                 0x10000000
 362 #define ST0_CU1                 0x20000000
 363 #define ST0_CU2                 0x40000000
 364 #define ST0_CU3                 0x80000000
 365 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 366
 367 /*
 368  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 369  */
 370 #define INTCTLB_IPFDC           23
 371 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 372 #define INTCTLB_IPPCI           26
 373 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 374 #define INTCTLB_IPTI            29
 375 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 376
 377 /*
 378  * Bitfields and bit numbers in the coprocessor 0 cause register.
 379  *
 380  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 381  */
 382 #define CAUSEB_EXCCODE          2
 383 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 384 #define CAUSEB_IP               8
 385 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 386 #define  CAUSEB_IP0             8
 387 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 388 #define  CAUSEB_IP1             9
 389 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 390 #define  CAUSEB_IP2             10
 391 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 392 #define  CAUSEB_IP3             11
 393 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 394 #define  CAUSEB_IP4             12
 395 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 396 #define  CAUSEB_IP5             13
 397 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 398 #define  CAUSEB_IP6             14
 399 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 400 #define  CAUSEB_IP7             15
 401 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 402 #define CAUSEB_FDCI             21
 403 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 404 #define CAUSEB_WP               22
 405 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 406 #define CAUSEB_IV               23
 407 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 408 #define CAUSEB_PCI              26
 409 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 410 #define CAUSEB_DC               27
 411 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 412 #define CAUSEB_CE               28
 413 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 414 #define CAUSEB_TI               30
 415 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 416 #define CAUSEB_BD               31
 417 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 418
 419 /*
 420  * Cause.ExcCode trap codes.
 421  */
 422 #define EXCCODE_INT             0       /* Interrupt pending */
 423 #define EXCCODE_MOD             1       /* TLB modified fault */
 424 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 425 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 426 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 427 #define EXCCODE_ADES            5       /* Address error on a store */
 428 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 429 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 430 #define EXCCODE_SYS             8       /* System call */
 431 #define EXCCODE_BP              9       /* Breakpoint */
 432 #define EXCCODE_RI              10      /* Reserved instruction exception */
 433 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 434 #define EXCCODE_OV              12      /* Arithmetic overflow */
 435 #define EXCCODE_TR              13      /* Trap instruction */
 436 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 437 #define EXCCODE_FPE             15      /* Floating point exception */
 438 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 439 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 440 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 441 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 442 #define EXCCODE_WATCH           23      /* Watch address reference */
 443 #define EXCCODE_MCHECK          24      /* Machine check */
 444 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 445 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 446 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 447
 448 /* Implementation specific trap codes used by MIPS cores */
 449 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 450
 451 /*
 452  * Bits in the coprocessor 0 config register.
 453  */
 454 /* Generic bits.  */
 455 #define CONF_CM_CACHABLE_NO_WA          0
 456 #define CONF_CM_CACHABLE_WA             1
 457 #define CONF_CM_UNCACHED                2
 458 #define CONF_CM_CACHABLE_NONCOHERENT    3
 459 #define CONF_CM_CACHABLE_CE             4
 460 #define CONF_CM_CACHABLE_COW            5
 461 #define CONF_CM_CACHABLE_CUW            6
 462 #define CONF_CM_CACHABLE_ACCELERATED    7
 463 #define CONF_CM_CMASK                   7
 464 #define CONF_BE                 (_ULCAST_(1) << 15)
 465
 466 /* Bits common to various processors.  */
 467 #define CONF_CU                 (_ULCAST_(1) <<  3)
 468 #define CONF_DB                 (_ULCAST_(1) <<  4)
 469 #define CONF_IB                 (_ULCAST_(1) <<  5)
 470 #define CONF_DC                 (_ULCAST_(7) <<  6)
 471 #define CONF_IC                 (_ULCAST_(7) <<  9)
 472 #define CONF_EB                 (_ULCAST_(1) << 13)
 473 #define CONF_EM                 (_ULCAST_(1) << 14)
 474 #define CONF_SM                 (_ULCAST_(1) << 16)
 475 #define CONF_SC                 (_ULCAST_(1) << 17)
 476 #define CONF_EW                 (_ULCAST_(3) << 18)
 477 #define CONF_EP                 (_ULCAST_(15)<< 24)
 478 #define CONF_EC                 (_ULCAST_(7) << 28)
 479 #define CONF_CM                 (_ULCAST_(1) << 31)
 480
 481 /* Bits specific to the R4xx0.  */
 482 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 483 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 484 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 485
 486 /* Bits specific to the R5000.  */
 487 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 488 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 489
 490 /* Bits specific to the RM7000.  */
 491 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 492 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 493 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 494 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 495 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 496 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 497
 498 /* Bits specific to the R10000.  */
 499 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 500 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 501 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 502 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 503 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 504 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 505 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 506 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 507 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 508 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 509 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 510
 511 /* Bits specific to the VR41xx.  */
 512 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 513 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 514 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 515 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 516 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 517
 518 /* Bits specific to the R30xx.  */
 519 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 520 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 521 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 522 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 523 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 524 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 525 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 526 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 527 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 528
 529 /* Bits specific to the TX49.  */
 530 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 531 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 532 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 533 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 534
 535 /* Bits specific to the MIPS32/64 PRA.  */
 536 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 537 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 538 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 539 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 540 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 541 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 542
 543 /*
 544  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 545  */
 546 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 547 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 548 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 549 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 550 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 551 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 552 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 553 #define MIPS_CONF1_DA_SHF       7
 554 #define MIPS_CONF1_DA_SZ        3
 555 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 556 #define MIPS_CONF1_DL_SHF       10
 557 #define MIPS_CONF1_DL_SZ        3
 558 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 559 #define MIPS_CONF1_DS_SHF       13
 560 #define MIPS_CONF1_DS_SZ        3
 561 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 562 #define MIPS_CONF1_IA_SHF       16
 563 #define MIPS_CONF1_IA_SZ        3
 564 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 565 #define MIPS_CONF1_IL_SHF       19
 566 #define MIPS_CONF1_IL_SZ        3
 567 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 568 #define MIPS_CONF1_IS_SHF       22
 569 #define MIPS_CONF1_IS_SZ        3
 570 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 571 #define MIPS_CONF1_TLBS_SHIFT   (25)
 572 #define MIPS_CONF1_TLBS_SIZE    (6)
 573 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 574
 575 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 576 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 577 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 578 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 579 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 580 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 581 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 582 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 583
 584 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 585 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 586 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 587 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 588 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 589 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 590 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 591 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 592 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 593 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 594 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 595 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 596 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 597 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 598 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 599 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 600 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 601 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 602 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 603 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 604 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 605 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 606 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 607 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 608 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 609 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 610 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 611
 612 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 613 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 614 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 615 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 616 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 617 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 618 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 619 /* bits 10:8 in FTLB-only configurations */
 620 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 621 /* bits 12:8 in VTLB-FTLB only configurations */
 622 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 623 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 624 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 625 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 626 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 627 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 628 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 629 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 630 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 631 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 632 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 633 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 634
 635 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 636 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 637 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 638 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 639 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 640 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 641 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 642 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 643 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 644 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 645 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 646 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 647
 648 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 649 /* proAptiv FTLB on/off bit */
 650 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 651 /* Loongson-3 FTLB on/off bit */
 652 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 653 /* FTLB probability bits */
 654 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 655
 656 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 657
 658 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 659
 660 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 661 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 662 /* FTLB probability bits for R6 */
 663 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 664
 665 /* WatchLo* register definitions */
 666 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 667
 668 /* WatchHi* register definitions */
 669 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 670 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 671 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 672 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 673 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 674 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 675 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 676 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 677 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 678 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 679 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 680 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 681 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 682
 683 /* MAAR bit definitions */
 684 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 685 #define MIPS_MAAR_ADDR_SHIFT    12
 686 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 687 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 688
 689 /* EBase bit definitions */
 690 #define MIPS_EBASE_CPUNUM_SHIFT 0
 691 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 692 #define MIPS_EBASE_WG_SHIFT     11
 693 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 694 #define MIPS_EBASE_BASE_SHIFT   12
 695 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 696
 697 /* CMGCRBase bit definitions */
 698 #define MIPS_CMGCRB_BASE        11
 699 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 700
 701 /*
 702  * Bits in the MIPS32 Memory Segmentation registers.
 703  */
 704 #define MIPS_SEGCFG_PA_SHIFT    9
 705 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 706 #define MIPS_SEGCFG_AM_SHIFT    4
 707 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 708 #define MIPS_SEGCFG_EU_SHIFT    3
 709 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 710 #define MIPS_SEGCFG_C_SHIFT     0
 711 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 712
 713 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 714 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 715 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 716 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 717 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 718 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 719 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 720
 721 #define MIPS_PWFIELD_GDI_SHIFT  24
 722 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 723 #define MIPS_PWFIELD_UDI_SHIFT  18
 724 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 725 #define MIPS_PWFIELD_MDI_SHIFT  12
 726 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 727 #define MIPS_PWFIELD_PTI_SHIFT  6
 728 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 729 #define MIPS_PWFIELD_PTEI_SHIFT 0
 730 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 731
 732 #define MIPS_PWSIZE_GDW_SHIFT   24
 733 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 734 #define MIPS_PWSIZE_UDW_SHIFT   18
 735 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 736 #define MIPS_PWSIZE_MDW_SHIFT   12
 737 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 738 #define MIPS_PWSIZE_PTW_SHIFT   6
 739 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 740 #define MIPS_PWSIZE_PTEW_SHIFT  0
 741 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 742
 743 #define MIPS_PWCTL_PWEN_SHIFT   31
 744 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 745 #define MIPS_PWCTL_DPH_SHIFT    7
 746 #define MIPS_PWCTL_DPH_MASK     0x00000080
 747 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 748 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 749 #define MIPS_PWCTL_PSN_SHIFT    0
 750 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 751
 752 /* GuestCtl0 fields */
 753 #define MIPS_GCTL0_GM_SHIFT     31
 754 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 755 #define MIPS_GCTL0_RI_SHIFT     30
 756 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 757 #define MIPS_GCTL0_MC_SHIFT     29
 758 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 759 #define MIPS_GCTL0_CP0_SHIFT    28
 760 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 761 #define MIPS_GCTL0_AT_SHIFT     26
 762 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 763 #define MIPS_GCTL0_GT_SHIFT     25
 764 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 765 #define MIPS_GCTL0_CG_SHIFT     24
 766 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 767 #define MIPS_GCTL0_CF_SHIFT     23
 768 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 769 #define MIPS_GCTL0_G1_SHIFT     22
 770 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 771 #define MIPS_GCTL0_G0E_SHIFT    19
 772 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 773 #define MIPS_GCTL0_PT_SHIFT     18
 774 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 775 #define MIPS_GCTL0_RAD_SHIFT    9
 776 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 777 #define MIPS_GCTL0_DRG_SHIFT    8
 778 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 779 #define MIPS_GCTL0_G2_SHIFT     7
 780 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 781 #define MIPS_GCTL0_GEXC_SHIFT   2
 782 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 783 #define MIPS_GCTL0_SFC2_SHIFT   1
 784 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 785 #define MIPS_GCTL0_SFC1_SHIFT   0
 786 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 787
 788 /* GuestCtl0.AT Guest address translation control */
 789 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 790 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 791
 792 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 793 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 794 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 795 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 796 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 797 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 798 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 799 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 800
 801 /* GuestCtl0Ext fields */
 802 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 803 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 804 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 805 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 806 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 807 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 808 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 809 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 810 #define MIPS_GCTL0EXT_OG_SHIFT  2
 811 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 812 #define MIPS_GCTL0EXT_BG_SHIFT  1
 813 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 814 #define MIPS_GCTL0EXT_MG_SHIFT  0
 815 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 816
 817 /* GuestCtl0Ext.RPW Root page walk configuration */
 818 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 819 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 820 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 821
 822 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 823 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 824 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 825
 826 /* GuestCtl1 fields */
 827 #define MIPS_GCTL1_ID_SHIFT     0
 828 #define MIPS_GCTL1_ID_WIDTH     8
 829 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 830 #define MIPS_GCTL1_RID_SHIFT    16
 831 #define MIPS_GCTL1_RID_WIDTH    8
 832 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 833 #define MIPS_GCTL1_EID_SHIFT    24
 834 #define MIPS_GCTL1_EID_WIDTH    8
 835 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 836
 837 /* GuestID reserved for root context */
 838 #define MIPS_GCTL1_ROOT_GUESTID 0
 839
 840 /* CDMMBase register bit definitions */
 841 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 842 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 843 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 844 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 845 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 846 #define MIPS_CDMMBASE_ADDR_START 15
 847
 848 /*
 849  * Bitfields in the TX39 family CP0 Configuration Register 3
 850  */
 851 #define TX39_CONF_ICS_SHIFT     19
 852 #define TX39_CONF_ICS_MASK      0x00380000
 853 #define TX39_CONF_ICS_1KB       0x00000000
 854 #define TX39_CONF_ICS_2KB       0x00080000
 855 #define TX39_CONF_ICS_4KB       0x00100000
 856 #define TX39_CONF_ICS_8KB       0x00180000
 857 #define TX39_CONF_ICS_16KB      0x00200000
 858
 859 #define TX39_CONF_DCS_SHIFT     16
 860 #define TX39_CONF_DCS_MASK      0x00070000
 861 #define TX39_CONF_DCS_1KB       0x00000000
 862 #define TX39_CONF_DCS_2KB       0x00010000
 863 #define TX39_CONF_DCS_4KB       0x00020000
 864 #define TX39_CONF_DCS_8KB       0x00030000
 865 #define TX39_CONF_DCS_16KB      0x00040000
 866
 867 #define TX39_CONF_CWFON         0x00004000
 868 #define TX39_CONF_WBON          0x00002000
 869 #define TX39_CONF_RF_SHIFT      10
 870 #define TX39_CONF_RF_MASK       0x00000c00
 871 #define TX39_CONF_DOZE          0x00000200
 872 #define TX39_CONF_HALT          0x00000100
 873 #define TX39_CONF_LOCK          0x00000080
 874 #define TX39_CONF_ICE           0x00000020
 875 #define TX39_CONF_DCE           0x00000010
 876 #define TX39_CONF_IRSIZE_SHIFT  2
 877 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 878 #define TX39_CONF_DRSIZE_SHIFT  0
 879 #define TX39_CONF_DRSIZE_MASK   0x00000003
 880
 881 /*
 882  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 883  */
 884 /* Disable Branch Target Address Cache */
 885 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 886 /* Enable Branch Prediction Global History */
 887 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 888 /* Disable Branch Return Cache */
 889 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 890
 891 /* Flush ITLB */
 892 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 893 /* Flush DTLB */
 894 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 895 /* Flush VTLB */
 896 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 897 /* Flush FTLB */
 898 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 899
 900 /*
 901  * Coprocessor 1 (FPU) register names
 902  */
 903 #define CP1_REVISION    $0
 904 #define CP1_UFR         $1
 905 #define CP1_UNFR        $4
 906 #define CP1_FCCR        $25
 907 #define CP1_FEXR        $26
 908 #define CP1_FENR        $28
 909 #define CP1_STATUS      $31
 910
 911
 912 /*
 913  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 914  */
 915 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 916 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 917 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 918 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 919 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 920 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 921 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 922 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 923 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 924 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 925
 926 /*
 927  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 928  */
 929 #define MIPS_FCCR_CONDX_S       0
 930 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 931 #define MIPS_FCCR_COND0_S       0
 932 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 933 #define MIPS_FCCR_COND1_S       1
 934 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 935 #define MIPS_FCCR_COND2_S       2
 936 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 937 #define MIPS_FCCR_COND3_S       3
 938 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 939 #define MIPS_FCCR_COND4_S       4
 940 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 941 #define MIPS_FCCR_COND5_S       5
 942 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 943 #define MIPS_FCCR_COND6_S       6
 944 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 945 #define MIPS_FCCR_COND7_S       7
 946 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 947
 948 /*
 949  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 950  */
 951 #define MIPS_FENR_FS_S          2
 952 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 953
 954 /*
 955  * FPU Status Register Values
 956  */
 957 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 958 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 959
 960 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 961 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 962
 963 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 964 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 965 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 966 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 967 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 968 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 969 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 970 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 971 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 972 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 973 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 974 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 975 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 976 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 977 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 978 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 979
 980 /*
 981  * Bits 22:20 of the FPU Status Register will be read as 0,
 982  * and should be written as zero.
 983  */
 984 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 985
 986 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 987 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 988
 989 /*
 990  * X the exception cause indicator
 991  * E the exception enable
 992  * S the sticky/flag bit
 993 */
 994 #define FPU_CSR_ALL_X   0x0003f000
 995 #define FPU_CSR_UNI_X   0x00020000
 996 #define FPU_CSR_INV_X   0x00010000
 997 #define FPU_CSR_DIV_X   0x00008000
 998 #define FPU_CSR_OVF_X   0x00004000
 999 #define FPU_CSR_UDF_X   0x00002000
1000 #define FPU_CSR_INE_X   0x00001000
1001
1002 #define FPU_CSR_ALL_E   0x00000f80
1003 #define FPU_CSR_INV_E   0x00000800
1004 #define FPU_CSR_DIV_E   0x00000400
1005 #define FPU_CSR_OVF_E   0x00000200
1006 #define FPU_CSR_UDF_E   0x00000100
1007 #define FPU_CSR_INE_E   0x00000080
1008
1009 #define FPU_CSR_ALL_S   0x0000007c
1010 #define FPU_CSR_INV_S   0x00000040
1011 #define FPU_CSR_DIV_S   0x00000020
1012 #define FPU_CSR_OVF_S   0x00000010
1013 #define FPU_CSR_UDF_S   0x00000008
1014 #define FPU_CSR_INE_S   0x00000004
1015
1016 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1017 #define FPU_CSR_RM      0x00000003
1018 #define FPU_CSR_RN      0x0     /* nearest */
1019 #define FPU_CSR_RZ      0x1     /* towards zero */
1020 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1021 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1022
1023
1024 #ifndef __ASSEMBLY__
1025
1026 /*
1027  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1028  */
1029 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1030     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1031 #define get_isa16_mode(x)               ((x) & 0x1)
1032 #define msk_isa16_mode(x)               ((x) & ~0x1)
1033 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1034 #else
1035 #define get_isa16_mode(x)               0
1036 #define msk_isa16_mode(x)               (x)
1037 #define set_isa16_mode(x)               do { } while(0)
1038 #endif
1039
1040 /*
1041  * microMIPS instructions can be 16-bit or 32-bit in length. This
1042  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1043  */
1044 static inline int mm_insn_16bit(u16 insn)
1045 {
1046         u16 opcode = (insn >> 10) & 0x7;
1047
1048         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1049 }
1050
1051 /*
1052  * TLB Invalidate Flush
1053  */
1054 static inline void tlbinvf(void)
1055 {
1056         __asm__ __volatile__(
1057                 ".set push\n\t"
1058                 ".set noreorder\n\t"
1059                 ".word 0x42000004\n\t" /* tlbinvf */
1060                 ".set pop");
1061 }
1062
1063
1064 /*
1065  * Functions to access the R10000 performance counters.  These are basically
1066  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1067  * performance counter number encoded into bits 1 ... 5 of the instruction.
1068  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1069  * disassembler these will look like an access to sel 0 or 1.
1070  */
1071 #define read_r10k_perf_cntr(counter)                            \
1072 ({                                                              \
1073         unsigned int __res;                                     \
1074         __asm__ __volatile__(                                   \
1075         "mfpc\t%0, %1"                                          \
1076         : "=r" (__res)                                          \
1077         : "i" (counter));                                       \
1078                                                                 \
1079         __res;                                                  \
1080 })
1081
1082 #define write_r10k_perf_cntr(counter,val)                       \
1083 do {                                                            \
1084         __asm__ __volatile__(                                   \
1085         "mtpc\t%0, %1"                                          \
1086         :                                                       \
1087         : "r" (val), "i" (counter));                            \
1088 } while (0)
1089
1090 #define read_r10k_perf_event(counter)                           \
1091 ({                                                              \
1092         unsigned int __res;                                     \
1093         __asm__ __volatile__(                                   \
1094         "mfps\t%0, %1"                                          \
1095         : "=r" (__res)                                          \
1096         : "i" (counter));                                       \
1097                                                                 \
1098         __res;                                                  \
1099 })
1100
1101 #define write_r10k_perf_cntl(counter,val)                       \
1102 do {                                                            \
1103         __asm__ __volatile__(                                   \
1104         "mtps\t%0, %1"                                          \
1105         :                                                       \
1106         : "r" (val), "i" (counter));                            \
1107 } while (0)
1108
1109
1110 /*
1111  * Macros to access the system control coprocessor
1112  */
1113
1114 #define __read_32bit_c0_register(source, sel)                           \
1115 ({ unsigned int __res;                                                  \
1116         if (sel == 0)                                                   \
1117                 __asm__ __volatile__(                                   \
1118                         "mfc0\t%0, " #source "\n\t"                     \
1119                         : "=r" (__res));                                \
1120         else                                                            \
1121                 __asm__ __volatile__(                                   \
1122                         ".set\tmips32\n\t"                              \
1123                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1124                         ".set\tmips0\n\t"                               \
1125                         : "=r" (__res));                                \
1126         __res;                                                          \
1127 })
1128
1129 #define __read_64bit_c0_register(source, sel)                           \
1130 ({ unsigned long long __res;                                            \
1131         if (sizeof(unsigned long) == 4)                                 \
1132                 __res = __read_64bit_c0_split(source, sel);             \
1133         else if (sel == 0)                                              \
1134                 __asm__ __volatile__(                                   \
1135                         ".set\tmips3\n\t"                               \
1136                         "dmfc0\t%0, " #source "\n\t"                    \
1137                         ".set\tmips0"                                   \
1138                         : "=r" (__res));                                \
1139         else                                                            \
1140                 __asm__ __volatile__(                                   \
1141                         ".set\tmips64\n\t"                              \
1142                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1143                         ".set\tmips0"                                   \
1144                         : "=r" (__res));                                \
1145         __res;                                                          \
1146 })
1147
1148 #define __write_32bit_c0_register(register, sel, value)                 \
1149 do {                                                                    \
1150         if (sel == 0)                                                   \
1151                 __asm__ __volatile__(                                   \
1152                         "mtc0\t%z0, " #register "\n\t"                  \
1153                         : : "Jr" ((unsigned int)(value)));              \
1154         else                                                            \
1155                 __asm__ __volatile__(                                   \
1156                         ".set\tmips32\n\t"                              \
1157                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1158                         ".set\tmips0"                                   \
1159                         : : "Jr" ((unsigned int)(value)));              \
1160 } while (0)
1161
1162 #define __write_64bit_c0_register(register, sel, value)                 \
1163 do {                                                                    \
1164         if (sizeof(unsigned long) == 4)                                 \
1165                 __write_64bit_c0_split(register, sel, value);           \
1166         else if (sel == 0)                                              \
1167                 __asm__ __volatile__(                                   \
1168                         ".set\tmips3\n\t"                               \
1169                         "dmtc0\t%z0, " #register "\n\t"                 \
1170                         ".set\tmips0"                                   \
1171                         : : "Jr" (value));                              \
1172         else                                                            \
1173                 __asm__ __volatile__(                                   \
1174                         ".set\tmips64\n\t"                              \
1175                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1176                         ".set\tmips0"                                   \
1177                         : : "Jr" (value));                              \
1178 } while (0)
1179
1180 #define __read_ulong_c0_register(reg, sel)                              \
1181         ((sizeof(unsigned long) == 4) ?                                 \
1182         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1183         (unsigned long) __read_64bit_c0_register(reg, sel))
1184
1185 #define __write_ulong_c0_register(reg, sel, val)                        \
1186 do {                                                                    \
1187         if (sizeof(unsigned long) == 4)                                 \
1188                 __write_32bit_c0_register(reg, sel, val);               \
1189         else                                                            \
1190                 __write_64bit_c0_register(reg, sel, val);               \
1191 } while (0)
1192
1193 /*
1194  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1195  */
1196 #define __read_32bit_c0_ctrl_register(source)                           \
1197 ({ unsigned int __res;                                                  \
1198         __asm__ __volatile__(                                           \
1199                 "cfc0\t%0, " #source "\n\t"                             \
1200                 : "=r" (__res));                                        \
1201         __res;                                                          \
1202 })
1203
1204 #define __write_32bit_c0_ctrl_register(register, value)                 \
1205 do {                                                                    \
1206         __asm__ __volatile__(                                           \
1207                 "ctc0\t%z0, " #register "\n\t"                          \
1208                 : : "Jr" ((unsigned int)(value)));                      \
1209 } while (0)
1210
1211 /*
1212  * These versions are only needed for systems with more than 38 bits of
1213  * physical address space running the 32-bit kernel.  That's none atm :-)
1214  */
1215 #define __read_64bit_c0_split(source, sel)                              \
1216 ({                                                                      \
1217         unsigned long long __val;                                       \
1218         unsigned long __flags;                                          \
1219                                                                         \
1220         local_irq_save(__flags);                                        \
1221         if (sel == 0)                                                   \
1222                 __asm__ __volatile__(                                   \
1223                         ".set\tmips64\n\t"                              \
1224                         "dmfc0\t%M0, " #source "\n\t"                   \
1225                         "dsll\t%L0, %M0, 32\n\t"                        \
1226                         "dsra\t%M0, %M0, 32\n\t"                        \
1227                         "dsra\t%L0, %L0, 32\n\t"                        \
1228                         ".set\tmips0"                                   \
1229                         : "=r" (__val));                                \
1230         else                                                            \
1231                 __asm__ __volatile__(                                   \
1232                         ".set\tmips64\n\t"                              \
1233                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1234                         "dsll\t%L0, %M0, 32\n\t"                        \
1235                         "dsra\t%M0, %M0, 32\n\t"                        \
1236                         "dsra\t%L0, %L0, 32\n\t"                        \
1237                         ".set\tmips0"                                   \
1238                         : "=r" (__val));                                \
1239         local_irq_restore(__flags);                                     \
1240                                                                         \
1241         __val;                                                          \
1242 })
1243
1244 #define __write_64bit_c0_split(source, sel, val)                        \
1245 do {                                                                    \
1246         unsigned long __flags;                                          \
1247                                                                         \
1248         local_irq_save(__flags);                                        \
1249         if (sel == 0)                                                   \
1250                 __asm__ __volatile__(                                   \
1251                         ".set\tmips64\n\t"                              \
1252                         "dsll\t%L0, %L0, 32\n\t"                        \
1253                         "dsrl\t%L0, %L0, 32\n\t"                        \
1254                         "dsll\t%M0, %M0, 32\n\t"                        \
1255                         "or\t%L0, %L0, %M0\n\t"                         \
1256                         "dmtc0\t%L0, " #source "\n\t"                   \
1257                         ".set\tmips0"                                   \
1258                         : : "r" (val));                                 \
1259         else                                                            \
1260                 __asm__ __volatile__(                                   \
1261                         ".set\tmips64\n\t"                              \
1262                         "dsll\t%L0, %L0, 32\n\t"                        \
1263                         "dsrl\t%L0, %L0, 32\n\t"                        \
1264                         "dsll\t%M0, %M0, 32\n\t"                        \
1265                         "or\t%L0, %L0, %M0\n\t"                         \
1266                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1267                         ".set\tmips0"                                   \
1268                         : : "r" (val));                                 \
1269         local_irq_restore(__flags);                                     \
1270 } while (0)
1271
1272 #define __readx_32bit_c0_register(source)                               \
1273 ({                                                                      \
1274         unsigned int __res;                                             \
1275                                                                         \
1276         __asm__ __volatile__(                                           \
1277         "       .set    push                                    \n"     \
1278         "       .set    noat                                    \n"     \
1279         "       .set    mips32r2                                \n"     \
1280         "       .insn                                           \n"     \
1281         "       # mfhc0 $1, %1                                  \n"     \
1282         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1283         "       move    %0, $1                                  \n"     \
1284         "       .set    pop                                     \n"     \
1285         : "=r" (__res)                                                  \
1286         : "i" (source));                                                \
1287         __res;                                                          \
1288 })
1289
1290 #define __writex_32bit_c0_register(register, value)                     \
1291 do {                                                                    \
1292         __asm__ __volatile__(                                           \
1293         "       .set    push                                    \n"     \
1294         "       .set    noat                                    \n"     \
1295         "       .set    mips32r2                                \n"     \
1296         "       move    $1, %0                                  \n"     \
1297         "       # mthc0 $1, %1                                  \n"     \
1298         "       .insn                                           \n"     \
1299         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1300         "       .set    pop                                     \n"     \
1301         :                                                               \
1302         : "r" (value), "i" (register));                                 \
1303 } while (0)
1304
1305 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1306 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1307
1308 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1309 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1310
1311 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1312 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1313
1314 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1315 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1316
1317 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1318 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1319
1320 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1321 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1322
1323 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1324 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1325
1326 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1327 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1328
1329 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1330 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1331
1332 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1333 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1334
1335 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1336 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1337
1338 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1339 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1340
1341 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1342 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1343
1344 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1345 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1346
1347 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1348
1349 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1350 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1351
1352 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1353 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1354
1355 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1356 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1357
1358 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1359 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1360
1361 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1362 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1363
1364 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1365 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1366
1367 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1368 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1369
1370 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1371 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1372
1373 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1374 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1375
1376 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1377 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1378
1379 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1380 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1381
1382 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1383 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1384
1385 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1386 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1387
1388 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1389 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1390
1391 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1392
1393 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1394
1395 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1396 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1397
1398 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1399 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1400
1401 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1402 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1403
1404 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1405 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1406
1407 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1408
1409 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1410
1411 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1412 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1413 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1414 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1415 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1416 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1417 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1418 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1419 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1420 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1421 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1422 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1423 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1424 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1425 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1426 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1427
1428 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1429 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1430 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1431 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1432 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1433 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1434
1435 /*
1436  * The WatchLo register.  There may be up to 8 of them.
1437  */
1438 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1439 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1440 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1441 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1442 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1443 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1444 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1445 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1446 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1447 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1448 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1449 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1450 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1451 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1452 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1453 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1454
1455 /*
1456  * The WatchHi register.  There may be up to 8 of them.
1457  */
1458 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1459 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1460 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1461 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1462 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1463 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1464 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1465 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1466
1467 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1468 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1469 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1470 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1471 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1472 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1473 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1474 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1475
1476 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1477 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1478
1479 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1480 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1481
1482 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1483 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1484
1485 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1486 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1487
1488 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1489 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1490 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1491
1492 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1493 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1494
1495 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1496 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1497
1498 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1499 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1500
1501 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1502 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1503
1504 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1505 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1506
1507 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1508 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1509
1510 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1511 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1512
1513 /*
1514  * MIPS32 / MIPS64 performance counters
1515  */
1516 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1517 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1518 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1519 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1520 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1521 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1522 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1523 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1524 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1525 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1526 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1527 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1528 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1529 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1530 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1531 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1532 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1533 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1534 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1535 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1536 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1537 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1538 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1539 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1540
1541 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1542 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1543
1544 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1545 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1546
1547 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1548
1549 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1550 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1551
1552 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1553 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1554
1555 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1556 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1557
1558 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1559 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1560
1561 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1562 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1563
1564 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1565 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1566
1567 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1568 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1569
1570 /* MIPSR2 */
1571 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1572 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1573
1574 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1575 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1576
1577 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1578 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1579
1580 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1581 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1582
1583 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1584 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1585
1586 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1587 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1588
1589 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1590 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1591
1592 /* MIPSR3 */
1593 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1594 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1595
1596 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1597 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1598
1599 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1600 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1601
1602 /* Hardware Page Table Walker */
1603 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1604 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1605
1606 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1607 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1608
1609 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1610 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1611
1612 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1613 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1614
1615 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1616 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1617
1618 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1619 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1620
1621 /* Cavium OCTEON (cnMIPS) */
1622 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1623 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1624
1625 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1626 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1627
1628 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1629 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1630 /*
1631  * The cacheerr registers are not standardized.  On OCTEON, they are
1632  * 64 bits wide.
1633  */
1634 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1635 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1636
1637 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1638 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1639
1640 /* BMIPS3300 */
1641 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1642 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1643
1644 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1645 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1646
1647 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1648 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1649
1650 /* BMIPS43xx */
1651 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1652 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1653
1654 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1655 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1656
1657 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1658 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1659
1660 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1661 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1662
1663 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1664 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1665
1666 /* BMIPS5000 */
1667 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1668 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1669
1670 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1671 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1672
1673 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1674 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1675
1676 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1677 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1678
1679 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1680 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1681
1682 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1683 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1684
1685 /*
1686  * Macros to access the guest system control coprocessor
1687  */
1688
1689 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1690
1691 #define __read_32bit_gc0_register(source, sel)                          \
1692 ({ int __res;                                                           \
1693         __asm__ __volatile__(                                           \
1694                 ".set\tpush\n\t"                                        \
1695                 ".set\tmips32r2\n\t"                                    \
1696                 ".set\tvirt\n\t"                                        \
1697                 "mfgc0\t%0, $%1, %2\n\t"                                \
1698                 ".set\tpop"                                             \
1699                 : "=r" (__res)                                          \
1700                 : "i" (source), "i" (sel));                             \
1701         __res;                                                          \
1702 })
1703
1704 #define __read_64bit_gc0_register(source, sel)                          \
1705 ({ unsigned long long __res;                                            \
1706         __asm__ __volatile__(                                           \
1707                 ".set\tpush\n\t"                                        \
1708                 ".set\tmips64r2\n\t"                                    \
1709                 ".set\tvirt\n\t"                                        \
1710                 "dmfgc0\t%0, $%1, %2\n\t"                       \
1711                 ".set\tpop"                                             \
1712                 : "=r" (__res)                                          \
1713                 : "i" (source), "i" (sel));                             \
1714         __res;                                                          \
1715 })
1716
1717 #define __write_32bit_gc0_register(register, sel, value)                \
1718 do {                                                                    \
1719         __asm__ __volatile__(                                           \
1720                 ".set\tpush\n\t"                                        \
1721                 ".set\tmips32r2\n\t"                                    \
1722                 ".set\tvirt\n\t"                                        \
1723                 "mtgc0\t%z0, $%1, %2\n\t"                               \
1724                 ".set\tpop"                                             \
1725                 : : "Jr" ((unsigned int)(value)),                       \
1726                     "i" (register), "i" (sel));                         \
1727 } while (0)
1728
1729 #define __write_64bit_gc0_register(register, sel, value)                \
1730 do {                                                                    \
1731         __asm__ __volatile__(                                           \
1732                 ".set\tpush\n\t"                                        \
1733                 ".set\tmips64r2\n\t"                                    \
1734                 ".set\tvirt\n\t"                                        \
1735                 "dmtgc0\t%z0, $%1, %2\n\t"                              \
1736                 ".set\tpop"                                             \
1737                 : : "Jr" (value),                                       \
1738                     "i" (register), "i" (sel));                         \
1739 } while (0)
1740
1741 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
1742
1743 #define __read_32bit_gc0_register(source, sel)                          \
1744 ({ int __res;                                                           \
1745         __asm__ __volatile__(                                           \
1746                 ".set\tpush\n\t"                                        \
1747                 ".set\tnoat\n\t"                                        \
1748                 "# mfgc0\t$1, $%1, %2\n\t"                              \
1749                 ".word\t(0x40610000 | %1 << 11 | %2)\n\t"               \
1750                 "move\t%0, $1\n\t"                                      \
1751                 ".set\tpop"                                             \
1752                 : "=r" (__res)                                          \
1753                 : "i" (source), "i" (sel));                             \
1754         __res;                                                          \
1755 })
1756
1757 #define __read_64bit_gc0_register(source, sel)                          \
1758 ({ unsigned long long __res;                                            \
1759         __asm__ __volatile__(                                           \
1760                 ".set\tpush\n\t"                                        \
1761                 ".set\tnoat\n\t"                                        \
1762                 "# dmfgc0\t$1, $%1, %2\n\t"                             \
1763                 ".word\t(0x40610100 | %1 << 11 | %2)\n\t"               \
1764                 "move\t%0, $1\n\t"                                      \
1765                 ".set\tpop"                                             \
1766                 : "=r" (__res)                                          \
1767                 : "i" (source), "i" (sel));                             \
1768         __res;                                                          \
1769 })
1770
1771 #define __write_32bit_gc0_register(register, sel, value)                \
1772 do {                                                                    \
1773         __asm__ __volatile__(                                           \
1774                 ".set\tpush\n\t"                                        \
1775                 ".set\tnoat\n\t"                                        \
1776                 "move\t$1, %0\n\t"                                      \
1777                 "# mtgc0\t$1, $%1, %2\n\t"                              \
1778                 ".word\t(0x40610200 | %1 << 11 | %2)\n\t"               \
1779                 ".set\tpop"                                             \
1780                 : : "Jr" ((unsigned int)(value)),                       \
1781                     "i" (register), "i" (sel));                         \
1782 } while (0)
1783
1784 #define __write_64bit_gc0_register(register, sel, value)                \
1785 do {                                                                    \
1786         __asm__ __volatile__(                                           \
1787                 ".set\tpush\n\t"                                        \
1788                 ".set\tnoat\n\t"                                        \
1789                 "move\t$1, %0\n\t"                                      \
1790                 "# dmtgc0\t$1, $%1, %2\n\t"                             \
1791                 ".word\t(0x40610300 | %1 << 11 | %2)\n\t"               \
1792                 ".set\tpop"                                             \
1793                 : : "Jr" (value),                                       \
1794                     "i" (register), "i" (sel));                         \
1795 } while (0)
1796
1797 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
1798
1799 #define __read_ulong_gc0_register(reg, sel)                             \
1800         ((sizeof(unsigned long) == 4) ?                                 \
1801         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
1802         (unsigned long) __read_64bit_gc0_register(reg, sel))
1803
1804 #define __write_ulong_gc0_register(reg, sel, val)                       \
1805 do {                                                                    \
1806         if (sizeof(unsigned long) == 4)                                 \
1807                 __write_32bit_gc0_register(reg, sel, val);              \
1808         else                                                            \
1809                 __write_64bit_gc0_register(reg, sel, val);              \
1810 } while (0)
1811
1812 #define read_gc0_index()                __read_32bit_gc0_register(0, 0)
1813 #define write_gc0_index(val)            __write_32bit_gc0_register(0, 0, val)
1814
1815 #define read_gc0_entrylo0()             __read_ulong_gc0_register(2, 0)
1816 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register(2, 0, val)
1817
1818 #define read_gc0_entrylo1()             __read_ulong_gc0_register(3, 0)
1819 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register(3, 0, val)
1820
1821 #define read_gc0_context()              __read_ulong_gc0_register(4, 0)
1822 #define write_gc0_context(val)          __write_ulong_gc0_register(4, 0, val)
1823
1824 #define read_gc0_contextconfig()        __read_32bit_gc0_register(4, 1)
1825 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register(4, 1, val)
1826
1827 #define read_gc0_userlocal()            __read_ulong_gc0_register(4, 2)
1828 #define write_gc0_userlocal(val)        __write_ulong_gc0_register(4, 2, val)
1829
1830 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register(4, 3)
1831 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register(4, 3, val)
1832
1833 #define read_gc0_pagemask()             __read_32bit_gc0_register(5, 0)
1834 #define write_gc0_pagemask(val)         __write_32bit_gc0_register(5, 0, val)
1835
1836 #define read_gc0_pagegrain()            __read_32bit_gc0_register(5, 1)
1837 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register(5, 1, val)
1838
1839 #define read_gc0_segctl0()              __read_ulong_gc0_register(5, 2)
1840 #define write_gc0_segctl0(val)          __write_ulong_gc0_register(5, 2, val)
1841
1842 #define read_gc0_segctl1()              __read_ulong_gc0_register(5, 3)
1843 #define write_gc0_segctl1(val)          __write_ulong_gc0_register(5, 3, val)
1844
1845 #define read_gc0_segctl2()              __read_ulong_gc0_register(5, 4)
1846 #define write_gc0_segctl2(val)          __write_ulong_gc0_register(5, 4, val)
1847
1848 #define read_gc0_pwbase()               __read_ulong_gc0_register(5, 5)
1849 #define write_gc0_pwbase(val)           __write_ulong_gc0_register(5, 5, val)
1850
1851 #define read_gc0_pwfield()              __read_ulong_gc0_register(5, 6)
1852 #define write_gc0_pwfield(val)          __write_ulong_gc0_register(5, 6, val)
1853
1854 #define read_gc0_pwsize()               __read_ulong_gc0_register(5, 7)
1855 #define write_gc0_pwsize(val)           __write_ulong_gc0_register(5, 7, val)
1856
1857 #define read_gc0_wired()                __read_32bit_gc0_register(6, 0)
1858 #define write_gc0_wired(val)            __write_32bit_gc0_register(6, 0, val)
1859
1860 #define read_gc0_pwctl()                __read_32bit_gc0_register(6, 6)
1861 #define write_gc0_pwctl(val)            __write_32bit_gc0_register(6, 6, val)
1862
1863 #define read_gc0_hwrena()               __read_32bit_gc0_register(7, 0)
1864 #define write_gc0_hwrena(val)           __write_32bit_gc0_register(7, 0, val)
1865
1866 #define read_gc0_badvaddr()             __read_ulong_gc0_register(8, 0)
1867 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register(8, 0, val)
1868
1869 #define read_gc0_badinstr()             __read_32bit_gc0_register(8, 1)
1870 #define write_gc0_badinstr(val)         __write_32bit_gc0_register(8, 1, val)
1871
1872 #define read_gc0_badinstrp()            __read_32bit_gc0_register(8, 2)
1873 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register(8, 2, val)
1874
1875 #define read_gc0_count()                __read_32bit_gc0_register(9, 0)
1876
1877 #define read_gc0_entryhi()              __read_ulong_gc0_register(10, 0)
1878 #define write_gc0_entryhi(val)          __write_ulong_gc0_register(10, 0, val)
1879
1880 #define read_gc0_compare()              __read_32bit_gc0_register(11, 0)
1881 #define write_gc0_compare(val)          __write_32bit_gc0_register(11, 0, val)
1882
1883 #define read_gc0_status()               __read_32bit_gc0_register(12, 0)
1884 #define write_gc0_status(val)           __write_32bit_gc0_register(12, 0, val)
1885
1886 #define read_gc0_intctl()               __read_32bit_gc0_register(12, 1)
1887 #define write_gc0_intctl(val)           __write_32bit_gc0_register(12, 1, val)
1888
1889 #define read_gc0_cause()                __read_32bit_gc0_register(13, 0)
1890 #define write_gc0_cause(val)            __write_32bit_gc0_register(13, 0, val)
1891
1892 #define read_gc0_epc()                  __read_ulong_gc0_register(14, 0)
1893 #define write_gc0_epc(val)              __write_ulong_gc0_register(14, 0, val)
1894
1895 #define read_gc0_ebase()                __read_32bit_gc0_register(15, 1)
1896 #define write_gc0_ebase(val)            __write_32bit_gc0_register(15, 1, val)
1897
1898 #define read_gc0_ebase_64()             __read_64bit_gc0_register(15, 1)
1899 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register(15, 1, val)
1900
1901 #define read_gc0_config()               __read_32bit_gc0_register(16, 0)
1902 #define read_gc0_config1()              __read_32bit_gc0_register(16, 1)
1903 #define read_gc0_config2()              __read_32bit_gc0_register(16, 2)
1904 #define read_gc0_config3()              __read_32bit_gc0_register(16, 3)
1905 #define read_gc0_config4()              __read_32bit_gc0_register(16, 4)
1906 #define read_gc0_config5()              __read_32bit_gc0_register(16, 5)
1907 #define read_gc0_config6()              __read_32bit_gc0_register(16, 6)
1908 #define read_gc0_config7()              __read_32bit_gc0_register(16, 7)
1909 #define write_gc0_config(val)           __write_32bit_gc0_register(16, 0, val)
1910 #define write_gc0_config1(val)          __write_32bit_gc0_register(16, 1, val)
1911 #define write_gc0_config2(val)          __write_32bit_gc0_register(16, 2, val)
1912 #define write_gc0_config3(val)          __write_32bit_gc0_register(16, 3, val)
1913 #define write_gc0_config4(val)          __write_32bit_gc0_register(16, 4, val)
1914 #define write_gc0_config5(val)          __write_32bit_gc0_register(16, 5, val)
1915 #define write_gc0_config6(val)          __write_32bit_gc0_register(16, 6, val)
1916 #define write_gc0_config7(val)          __write_32bit_gc0_register(16, 7, val)
1917
1918 #define read_gc0_watchlo0()             __read_ulong_gc0_register(18, 0)
1919 #define read_gc0_watchlo1()             __read_ulong_gc0_register(18, 1)
1920 #define read_gc0_watchlo2()             __read_ulong_gc0_register(18, 2)
1921 #define read_gc0_watchlo3()             __read_ulong_gc0_register(18, 3)
1922 #define read_gc0_watchlo4()             __read_ulong_gc0_register(18, 4)
1923 #define read_gc0_watchlo5()             __read_ulong_gc0_register(18, 5)
1924 #define read_gc0_watchlo6()             __read_ulong_gc0_register(18, 6)
1925 #define read_gc0_watchlo7()             __read_ulong_gc0_register(18, 7)
1926 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register(18, 0, val)
1927 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register(18, 1, val)
1928 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register(18, 2, val)
1929 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register(18, 3, val)
1930 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register(18, 4, val)
1931 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register(18, 5, val)
1932 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register(18, 6, val)
1933 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register(18, 7, val)
1934
1935 #define read_gc0_watchhi0()             __read_32bit_gc0_register(19, 0)
1936 #define read_gc0_watchhi1()             __read_32bit_gc0_register(19, 1)
1937 #define read_gc0_watchhi2()             __read_32bit_gc0_register(19, 2)
1938 #define read_gc0_watchhi3()             __read_32bit_gc0_register(19, 3)
1939 #define read_gc0_watchhi4()             __read_32bit_gc0_register(19, 4)
1940 #define read_gc0_watchhi5()             __read_32bit_gc0_register(19, 5)
1941 #define read_gc0_watchhi6()             __read_32bit_gc0_register(19, 6)
1942 #define read_gc0_watchhi7()             __read_32bit_gc0_register(19, 7)
1943 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register(19, 0, val)
1944 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register(19, 1, val)
1945 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register(19, 2, val)
1946 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register(19, 3, val)
1947 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register(19, 4, val)
1948 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register(19, 5, val)
1949 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register(19, 6, val)
1950 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register(19, 7, val)
1951
1952 #define read_gc0_xcontext()             __read_ulong_gc0_register(20, 0)
1953 #define write_gc0_xcontext(val)         __write_ulong_gc0_register(20, 0, val)
1954
1955 #define read_gc0_perfctrl0()            __read_32bit_gc0_register(25, 0)
1956 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register(25, 0, val)
1957 #define read_gc0_perfcntr0()            __read_32bit_gc0_register(25, 1)
1958 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register(25, 1, val)
1959 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register(25, 1)
1960 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register(25, 1, val)
1961 #define read_gc0_perfctrl1()            __read_32bit_gc0_register(25, 2)
1962 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register(25, 2, val)
1963 #define read_gc0_perfcntr1()            __read_32bit_gc0_register(25, 3)
1964 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register(25, 3, val)
1965 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register(25, 3)
1966 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register(25, 3, val)
1967 #define read_gc0_perfctrl2()            __read_32bit_gc0_register(25, 4)
1968 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register(25, 4, val)
1969 #define read_gc0_perfcntr2()            __read_32bit_gc0_register(25, 5)
1970 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register(25, 5, val)
1971 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register(25, 5)
1972 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register(25, 5, val)
1973 #define read_gc0_perfctrl3()            __read_32bit_gc0_register(25, 6)
1974 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register(25, 6, val)
1975 #define read_gc0_perfcntr3()            __read_32bit_gc0_register(25, 7)
1976 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register(25, 7, val)
1977 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register(25, 7)
1978 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register(25, 7, val)
1979
1980 #define read_gc0_errorepc()             __read_ulong_gc0_register(30, 0)
1981 #define write_gc0_errorepc(val)         __write_ulong_gc0_register(30, 0, val)
1982
1983 #define read_gc0_kscratch1()            __read_ulong_gc0_register(31, 2)
1984 #define read_gc0_kscratch2()            __read_ulong_gc0_register(31, 3)
1985 #define read_gc0_kscratch3()            __read_ulong_gc0_register(31, 4)
1986 #define read_gc0_kscratch4()            __read_ulong_gc0_register(31, 5)
1987 #define read_gc0_kscratch5()            __read_ulong_gc0_register(31, 6)
1988 #define read_gc0_kscratch6()            __read_ulong_gc0_register(31, 7)
1989 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register(31, 2, val)
1990 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register(31, 3, val)
1991 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register(31, 4, val)
1992 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register(31, 5, val)
1993 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register(31, 6, val)
1994 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register(31, 7, val)
1995
1996 /*
1997  * Macros to access the floating point coprocessor control registers
1998  */
1999 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2000 ({                                                                      \
2001         unsigned int __res;                                             \
2002                                                                         \
2003         __asm__ __volatile__(                                           \
2004         "       .set    push                                    \n"     \
2005         "       .set    reorder                                 \n"     \
2006         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2007         "       # like Octeon.                                  \n"     \
2008         "       .set    mips1                                   \n"     \
2009         "       "STR(gas_hardfloat)"                            \n"     \
2010         "       cfc1    %0,"STR(source)"                        \n"     \
2011         "       .set    pop                                     \n"     \
2012         : "=r" (__res));                                                \
2013         __res;                                                          \
2014 })
2015
2016 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2017 do {                                                                    \
2018         __asm__ __volatile__(                                           \
2019         "       .set    push                                    \n"     \
2020         "       .set    reorder                                 \n"     \
2021         "       "STR(gas_hardfloat)"                            \n"     \
2022         "       ctc1    %0,"STR(dest)"                          \n"     \
2023         "       .set    pop                                     \n"     \
2024         : : "r" (val));                                                 \
2025 } while (0)
2026
2027 #ifdef GAS_HAS_SET_HARDFLOAT
2028 #define read_32bit_cp1_register(source)                                 \
2029         _read_32bit_cp1_register(source, .set hardfloat)
2030 #define write_32bit_cp1_register(dest, val)                             \
2031         _write_32bit_cp1_register(dest, val, .set hardfloat)
2032 #else
2033 #define read_32bit_cp1_register(source)                                 \
2034         _read_32bit_cp1_register(source, )
2035 #define write_32bit_cp1_register(dest, val)                             \
2036         _write_32bit_cp1_register(dest, val, )
2037 #endif
2038
2039 #ifdef HAVE_AS_DSP
2040 #define rddsp(mask)                                                     \
2041 ({                                                                      \
2042         unsigned int __dspctl;                                          \
2043                                                                         \
2044         __asm__ __volatile__(                                           \
2045         "       .set push                                       \n"     \
2046         "       .set dsp                                        \n"     \
2047         "       rddsp   %0, %x1                                 \n"     \
2048         "       .set pop                                        \n"     \
2049         : "=r" (__dspctl)                                               \
2050         : "i" (mask));                                                  \
2051         __dspctl;                                                       \
2052 })
2053
2054 #define wrdsp(val, mask)                                                \
2055 do {                                                                    \
2056         __asm__ __volatile__(                                           \
2057         "       .set push                                       \n"     \
2058         "       .set dsp                                        \n"     \
2059         "       wrdsp   %0, %x1                                 \n"     \
2060         "       .set pop                                        \n"     \
2061         :                                                               \
2062         : "r" (val), "i" (mask));                                       \
2063 } while (0)
2064
2065 #define mflo0()                                                         \
2066 ({                                                                      \
2067         long mflo0;                                                     \
2068         __asm__(                                                        \
2069         "       .set push                                       \n"     \
2070         "       .set dsp                                        \n"     \
2071         "       mflo %0, $ac0                                   \n"     \
2072         "       .set pop                                        \n"     \
2073         : "=r" (mflo0));                                                \
2074         mflo0;                                                          \
2075 })
2076
2077 #define mflo1()                                                         \
2078 ({                                                                      \
2079         long mflo1;                                                     \
2080         __asm__(                                                        \
2081         "       .set push                                       \n"     \
2082         "       .set dsp                                        \n"     \
2083         "       mflo %0, $ac1                                   \n"     \
2084         "       .set pop                                        \n"     \
2085         : "=r" (mflo1));                                                \
2086         mflo1;                                                          \
2087 })
2088
2089 #define mflo2()                                                         \
2090 ({                                                                      \
2091         long mflo2;                                                     \
2092         __asm__(                                                        \
2093         "       .set push                                       \n"     \
2094         "       .set dsp                                        \n"     \
2095         "       mflo %0, $ac2                                   \n"     \
2096         "       .set pop                                        \n"     \
2097         : "=r" (mflo2));                                                \
2098         mflo2;                                                          \
2099 })
2100
2101 #define mflo3()                                                         \
2102 ({                                                                      \
2103         long mflo3;                                                     \
2104         __asm__(                                                        \
2105         "       .set push                                       \n"     \
2106         "       .set dsp                                        \n"     \
2107         "       mflo %0, $ac3                                   \n"     \
2108         "       .set pop                                        \n"     \
2109         : "=r" (mflo3));                                                \
2110         mflo3;                                                          \
2111 })
2112
2113 #define mfhi0()                                                         \
2114 ({                                                                      \
2115         long mfhi0;                                                     \
2116         __asm__(                                                        \
2117         "       .set push                                       \n"     \
2118         "       .set dsp                                        \n"     \
2119         "       mfhi %0, $ac0                                   \n"     \
2120         "       .set pop                                        \n"     \
2121         : "=r" (mfhi0));                                                \
2122         mfhi0;                                                          \
2123 })
2124
2125 #define mfhi1()                                                         \
2126 ({                                                                      \
2127         long mfhi1;                                                     \
2128         __asm__(                                                        \
2129         "       .set push                                       \n"     \
2130         "       .set dsp                                        \n"     \
2131         "       mfhi %0, $ac1                                   \n"     \
2132         "       .set pop                                        \n"     \
2133         : "=r" (mfhi1));                                                \
2134         mfhi1;                                                          \
2135 })
2136
2137 #define mfhi2()                                                         \
2138 ({                                                                      \
2139         long mfhi2;                                                     \
2140         __asm__(                                                        \
2141         "       .set push                                       \n"     \
2142         "       .set dsp                                        \n"     \
2143         "       mfhi %0, $ac2                                   \n"     \
2144         "       .set pop                                        \n"     \
2145         : "=r" (mfhi2));                                                \
2146         mfhi2;                                                          \
2147 })
2148
2149 #define mfhi3()                                                         \
2150 ({                                                                      \
2151         long mfhi3;                                                     \
2152         __asm__(                                                        \
2153         "       .set push                                       \n"     \
2154         "       .set dsp                                        \n"     \
2155         "       mfhi %0, $ac3                                   \n"     \
2156         "       .set pop                                        \n"     \
2157         : "=r" (mfhi3));                                                \
2158         mfhi3;                                                          \
2159 })
2160
2161
2162 #define mtlo0(x)                                                        \
2163 ({                                                                      \
2164         __asm__(                                                        \
2165         "       .set push                                       \n"     \
2166         "       .set dsp                                        \n"     \
2167         "       mtlo %0, $ac0                                   \n"     \
2168         "       .set pop                                        \n"     \
2169         :                                                               \
2170         : "r" (x));                                                     \
2171 })
2172
2173 #define mtlo1(x)                                                        \
2174 ({                                                                      \
2175         __asm__(                                                        \
2176         "       .set push                                       \n"     \
2177         "       .set dsp                                        \n"     \
2178         "       mtlo %0, $ac1                                   \n"     \
2179         "       .set pop                                        \n"     \
2180         :                                                               \
2181         : "r" (x));                                                     \
2182 })
2183
2184 #define mtlo2(x)                                                        \
2185 ({                                                                      \
2186         __asm__(                                                        \
2187         "       .set push                                       \n"     \
2188         "       .set dsp                                        \n"     \
2189         "       mtlo %0, $ac2                                   \n"     \
2190         "       .set pop                                        \n"     \
2191         :                                                               \
2192         : "r" (x));                                                     \
2193 })
2194
2195 #define mtlo3(x)                                                        \
2196 ({                                                                      \
2197         __asm__(                                                        \
2198         "       .set push                                       \n"     \
2199         "       .set dsp                                        \n"     \
2200         "       mtlo %0, $ac3                                   \n"     \
2201         "       .set pop                                        \n"     \
2202         :                                                               \
2203         : "r" (x));                                                     \
2204 })
2205
2206 #define mthi0(x)                                                        \
2207 ({                                                                      \
2208         __asm__(                                                        \
2209         "       .set push                                       \n"     \
2210         "       .set dsp                                        \n"     \
2211         "       mthi %0, $ac0                                   \n"     \
2212         "       .set pop                                        \n"     \
2213         :                                                               \
2214         : "r" (x));                                                     \
2215 })
2216
2217 #define mthi1(x)                                                        \
2218 ({                                                                      \
2219         __asm__(                                                        \
2220         "       .set push                                       \n"     \
2221         "       .set dsp                                        \n"     \
2222         "       mthi %0, $ac1                                   \n"     \
2223         "       .set pop                                        \n"     \
2224         :                                                               \
2225         : "r" (x));                                                     \
2226 })
2227
2228 #define mthi2(x)                                                        \
2229 ({                                                                      \
2230         __asm__(                                                        \
2231         "       .set push                                       \n"     \
2232         "       .set dsp                                        \n"     \
2233         "       mthi %0, $ac2                                   \n"     \
2234         "       .set pop                                        \n"     \
2235         :                                                               \
2236         : "r" (x));                                                     \
2237 })
2238
2239 #define mthi3(x)                                                        \
2240 ({                                                                      \
2241         __asm__(                                                        \
2242         "       .set push                                       \n"     \
2243         "       .set dsp                                        \n"     \
2244         "       mthi %0, $ac3                                   \n"     \
2245         "       .set pop                                        \n"     \
2246         :                                                               \
2247         : "r" (x));                                                     \
2248 })
2249
2250 #else
2251
2252 #ifdef CONFIG_CPU_MICROMIPS
2253 #define rddsp(mask)                                                     \
2254 ({                                                                      \
2255         unsigned int __res;                                             \
2256                                                                         \
2257         __asm__ __volatile__(                                           \
2258         "       .set    push                                    \n"     \
2259         "       .set    noat                                    \n"     \
2260         "       # rddsp $1, %x1                                 \n"     \
2261         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
2262         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
2263         "       move    %0, $1                                  \n"     \
2264         "       .set    pop                                     \n"     \
2265         : "=r" (__res)                                                  \
2266         : "i" (mask));                                                  \
2267         __res;                                                          \
2268 })
2269
2270 #define wrdsp(val, mask)                                                \
2271 do {                                                                    \
2272         __asm__ __volatile__(                                           \
2273         "       .set    push                                    \n"     \
2274         "       .set    noat                                    \n"     \
2275         "       move    $1, %0                                  \n"     \
2276         "       # wrdsp $1, %x1                                 \n"     \
2277         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
2278         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
2279         "       .set    pop                                     \n"     \
2280         :                                                               \
2281         : "r" (val), "i" (mask));                                       \
2282 } while (0)
2283
2284 #define _umips_dsp_mfxxx(ins)                                           \
2285 ({                                                                      \
2286         unsigned long __treg;                                           \
2287                                                                         \
2288         __asm__ __volatile__(                                           \
2289         "       .set    push                                    \n"     \
2290         "       .set    noat                                    \n"     \
2291         "       .hword  0x0001                                  \n"     \
2292         "       .hword  %x1                                     \n"     \
2293         "       move    %0, $1                                  \n"     \
2294         "       .set    pop                                     \n"     \
2295         : "=r" (__treg)                                                 \
2296         : "i" (ins));                                                   \
2297         __treg;                                                         \
2298 })
2299
2300 #define _umips_dsp_mtxxx(val, ins)                                      \
2301 do {                                                                    \
2302         __asm__ __volatile__(                                           \
2303         "       .set    push                                    \n"     \
2304         "       .set    noat                                    \n"     \
2305         "       move    $1, %0                                  \n"     \
2306         "       .hword  0x0001                                  \n"     \
2307         "       .hword  %x1                                     \n"     \
2308         "       .set    pop                                     \n"     \
2309         :                                                               \
2310         : "r" (val), "i" (ins));                                        \
2311 } while (0)
2312
2313 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
2314 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
2315
2316 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
2317 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
2318
2319 #define mflo0() _umips_dsp_mflo(0)
2320 #define mflo1() _umips_dsp_mflo(1)
2321 #define mflo2() _umips_dsp_mflo(2)
2322 #define mflo3() _umips_dsp_mflo(3)
2323
2324 #define mfhi0() _umips_dsp_mfhi(0)
2325 #define mfhi1() _umips_dsp_mfhi(1)
2326 #define mfhi2() _umips_dsp_mfhi(2)
2327 #define mfhi3() _umips_dsp_mfhi(3)
2328
2329 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
2330 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
2331 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
2332 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
2333
2334 #define mthi0(x) _umips_dsp_mthi(x, 0)
2335 #define mthi1(x) _umips_dsp_mthi(x, 1)
2336 #define mthi2(x) _umips_dsp_mthi(x, 2)
2337 #define mthi3(x) _umips_dsp_mthi(x, 3)
2338
2339 #else  /* !CONFIG_CPU_MICROMIPS */
2340 #define rddsp(mask)                                                     \
2341 ({                                                                      \
2342         unsigned int __res;                                             \
2343                                                                         \
2344         __asm__ __volatile__(                                           \
2345         "       .set    push                            \n"             \
2346         "       .set    noat                            \n"             \
2347         "       # rddsp $1, %x1                         \n"             \
2348         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
2349         "       move    %0, $1                          \n"             \
2350         "       .set    pop                             \n"             \
2351         : "=r" (__res)                                                  \
2352         : "i" (mask));                                                  \
2353         __res;                                                          \
2354 })
2355
2356 #define wrdsp(val, mask)                                                \
2357 do {                                                                    \
2358         __asm__ __volatile__(                                           \
2359         "       .set    push                                    \n"     \
2360         "       .set    noat                                    \n"     \
2361         "       move    $1, %0                                  \n"     \
2362         "       # wrdsp $1, %x1                                 \n"     \
2363         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
2364         "       .set    pop                                     \n"     \
2365         :                                                               \
2366         : "r" (val), "i" (mask));                                       \
2367 } while (0)
2368
2369 #define _dsp_mfxxx(ins)                                                 \
2370 ({                                                                      \
2371         unsigned long __treg;                                           \
2372                                                                         \
2373         __asm__ __volatile__(                                           \
2374         "       .set    push                                    \n"     \
2375         "       .set    noat                                    \n"     \
2376         "       .word   (0x00000810 | %1)                       \n"     \
2377         "       move    %0, $1                                  \n"     \
2378         "       .set    pop                                     \n"     \
2379         : "=r" (__treg)                                                 \
2380         : "i" (ins));                                                   \
2381         __treg;                                                         \
2382 })
2383
2384 #define _dsp_mtxxx(val, ins)                                            \
2385 do {                                                                    \
2386         __asm__ __volatile__(                                           \
2387         "       .set    push                                    \n"     \
2388         "       .set    noat                                    \n"     \
2389         "       move    $1, %0                                  \n"     \
2390         "       .word   (0x00200011 | %1)                       \n"     \
2391         "       .set    pop                                     \n"     \
2392         :                                                               \
2393         : "r" (val), "i" (ins));                                        \
2394 } while (0)
2395
2396 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2397 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2398
2399 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2400 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2401
2402 #define mflo0() _dsp_mflo(0)
2403 #define mflo1() _dsp_mflo(1)
2404 #define mflo2() _dsp_mflo(2)
2405 #define mflo3() _dsp_mflo(3)
2406
2407 #define mfhi0() _dsp_mfhi(0)
2408 #define mfhi1() _dsp_mfhi(1)
2409 #define mfhi2() _dsp_mfhi(2)
2410 #define mfhi3() _dsp_mfhi(3)
2411
2412 #define mtlo0(x) _dsp_mtlo(x, 0)
2413 #define mtlo1(x) _dsp_mtlo(x, 1)
2414 #define mtlo2(x) _dsp_mtlo(x, 2)
2415 #define mtlo3(x) _dsp_mtlo(x, 3)
2416
2417 #define mthi0(x) _dsp_mthi(x, 0)
2418 #define mthi1(x) _dsp_mthi(x, 1)
2419 #define mthi2(x) _dsp_mthi(x, 2)
2420 #define mthi3(x) _dsp_mthi(x, 3)
2421
2422 #endif /* CONFIG_CPU_MICROMIPS */
2423 #endif
2424
2425 /*
2426  * TLB operations.
2427  *
2428  * It is responsibility of the caller to take care of any TLB hazards.
2429  */
2430 static inline void tlb_probe(void)
2431 {
2432         __asm__ __volatile__(
2433                 ".set noreorder\n\t"
2434                 "tlbp\n\t"
2435                 ".set reorder");
2436 }
2437
2438 static inline void tlb_read(void)
2439 {
2440 #if MIPS34K_MISSED_ITLB_WAR
2441         int res = 0;
2442
2443         __asm__ __volatile__(
2444         "       .set    push                                    \n"
2445         "       .set    noreorder                               \n"
2446         "       .set    noat                                    \n"
2447         "       .set    mips32r2                                \n"
2448         "       .word   0x41610001              # dvpe $1       \n"
2449         "       move    %0, $1                                  \n"
2450         "       ehb                                             \n"
2451         "       .set    pop                                     \n"
2452         : "=r" (res));
2453
2454         instruction_hazard();
2455 #endif
2456
2457         __asm__ __volatile__(
2458                 ".set noreorder\n\t"
2459                 "tlbr\n\t"
2460                 ".set reorder");
2461
2462 #if MIPS34K_MISSED_ITLB_WAR
2463         if ((res & _ULCAST_(1)))
2464                 __asm__ __volatile__(
2465                 "       .set    push                            \n"
2466                 "       .set    noreorder                       \n"
2467                 "       .set    noat                            \n"
2468                 "       .set    mips32r2                        \n"
2469                 "       .word   0x41600021      # evpe          \n"
2470                 "       ehb                                     \n"
2471                 "       .set    pop                             \n");
2472 #endif
2473 }
2474
2475 static inline void tlb_write_indexed(void)
2476 {
2477         __asm__ __volatile__(
2478                 ".set noreorder\n\t"
2479                 "tlbwi\n\t"
2480                 ".set reorder");
2481 }
2482
2483 static inline void tlb_write_random(void)
2484 {
2485         __asm__ __volatile__(
2486                 ".set noreorder\n\t"
2487                 "tlbwr\n\t"
2488                 ".set reorder");
2489 }
2490
2491 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2492
2493 /*
2494  * Guest TLB operations.
2495  *
2496  * It is responsibility of the caller to take care of any TLB hazards.
2497  */
2498 static inline void guest_tlb_probe(void)
2499 {
2500         __asm__ __volatile__(
2501                 ".set push\n\t"
2502                 ".set noreorder\n\t"
2503                 ".set virt\n\t"
2504                 "tlbgp\n\t"
2505                 ".set pop");
2506 }
2507
2508 static inline void guest_tlb_read(void)
2509 {
2510         __asm__ __volatile__(
2511                 ".set push\n\t"
2512                 ".set noreorder\n\t"
2513                 ".set virt\n\t"
2514                 "tlbgr\n\t"
2515                 ".set pop");
2516 }
2517
2518 static inline void guest_tlb_write_indexed(void)
2519 {
2520         __asm__ __volatile__(
2521                 ".set push\n\t"
2522                 ".set noreorder\n\t"
2523                 ".set virt\n\t"
2524                 "tlbgwi\n\t"
2525                 ".set pop");
2526 }
2527
2528 static inline void guest_tlb_write_random(void)
2529 {
2530         __asm__ __volatile__(
2531                 ".set push\n\t"
2532                 ".set noreorder\n\t"
2533                 ".set virt\n\t"
2534                 "tlbgwr\n\t"
2535                 ".set pop");
2536 }
2537
2538 /*
2539  * Guest TLB Invalidate Flush
2540  */
2541 static inline void guest_tlbinvf(void)
2542 {
2543         __asm__ __volatile__(
2544                 ".set push\n\t"
2545                 ".set noreorder\n\t"
2546                 ".set virt\n\t"
2547                 "tlbginvf\n\t"
2548                 ".set pop");
2549 }
2550
2551 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
2552
2553 /*
2554  * Guest TLB operations.
2555  *
2556  * It is responsibility of the caller to take care of any TLB hazards.
2557  */
2558 static inline void guest_tlb_probe(void)
2559 {
2560         __asm__ __volatile__(
2561                 "# tlbgp\n\t"
2562                 ".word 0x42000010");
2563 }
2564
2565 static inline void guest_tlb_read(void)
2566 {
2567         __asm__ __volatile__(
2568                 "# tlbgr\n\t"
2569                 ".word 0x42000009");
2570 }
2571
2572 static inline void guest_tlb_write_indexed(void)
2573 {
2574         __asm__ __volatile__(
2575                 "# tlbgwi\n\t"
2576                 ".word 0x4200000a");
2577 }
2578
2579 static inline void guest_tlb_write_random(void)
2580 {
2581         __asm__ __volatile__(
2582                 "# tlbgwr\n\t"
2583                 ".word 0x4200000e");
2584 }
2585
2586 /*
2587  * Guest TLB Invalidate Flush
2588  */
2589 static inline void guest_tlbinvf(void)
2590 {
2591         __asm__ __volatile__(
2592                 "# tlbginvf\n\t"
2593                 ".word 0x4200000c");
2594 }
2595
2596 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
2597
2598 /*
2599  * Manipulate bits in a register.
2600  */
2601 #define __BUILD_SET_COMMON(name)                                \
2602 static inline unsigned int                                      \
2603 set_##name(unsigned int set)                                    \
2604 {                                                               \
2605         unsigned int res, new;                                  \
2606                                                                 \
2607         res = read_##name();                                    \
2608         new = res | set;                                        \
2609         write_##name(new);                                      \
2610                                                                 \
2611         return res;                                             \
2612 }                                                               \
2613                                                                 \
2614 static inline unsigned int                                      \
2615 clear_##name(unsigned int clear)                                \
2616 {                                                               \
2617         unsigned int res, new;                                  \
2618                                                                 \
2619         res = read_##name();                                    \
2620         new = res & ~clear;                                     \
2621         write_##name(new);                                      \
2622                                                                 \
2623         return res;                                             \
2624 }                                                               \
2625                                                                 \
2626 static inline unsigned int                                      \
2627 change_##name(unsigned int change, unsigned int val)            \
2628 {                                                               \
2629         unsigned int res, new;                                  \
2630                                                                 \
2631         res = read_##name();                                    \
2632         new = res & ~change;                                    \
2633         new |= (val & change);                                  \
2634         write_##name(new);                                      \
2635                                                                 \
2636         return res;                                             \
2637 }
2638
2639 /*
2640  * Manipulate bits in a c0 register.
2641  */
2642 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2643
2644 __BUILD_SET_C0(status)
2645 __BUILD_SET_C0(cause)
2646 __BUILD_SET_C0(config)
2647 __BUILD_SET_C0(config5)
2648 __BUILD_SET_C0(intcontrol)
2649 __BUILD_SET_C0(intctl)
2650 __BUILD_SET_C0(srsmap)
2651 __BUILD_SET_C0(pagegrain)
2652 __BUILD_SET_C0(guestctl0)
2653 __BUILD_SET_C0(guestctl0ext)
2654 __BUILD_SET_C0(guestctl1)
2655 __BUILD_SET_C0(guestctl2)
2656 __BUILD_SET_C0(guestctl3)
2657 __BUILD_SET_C0(brcm_config_0)
2658 __BUILD_SET_C0(brcm_bus_pll)
2659 __BUILD_SET_C0(brcm_reset)
2660 __BUILD_SET_C0(brcm_cmt_intr)
2661 __BUILD_SET_C0(brcm_cmt_ctrl)
2662 __BUILD_SET_C0(brcm_config)
2663 __BUILD_SET_C0(brcm_mode)
2664
2665 /*
2666  * Manipulate bits in a guest c0 register.
2667  */
2668 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2669
2670 __BUILD_SET_GC0(status)
2671 __BUILD_SET_GC0(cause)
2672 __BUILD_SET_GC0(ebase)
2673
2674 /*
2675  * Return low 10 bits of ebase.
2676  * Note that under KVM (MIPSVZ) this returns vcpu id.
2677  */
2678 static inline unsigned int get_ebase_cpunum(void)
2679 {
2680         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2681 }
2682
2683 #endif /* !__ASSEMBLY__ */
2684
2685 #endif /* _ASM_MIPSREGS_H */