arch/powerpc/mm/hash_utils_64.c

   1 /*
   2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
   3  *   {mikejc|engebret}@us.ibm.com
   4  *
   5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
   6  *
   7  * SMP scalability work:
   8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *    Module name: htab.c
  11  *
  12  *    Description:
  13  *      PowerPC Hashed Page Table functions
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  */
  20
  21 #undef DEBUG
  22 #undef DEBUG_LOW
  23
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/sched.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/stat.h>
  29 #include <linux/sysctl.h>
  30 #include <linux/export.h>
  31 #include <linux/ctype.h>
  32 #include <linux/cache.h>
  33 #include <linux/init.h>
  34 #include <linux/signal.h>
  35 #include <linux/memblock.h>
  36
  37 #include <asm/processor.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/mmu.h>
  40 #include <asm/mmu_context.h>
  41 #include <asm/page.h>
  42 #include <asm/types.h>
  43 #include <asm/uaccess.h>
  44 #include <asm/machdep.h>
  45 #include <asm/prom.h>
  46 #include <asm/tlbflush.h>
  47 #include <asm/io.h>
  48 #include <asm/eeh.h>
  49 #include <asm/tlb.h>
  50 #include <asm/cacheflush.h>
  51 #include <asm/cputable.h>
  52 #include <asm/sections.h>
  53 #include <asm/spu.h>
  54 #include <asm/udbg.h>
  55 #include <asm/code-patching.h>
  56 #include <asm/fadump.h>
  57 #include <asm/firmware.h>
  58 #include <asm/tm.h>
  59
  60 #ifdef DEBUG
  61 #define DBG(fmt...) udbg_printf(fmt)
  62 #else
  63 #define DBG(fmt...)
  64 #endif
  65
  66 #ifdef DEBUG_LOW
  67 #define DBG_LOW(fmt...) udbg_printf(fmt)
  68 #else
  69 #define DBG_LOW(fmt...)
  70 #endif
  71
  72 #define KB (1024)
  73 #define MB (1024*KB)
  74 #define GB (1024L*MB)
  75
  76 /*
  77  * Note:  pte   --> Linux PTE
  78  *        HPTE  --> PowerPC Hashed Page Table Entry
  79  *
  80  * Execution context:
  81  *   htab_initialize is called with the MMU off (of course), but
  82  *   the kernel has been copied down to zero so it can directly
  83  *   reference global data.  At this point it is very difficult
  84  *   to print debug info.
  85  *
  86  */
  87
  88 #ifdef CONFIG_U3_DART
  89 extern unsigned long dart_tablebase;
  90 #endif /* CONFIG_U3_DART */
  91
  92 static unsigned long _SDR1;
  93 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  94
  95 struct hash_pte *htab_address;
  96 unsigned long htab_size_bytes;
  97 unsigned long htab_hash_mask;
  98 EXPORT_SYMBOL_GPL(htab_hash_mask);
  99 int mmu_linear_psize = MMU_PAGE_4K;
 100 int mmu_virtual_psize = MMU_PAGE_4K;
 101 int mmu_vmalloc_psize = MMU_PAGE_4K;
 102 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 103 int mmu_vmemmap_psize = MMU_PAGE_4K;
 104 #endif
 105 int mmu_io_psize = MMU_PAGE_4K;
 106 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
 107 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
 108 u16 mmu_slb_size = 64;
 109 EXPORT_SYMBOL_GPL(mmu_slb_size);
 110 #ifdef CONFIG_PPC_64K_PAGES
 111 int mmu_ci_restrictions;
 112 #endif
 113 #ifdef CONFIG_DEBUG_PAGEALLOC
 114 static u8 *linear_map_hash_slots;
 115 static unsigned long linear_map_hash_count;
 116 static DEFINE_SPINLOCK(linear_map_hash_lock);
 117 #endif /* CONFIG_DEBUG_PAGEALLOC */
 118
 119 /* There are definitions of page sizes arrays to be used when none
 120  * is provided by the firmware.
 121  */
 122
 123 /* Pre-POWER4 CPUs (4k pages only)
 124  */
 125 static struct mmu_psize_def mmu_psize_defaults_old[] = {
 126         [MMU_PAGE_4K] = {
 127                 .shift  = 12,
 128                 .sllp   = 0,
 129                 .penc   = 0,
 130                 .avpnm  = 0,
 131                 .tlbiel = 0,
 132         },
 133 };
 134
 135 /* POWER4, GPUL, POWER5
 136  *
 137  * Support for 16Mb large pages
 138  */
 139 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
 140         [MMU_PAGE_4K] = {
 141                 .shift  = 12,
 142                 .sllp   = 0,
 143                 .penc   = 0,
 144                 .avpnm  = 0,
 145                 .tlbiel = 1,
 146         },
 147         [MMU_PAGE_16M] = {
 148                 .shift  = 24,
 149                 .sllp   = SLB_VSID_L,
 150                 .penc   = 0,
 151                 .avpnm  = 0x1UL,
 152                 .tlbiel = 0,
 153         },
 154 };
 155
 156 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
 157 {
 158         unsigned long rflags = pteflags & 0x1fa;
 159
 160         /* _PAGE_EXEC -> NOEXEC */
 161         if ((pteflags & _PAGE_EXEC) == 0)
 162                 rflags |= HPTE_R_N;
 163
 164         /* PP bits. PAGE_USER is already PP bit 0x2, so we only
 165          * need to add in 0x1 if it's a read-only user page
 166          */
 167         if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
 168                                          (pteflags & _PAGE_DIRTY)))
 169                 rflags |= 1;
 170
 171         /* Always add C */
 172         return rflags | HPTE_R_C;
 173 }
 174
 175 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 176                       unsigned long pstart, unsigned long prot,
 177                       int psize, int ssize)
 178 {
 179         unsigned long vaddr, paddr;
 180         unsigned int step, shift;
 181         int ret = 0;
 182
 183         shift = mmu_psize_defs[psize].shift;
 184         step = 1 << shift;
 185
 186         prot = htab_convert_pte_flags(prot);
 187
 188         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
 189             vstart, vend, pstart, prot, psize, ssize);
 190
 191         for (vaddr = vstart, paddr = pstart; vaddr < vend;
 192              vaddr += step, paddr += step) {
 193                 unsigned long hash, hpteg;
 194                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
 195                 unsigned long vpn  = hpt_vpn(vaddr, vsid, ssize);
 196                 unsigned long tprot = prot;
 197
 198                 /*
 199                  * If we hit a bad address return error.
 200                  */
 201                 if (!vsid)
 202                         return -1;
 203                 /* Make kernel text executable */
 204                 if (overlaps_kernel_text(vaddr, vaddr + step))
 205                         tprot &= ~HPTE_R_N;
 206
 207                 hash = hpt_hash(vpn, shift, ssize);
 208                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 209
 210                 BUG_ON(!ppc_md.hpte_insert);
 211                 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
 212                                          HPTE_V_BOLTED, psize, ssize);
 213
 214                 if (ret < 0)
 215                         break;
 216 #ifdef CONFIG_DEBUG_PAGEALLOC
 217                 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
 218                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
 219 #endif /* CONFIG_DEBUG_PAGEALLOC */
 220         }
 221         return ret < 0 ? ret : 0;
 222 }
 223
 224 #ifdef CONFIG_MEMORY_HOTPLUG
 225 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
 226                       int psize, int ssize)
 227 {
 228         unsigned long vaddr;
 229         unsigned int step, shift;
 230
 231         shift = mmu_psize_defs[psize].shift;
 232         step = 1 << shift;
 233
 234         if (!ppc_md.hpte_removebolted) {
 235                 printk(KERN_WARNING "Platform doesn't implement "
 236                                 "hpte_removebolted\n");
 237                 return -EINVAL;
 238         }
 239
 240         for (vaddr = vstart; vaddr < vend; vaddr += step)
 241                 ppc_md.hpte_removebolted(vaddr, psize, ssize);
 242
 243         return 0;
 244 }
 245 #endif /* CONFIG_MEMORY_HOTPLUG */
 246
 247 static int __init htab_dt_scan_seg_sizes(unsigned long node,
 248                                          const char *uname, int depth,
 249                                          void *data)
 250 {
 251         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 252         u32 *prop;
 253         unsigned long size = 0;
 254
 255         /* We are scanning "cpu" nodes only */
 256         if (type == NULL || strcmp(type, "cpu") != 0)
 257                 return 0;
 258
 259         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
 260                                           &size);
 261         if (prop == NULL)
 262                 return 0;
 263         for (; size >= 4; size -= 4, ++prop) {
 264                 if (prop[0] == 40) {
 265                         DBG("1T segment support detected\n");
 266                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
 267                         return 1;
 268                 }
 269         }
 270         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 271         return 0;
 272 }
 273
 274 static void __init htab_init_seg_sizes(void)
 275 {
 276         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
 277 }
 278
 279 static int __init htab_dt_scan_page_sizes(unsigned long node,
 280                                           const char *uname, int depth,
 281                                           void *data)
 282 {
 283         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 284         u32 *prop;
 285         unsigned long size = 0;
 286
 287         /* We are scanning "cpu" nodes only */
 288         if (type == NULL || strcmp(type, "cpu") != 0)
 289                 return 0;
 290
 291         prop = (u32 *)of_get_flat_dt_prop(node,
 292                                           "ibm,segment-page-sizes", &size);
 293         if (prop != NULL) {
 294                 DBG("Page sizes from device-tree:\n");
 295                 size /= 4;
 296                 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
 297                 while(size > 0) {
 298                         unsigned int shift = prop[0];
 299                         unsigned int slbenc = prop[1];
 300                         unsigned int lpnum = prop[2];
 301                         unsigned int lpenc = 0;
 302                         struct mmu_psize_def *def;
 303                         int idx = -1;
 304
 305                         size -= 3; prop += 3;
 306                         while(size > 0 && lpnum) {
 307                                 if (prop[0] == shift)
 308                                         lpenc = prop[1];
 309                                 prop += 2; size -= 2;
 310                                 lpnum--;
 311                         }
 312                         switch(shift) {
 313                         case 0xc:
 314                                 idx = MMU_PAGE_4K;
 315                                 break;
 316                         case 0x10:
 317                                 idx = MMU_PAGE_64K;
 318                                 break;
 319                         case 0x14:
 320                                 idx = MMU_PAGE_1M;
 321                                 break;
 322                         case 0x18:
 323                                 idx = MMU_PAGE_16M;
 324                                 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
 325                                 break;
 326                         case 0x22:
 327                                 idx = MMU_PAGE_16G;
 328                                 break;
 329                         }
 330                         if (idx < 0)
 331                                 continue;
 332                         def = &mmu_psize_defs[idx];
 333                         def->shift = shift;
 334                         if (shift <= 23)
 335                                 def->avpnm = 0;
 336                         else
 337                                 def->avpnm = (1 << (shift - 23)) - 1;
 338                         def->sllp = slbenc;
 339                         def->penc = lpenc;
 340                         /* We don't know for sure what's up with tlbiel, so
 341                          * for now we only set it for 4K and 64K pages
 342                          */
 343                         if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
 344                                 def->tlbiel = 1;
 345                         else
 346                                 def->tlbiel = 0;
 347
 348                         DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
 349                             "tlbiel=%d, penc=%d\n",
 350                             idx, shift, def->sllp, def->avpnm, def->tlbiel,
 351                             def->penc);
 352                 }
 353                 return 1;
 354         }
 355         return 0;
 356 }
 357
 358 #ifdef CONFIG_HUGETLB_PAGE
 359 /* Scan for 16G memory blocks that have been set aside for huge pages
 360  * and reserve those blocks for 16G huge pages.
 361  */
 362 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
 363                                         const char *uname, int depth,
 364                                         void *data) {
 365         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 366         unsigned long *addr_prop;
 367         u32 *page_count_prop;
 368         unsigned int expected_pages;
 369         long unsigned int phys_addr;
 370         long unsigned int block_size;
 371
 372         /* We are scanning "memory" nodes only */
 373         if (type == NULL || strcmp(type, "memory") != 0)
 374                 return 0;
 375
 376         /* This property is the log base 2 of the number of virtual pages that
 377          * will represent this memory block. */
 378         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
 379         if (page_count_prop == NULL)
 380                 return 0;
 381         expected_pages = (1 << page_count_prop[0]);
 382         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
 383         if (addr_prop == NULL)
 384                 return 0;
 385         phys_addr = addr_prop[0];
 386         block_size = addr_prop[1];
 387         if (block_size != (16 * GB))
 388                 return 0;
 389         printk(KERN_INFO "Huge page(16GB) memory: "
 390                         "addr = 0x%lX size = 0x%lX pages = %d\n",
 391                         phys_addr, block_size, expected_pages);
 392         if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
 393                 memblock_reserve(phys_addr, block_size * expected_pages);
 394                 add_gpage(phys_addr, block_size, expected_pages);
 395         }
 396         return 0;
 397 }
 398 #endif /* CONFIG_HUGETLB_PAGE */
 399
 400 static void __init htab_init_page_sizes(void)
 401 {
 402         int rc;
 403
 404         /* Default to 4K pages only */
 405         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
 406                sizeof(mmu_psize_defaults_old));
 407
 408         /*
 409          * Try to find the available page sizes in the device-tree
 410          */
 411         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
 412         if (rc != 0)  /* Found */
 413                 goto found;
 414
 415         /*
 416          * Not in the device-tree, let's fallback on known size
 417          * list for 16M capable GP & GR
 418          */
 419         if (mmu_has_feature(MMU_FTR_16M_PAGE))
 420                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
 421                        sizeof(mmu_psize_defaults_gp));
 422  found:
 423 #ifndef CONFIG_DEBUG_PAGEALLOC
 424         /*
 425          * Pick a size for the linear mapping. Currently, we only support
 426          * 16M, 1M and 4K which is the default
 427          */
 428         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 429                 mmu_linear_psize = MMU_PAGE_16M;
 430         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 431                 mmu_linear_psize = MMU_PAGE_1M;
 432 #endif /* CONFIG_DEBUG_PAGEALLOC */
 433
 434 #ifdef CONFIG_PPC_64K_PAGES
 435         /*
 436          * Pick a size for the ordinary pages. Default is 4K, we support
 437          * 64K for user mappings and vmalloc if supported by the processor.
 438          * We only use 64k for ioremap if the processor
 439          * (and firmware) support cache-inhibited large pages.
 440          * If not, we use 4k and set mmu_ci_restrictions so that
 441          * hash_page knows to switch processes that use cache-inhibited
 442          * mappings to 4k pages.
 443          */
 444         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
 445                 mmu_virtual_psize = MMU_PAGE_64K;
 446                 mmu_vmalloc_psize = MMU_PAGE_64K;
 447                 if (mmu_linear_psize == MMU_PAGE_4K)
 448                         mmu_linear_psize = MMU_PAGE_64K;
 449                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
 450                         /*
 451                          * Don't use 64k pages for ioremap on pSeries, since
 452                          * that would stop us accessing the HEA ethernet.
 453                          */
 454                         if (!machine_is(pseries))
 455                                 mmu_io_psize = MMU_PAGE_64K;
 456                 } else
 457                         mmu_ci_restrictions = 1;
 458         }
 459 #endif /* CONFIG_PPC_64K_PAGES */
 460
 461 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 462         /* We try to use 16M pages for vmemmap if that is supported
 463          * and we have at least 1G of RAM at boot
 464          */
 465         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
 466             memblock_phys_mem_size() >= 0x40000000)
 467                 mmu_vmemmap_psize = MMU_PAGE_16M;
 468         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
 469                 mmu_vmemmap_psize = MMU_PAGE_64K;
 470         else
 471                 mmu_vmemmap_psize = MMU_PAGE_4K;
 472 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 473
 474         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
 475                "virtual = %d, io = %d"
 476 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 477                ", vmemmap = %d"
 478 #endif
 479                "\n",
 480                mmu_psize_defs[mmu_linear_psize].shift,
 481                mmu_psize_defs[mmu_virtual_psize].shift,
 482                mmu_psize_defs[mmu_io_psize].shift
 483 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 484                ,mmu_psize_defs[mmu_vmemmap_psize].shift
 485 #endif
 486                );
 487
 488 #ifdef CONFIG_HUGETLB_PAGE
 489         /* Reserve 16G huge page memory sections for huge pages */
 490         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
 491 #endif /* CONFIG_HUGETLB_PAGE */
 492 }
 493
 494 static int __init htab_dt_scan_pftsize(unsigned long node,
 495                                        const char *uname, int depth,
 496                                        void *data)
 497 {
 498         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 499         u32 *prop;
 500
 501         /* We are scanning "cpu" nodes only */
 502         if (type == NULL || strcmp(type, "cpu") != 0)
 503                 return 0;
 504
 505         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
 506         if (prop != NULL) {
 507                 /* pft_size[0] is the NUMA CEC cookie */
 508                 ppc64_pft_size = prop[1];
 509                 return 1;
 510         }
 511         return 0;
 512 }
 513
 514 static unsigned long __init htab_get_table_size(void)
 515 {
 516         unsigned long mem_size, rnd_mem_size, pteg_count, psize;
 517
 518         /* If hash size isn't already provided by the platform, we try to
 519          * retrieve it from the device-tree. If it's not there neither, we
 520          * calculate it now based on the total RAM size
 521          */
 522         if (ppc64_pft_size == 0)
 523                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
 524         if (ppc64_pft_size)
 525                 return 1UL << ppc64_pft_size;
 526
 527         /* round mem_size up to next power of 2 */
 528         mem_size = memblock_phys_mem_size();
 529         rnd_mem_size = 1UL << __ilog2(mem_size);
 530         if (rnd_mem_size < mem_size)
 531                 rnd_mem_size <<= 1;
 532
 533         /* # pages / 2 */
 534         psize = mmu_psize_defs[mmu_virtual_psize].shift;
 535         pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
 536
 537         return pteg_count << 7;
 538 }
 539
 540 #ifdef CONFIG_MEMORY_HOTPLUG
 541 int create_section_mapping(unsigned long start, unsigned long end)
 542 {
 543         return htab_bolt_mapping(start, end, __pa(start),
 544                                  pgprot_val(PAGE_KERNEL), mmu_linear_psize,
 545                                  mmu_kernel_ssize);
 546 }
 547
 548 int remove_section_mapping(unsigned long start, unsigned long end)
 549 {
 550         return htab_remove_mapping(start, end, mmu_linear_psize,
 551                         mmu_kernel_ssize);
 552 }
 553 #endif /* CONFIG_MEMORY_HOTPLUG */
 554
 555 #define FUNCTION_TEXT(A)        ((*(unsigned long *)(A)))
 556
 557 static void __init htab_finish_init(void)
 558 {
 559         extern unsigned int *htab_call_hpte_insert1;
 560         extern unsigned int *htab_call_hpte_insert2;
 561         extern unsigned int *htab_call_hpte_remove;
 562         extern unsigned int *htab_call_hpte_updatepp;
 563
 564 #ifdef CONFIG_PPC_HAS_HASH_64K
 565         extern unsigned int *ht64_call_hpte_insert1;
 566         extern unsigned int *ht64_call_hpte_insert2;
 567         extern unsigned int *ht64_call_hpte_remove;
 568         extern unsigned int *ht64_call_hpte_updatepp;
 569
 570         patch_branch(ht64_call_hpte_insert1,
 571                 FUNCTION_TEXT(ppc_md.hpte_insert),
 572                 BRANCH_SET_LINK);
 573         patch_branch(ht64_call_hpte_insert2,
 574                 FUNCTION_TEXT(ppc_md.hpte_insert),
 575                 BRANCH_SET_LINK);
 576         patch_branch(ht64_call_hpte_remove,
 577                 FUNCTION_TEXT(ppc_md.hpte_remove),
 578                 BRANCH_SET_LINK);
 579         patch_branch(ht64_call_hpte_updatepp,
 580                 FUNCTION_TEXT(ppc_md.hpte_updatepp),
 581                 BRANCH_SET_LINK);
 582
 583 #endif /* CONFIG_PPC_HAS_HASH_64K */
 584
 585         patch_branch(htab_call_hpte_insert1,
 586                 FUNCTION_TEXT(ppc_md.hpte_insert),
 587                 BRANCH_SET_LINK);
 588         patch_branch(htab_call_hpte_insert2,
 589                 FUNCTION_TEXT(ppc_md.hpte_insert),
 590                 BRANCH_SET_LINK);
 591         patch_branch(htab_call_hpte_remove,
 592                 FUNCTION_TEXT(ppc_md.hpte_remove),
 593                 BRANCH_SET_LINK);
 594         patch_branch(htab_call_hpte_updatepp,
 595                 FUNCTION_TEXT(ppc_md.hpte_updatepp),
 596                 BRANCH_SET_LINK);
 597 }
 598
 599 static void __init htab_initialize(void)
 600 {
 601         unsigned long table;
 602         unsigned long pteg_count;
 603         unsigned long prot;
 604         unsigned long base = 0, size = 0, limit;
 605         struct memblock_region *reg;
 606
 607         DBG(" -> htab_initialize()\n");
 608
 609         /* Initialize segment sizes */
 610         htab_init_seg_sizes();
 611
 612         /* Initialize page sizes */
 613         htab_init_page_sizes();
 614
 615         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
 616                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
 617                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
 618                 printk(KERN_INFO "Using 1TB segments\n");
 619         }
 620
 621         /*
 622          * Calculate the required size of the htab.  We want the number of
 623          * PTEGs to equal one half the number of real pages.
 624          */
 625         htab_size_bytes = htab_get_table_size();
 626         pteg_count = htab_size_bytes >> 7;
 627
 628         htab_hash_mask = pteg_count - 1;
 629
 630         if (firmware_has_feature(FW_FEATURE_LPAR)) {
 631                 /* Using a hypervisor which owns the htab */
 632                 htab_address = NULL;
 633                 _SDR1 = 0;
 634 #ifdef CONFIG_FA_DUMP
 635                 /*
 636                  * If firmware assisted dump is active firmware preserves
 637                  * the contents of htab along with entire partition memory.
 638                  * Clear the htab if firmware assisted dump is active so
 639                  * that we dont end up using old mappings.
 640                  */
 641                 if (is_fadump_active() && ppc_md.hpte_clear_all)
 642                         ppc_md.hpte_clear_all();
 643 #endif
 644         } else {
 645                 /* Find storage for the HPT.  Must be contiguous in
 646                  * the absolute address space. On cell we want it to be
 647                  * in the first 2 Gig so we can use it for IOMMU hacks.
 648                  */
 649                 if (machine_is(cell))
 650                         limit = 0x80000000;
 651                 else
 652                         limit = MEMBLOCK_ALLOC_ANYWHERE;
 653
 654                 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
 655
 656                 DBG("Hash table allocated at %lx, size: %lx\n", table,
 657                     htab_size_bytes);
 658
 659                 htab_address = __va(table);
 660
 661                 /* htab absolute addr + encoded htabsize */
 662                 _SDR1 = table + __ilog2(pteg_count) - 11;
 663
 664                 /* Initialize the HPT with no entries */
 665                 memset((void *)table, 0, htab_size_bytes);
 666
 667                 /* Set SDR1 */
 668                 mtspr(SPRN_SDR1, _SDR1);
 669         }
 670
 671         prot = pgprot_val(PAGE_KERNEL);
 672
 673 #ifdef CONFIG_DEBUG_PAGEALLOC
 674         linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
 675         linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
 676                                                     1, ppc64_rma_size));
 677         memset(linear_map_hash_slots, 0, linear_map_hash_count);
 678 #endif /* CONFIG_DEBUG_PAGEALLOC */
 679
 680         /* On U3 based machines, we need to reserve the DART area and
 681          * _NOT_ map it to avoid cache paradoxes as it's remapped non
 682          * cacheable later on
 683          */
 684
 685         /* create bolted the linear mapping in the hash table */
 686         for_each_memblock(memory, reg) {
 687                 base = (unsigned long)__va(reg->base);
 688                 size = reg->size;
 689
 690                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
 691                     base, size, prot);
 692
 693 #ifdef CONFIG_U3_DART
 694                 /* Do not map the DART space. Fortunately, it will be aligned
 695                  * in such a way that it will not cross two memblock regions and
 696                  * will fit within a single 16Mb page.
 697                  * The DART space is assumed to be a full 16Mb region even if
 698                  * we only use 2Mb of that space. We will use more of it later
 699                  * for AGP GART. We have to use a full 16Mb large page.
 700                  */
 701                 DBG("DART base: %lx\n", dart_tablebase);
 702
 703                 if (dart_tablebase != 0 && dart_tablebase >= base
 704                     && dart_tablebase < (base + size)) {
 705                         unsigned long dart_table_end = dart_tablebase + 16 * MB;
 706                         if (base != dart_tablebase)
 707                                 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
 708                                                         __pa(base), prot,
 709                                                         mmu_linear_psize,
 710                                                         mmu_kernel_ssize));
 711                         if ((base + size) > dart_table_end)
 712                                 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
 713                                                         base + size,
 714                                                         __pa(dart_table_end),
 715                                                          prot,
 716                                                          mmu_linear_psize,
 717                                                          mmu_kernel_ssize));
 718                         continue;
 719                 }
 720 #endif /* CONFIG_U3_DART */
 721                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
 722                                 prot, mmu_linear_psize, mmu_kernel_ssize));
 723         }
 724         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 725
 726         /*
 727          * If we have a memory_limit and we've allocated TCEs then we need to
 728          * explicitly map the TCE area at the top of RAM. We also cope with the
 729          * case that the TCEs start below memory_limit.
 730          * tce_alloc_start/end are 16MB aligned so the mapping should work
 731          * for either 4K or 16MB pages.
 732          */
 733         if (tce_alloc_start) {
 734                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
 735                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
 736
 737                 if (base + size >= tce_alloc_start)
 738                         tce_alloc_start = base + size + 1;
 739
 740                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
 741                                          __pa(tce_alloc_start), prot,
 742                                          mmu_linear_psize, mmu_kernel_ssize));
 743         }
 744
 745         htab_finish_init();
 746
 747         DBG(" <- htab_initialize()\n");
 748 }
 749 #undef KB
 750 #undef MB
 751
 752 void __init early_init_mmu(void)
 753 {
 754         /* Setup initial STAB address in the PACA */
 755         get_paca()->stab_real = __pa((u64)&initial_stab);
 756         get_paca()->stab_addr = (u64)&initial_stab;
 757
 758         /* Initialize the MMU Hash table and create the linear mapping
 759          * of memory. Has to be done before stab/slb initialization as
 760          * this is currently where the page size encoding is obtained
 761          */
 762         htab_initialize();
 763
 764         /* Initialize stab / SLB management */
 765         if (mmu_has_feature(MMU_FTR_SLB))
 766                 slb_initialize();
 767         else
 768                 stab_initialize(get_paca()->stab_real);
 769 }
 770
 771 #ifdef CONFIG_SMP
 772 void __cpuinit early_init_mmu_secondary(void)
 773 {
 774         /* Initialize hash table for that CPU */
 775         if (!firmware_has_feature(FW_FEATURE_LPAR))
 776                 mtspr(SPRN_SDR1, _SDR1);
 777
 778         /* Initialize STAB/SLB. We use a virtual address as it works
 779          * in real mode on pSeries.
 780          */
 781         if (mmu_has_feature(MMU_FTR_SLB))
 782                 slb_initialize();
 783         else
 784                 stab_initialize(get_paca()->stab_addr);
 785 }
 786 #endif /* CONFIG_SMP */
 787
 788 /*
 789  * Called by asm hashtable.S for doing lazy icache flush
 790  */
 791 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
 792 {
 793         struct page *page;
 794
 795         if (!pfn_valid(pte_pfn(pte)))
 796                 return pp;
 797
 798         page = pte_page(pte);
 799
 800         /* page is dirty */
 801         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
 802                 if (trap == 0x400) {
 803                         flush_dcache_icache_page(page);
 804                         set_bit(PG_arch_1, &page->flags);
 805                 } else
 806                         pp |= HPTE_R_N;
 807         }
 808         return pp;
 809 }
 810
 811 #ifdef CONFIG_PPC_MM_SLICES
 812 unsigned int get_paca_psize(unsigned long addr)
 813 {
 814         u64 lpsizes;
 815         unsigned char *hpsizes;
 816         unsigned long index, mask_index;
 817
 818         if (addr < SLICE_LOW_TOP) {
 819                 lpsizes = get_paca()->context.low_slices_psize;
 820                 index = GET_LOW_SLICE_INDEX(addr);
 821                 return (lpsizes >> (index * 4)) & 0xF;
 822         }
 823         hpsizes = get_paca()->context.high_slices_psize;
 824         index = GET_HIGH_SLICE_INDEX(addr);
 825         mask_index = index & 0x1;
 826         return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
 827 }
 828
 829 #else
 830 unsigned int get_paca_psize(unsigned long addr)
 831 {
 832         return get_paca()->context.user_psize;
 833 }
 834 #endif
 835
 836 /*
 837  * Demote a segment to using 4k pages.
 838  * For now this makes the whole process use 4k pages.
 839  */
 840 #ifdef CONFIG_PPC_64K_PAGES
 841 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
 842 {
 843         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
 844                 return;
 845         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
 846 #ifdef CONFIG_SPU_BASE
 847         spu_flush_all_slbs(mm);
 848 #endif
 849         if (get_paca_psize(addr) != MMU_PAGE_4K) {
 850                 get_paca()->context = mm->context;
 851                 slb_flush_and_rebolt();
 852         }
 853 }
 854 #endif /* CONFIG_PPC_64K_PAGES */
 855
 856 #ifdef CONFIG_PPC_SUBPAGE_PROT
 857 /*
 858  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
 859  * Userspace sets the subpage permissions using the subpage_prot system call.
 860  *
 861  * Result is 0: full permissions, _PAGE_RW: read-only,
 862  * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
 863  */
 864 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
 865 {
 866         struct subpage_prot_table *spt = &mm->context.spt;
 867         u32 spp = 0;
 868         u32 **sbpm, *sbpp;
 869
 870         if (ea >= spt->maxaddr)
 871                 return 0;
 872         if (ea < 0x100000000) {
 873                 /* addresses below 4GB use spt->low_prot */
 874                 sbpm = spt->low_prot;
 875         } else {
 876                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
 877                 if (!sbpm)
 878                         return 0;
 879         }
 880         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
 881         if (!sbpp)
 882                 return 0;
 883         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
 884
 885         /* extract 2-bit bitfield for this 4k subpage */
 886         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
 887
 888         /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
 889         spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
 890         return spp;
 891 }
 892
 893 #else /* CONFIG_PPC_SUBPAGE_PROT */
 894 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
 895 {
 896         return 0;
 897 }
 898 #endif
 899
 900 void hash_failure_debug(unsigned long ea, unsigned long access,
 901                         unsigned long vsid, unsigned long trap,
 902                         int ssize, int psize, unsigned long pte)
 903 {
 904         if (!printk_ratelimit())
 905                 return;
 906         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
 907                 ea, access, current->comm);
 908         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
 909                 trap, vsid, ssize, psize, pte);
 910 }
 911
 912 /* Result code is:
 913  *  0 - handled
 914  *  1 - normal page fault
 915  * -1 - critical hash insertion error
 916  * -2 - access not permitted by subpage protection mechanism
 917  */
 918 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 919 {
 920         pgd_t *pgdir;
 921         unsigned long vsid;
 922         struct mm_struct *mm;
 923         pte_t *ptep;
 924         unsigned hugeshift;
 925         const struct cpumask *tmp;
 926         int rc, user_region = 0, local = 0;
 927         int psize, ssize;
 928
 929         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
 930                 ea, access, trap);
 931
 932         /* Get region & vsid */
 933         switch (REGION_ID(ea)) {
 934         case USER_REGION_ID:
 935                 user_region = 1;
 936                 mm = current->mm;
 937                 if (! mm) {
 938                         DBG_LOW(" user region with no mm !\n");
 939                         return 1;
 940                 }
 941                 psize = get_slice_psize(mm, ea);
 942                 ssize = user_segment_size(ea);
 943                 vsid = get_vsid(mm->context.id, ea, ssize);
 944                 break;
 945         case VMALLOC_REGION_ID:
 946                 mm = &init_mm;
 947                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
 948                 if (ea < VMALLOC_END)
 949                         psize = mmu_vmalloc_psize;
 950                 else
 951                         psize = mmu_io_psize;
 952                 ssize = mmu_kernel_ssize;
 953                 break;
 954         default:
 955                 /* Not a valid range
 956                  * Send the problem up to do_page_fault
 957                  */
 958                 return 1;
 959         }
 960         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
 961
 962         /* Bad address. */
 963         if (!vsid) {
 964                 DBG_LOW("Bad address!\n");
 965                 return 1;
 966         }
 967         /* Get pgdir */
 968         pgdir = mm->pgd;
 969         if (pgdir == NULL)
 970                 return 1;
 971
 972         /* Check CPU locality */
 973         tmp = cpumask_of(smp_processor_id());
 974         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
 975                 local = 1;
 976
 977 #ifndef CONFIG_PPC_64K_PAGES
 978         /* If we use 4K pages and our psize is not 4K, then we might
 979          * be hitting a special driver mapping, and need to align the
 980          * address before we fetch the PTE.
 981          *
 982          * It could also be a hugepage mapping, in which case this is
 983          * not necessary, but it's not harmful, either.
 984          */
 985         if (psize != MMU_PAGE_4K)
 986                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
 987 #endif /* CONFIG_PPC_64K_PAGES */
 988
 989         /* Get PTE and page size from page tables */
 990         ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
 991         if (ptep == NULL || !pte_present(*ptep)) {
 992                 DBG_LOW(" no PTE !\n");
 993                 return 1;
 994         }
 995
 996         /* Add _PAGE_PRESENT to the required access perm */
 997         access |= _PAGE_PRESENT;
 998
 999         /* Pre-check access permissions (will be re-checked atomically
1000          * in __hash_page_XX but this pre-check is a fast path
1001          */
1002         if (access & ~pte_val(*ptep)) {
1003                 DBG_LOW(" no access !\n");
1004                 return 1;
1005         }
1006
1007 #ifdef CONFIG_HUGETLB_PAGE
1008         if (hugeshift)
1009                 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
1010                                         ssize, hugeshift, psize);
1011 #endif /* CONFIG_HUGETLB_PAGE */
1012
1013 #ifndef CONFIG_PPC_64K_PAGES
1014         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1015 #else
1016         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1017                 pte_val(*(ptep + PTRS_PER_PTE)));
1018 #endif
1019         /* Do actual hashing */
1020 #ifdef CONFIG_PPC_64K_PAGES
1021         /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1022         if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1023                 demote_segment_4k(mm, ea);
1024                 psize = MMU_PAGE_4K;
1025         }
1026
1027         /* If this PTE is non-cacheable and we have restrictions on
1028          * using non cacheable large pages, then we switch to 4k
1029          */
1030         if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1031             (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1032                 if (user_region) {
1033                         demote_segment_4k(mm, ea);
1034                         psize = MMU_PAGE_4K;
1035                 } else if (ea < VMALLOC_END) {
1036                         /*
1037                          * some driver did a non-cacheable mapping
1038                          * in vmalloc space, so switch vmalloc
1039                          * to 4k pages
1040                          */
1041                         printk(KERN_ALERT "Reducing vmalloc segment "
1042                                "to 4kB pages because of "
1043                                "non-cacheable mapping\n");
1044                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1045 #ifdef CONFIG_SPU_BASE
1046                         spu_flush_all_slbs(mm);
1047 #endif
1048                 }
1049         }
1050         if (user_region) {
1051                 if (psize != get_paca_psize(ea)) {
1052                         get_paca()->context = mm->context;
1053                         slb_flush_and_rebolt();
1054                 }
1055         } else if (get_paca()->vmalloc_sllp !=
1056                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1057                 get_paca()->vmalloc_sllp =
1058                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1059                 slb_vmalloc_update();
1060         }
1061 #endif /* CONFIG_PPC_64K_PAGES */
1062
1063 #ifdef CONFIG_PPC_HAS_HASH_64K
1064         if (psize == MMU_PAGE_64K)
1065                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1066         else
1067 #endif /* CONFIG_PPC_HAS_HASH_64K */
1068         {
1069                 int spp = subpage_protection(mm, ea);
1070                 if (access & spp)
1071                         rc = -2;
1072                 else
1073                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1074                                             local, ssize, spp);
1075         }
1076
1077         /* Dump some info in case of hash insertion failure, they should
1078          * never happen so it is really useful to know if/when they do
1079          */
1080         if (rc == -1)
1081                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1082                                    pte_val(*ptep));
1083 #ifndef CONFIG_PPC_64K_PAGES
1084         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1085 #else
1086         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1087                 pte_val(*(ptep + PTRS_PER_PTE)));
1088 #endif
1089         DBG_LOW(" -> rc=%d\n", rc);
1090         return rc;
1091 }
1092 EXPORT_SYMBOL_GPL(hash_page);
1093
1094 void hash_preload(struct mm_struct *mm, unsigned long ea,
1095                   unsigned long access, unsigned long trap)
1096 {
1097         unsigned long vsid;
1098         pgd_t *pgdir;
1099         pte_t *ptep;
1100         unsigned long flags;
1101         int rc, ssize, local = 0;
1102
1103         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1104
1105 #ifdef CONFIG_PPC_MM_SLICES
1106         /* We only prefault standard pages for now */
1107         if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1108                 return;
1109 #endif
1110
1111         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1112                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1113
1114         /* Get Linux PTE if available */
1115         pgdir = mm->pgd;
1116         if (pgdir == NULL)
1117                 return;
1118         ptep = find_linux_pte(pgdir, ea);
1119         if (!ptep)
1120                 return;
1121
1122 #ifdef CONFIG_PPC_64K_PAGES
1123         /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1124          * a 64K kernel), then we don't preload, hash_page() will take
1125          * care of it once we actually try to access the page.
1126          * That way we don't have to duplicate all of the logic for segment
1127          * page size demotion here
1128          */
1129         if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1130                 return;
1131 #endif /* CONFIG_PPC_64K_PAGES */
1132
1133         /* Get VSID */
1134         ssize = user_segment_size(ea);
1135         vsid = get_vsid(mm->context.id, ea, ssize);
1136         if (!vsid)
1137                 return;
1138
1139         /* Hash doesn't like irqs */
1140         local_irq_save(flags);
1141
1142         /* Is that local to this CPU ? */
1143         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1144                 local = 1;
1145
1146         /* Hash it in */
1147 #ifdef CONFIG_PPC_HAS_HASH_64K
1148         if (mm->context.user_psize == MMU_PAGE_64K)
1149                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1150         else
1151 #endif /* CONFIG_PPC_HAS_HASH_64K */
1152                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1153                                     subpage_protection(mm, ea));
1154
1155         /* Dump some info in case of hash insertion failure, they should
1156          * never happen so it is really useful to know if/when they do
1157          */
1158         if (rc == -1)
1159                 hash_failure_debug(ea, access, vsid, trap, ssize,
1160                                    mm->context.user_psize, pte_val(*ptep));
1161
1162         local_irq_restore(flags);
1163 }
1164
1165 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1166  *          do not forget to update the assembly call site !
1167  */
1168 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1169                      int local)
1170 {
1171         unsigned long hash, index, shift, hidx, slot;
1172
1173         DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1174         pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1175                 hash = hpt_hash(vpn, shift, ssize);
1176                 hidx = __rpte_to_hidx(pte, index);
1177                 if (hidx & _PTEIDX_SECONDARY)
1178                         hash = ~hash;
1179                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1180                 slot += hidx & _PTEIDX_GROUP_IX;
1181                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1182                 ppc_md.hpte_invalidate(slot, vpn, psize, ssize, local);
1183         } pte_iterate_hashed_end();
1184
1185 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1186         /* Transactions are not aborted by tlbiel, only tlbie.
1187          * Without, syncing a page back to a block device w/ PIO could pick up
1188          * transactional data (bad!) so we force an abort here.  Before the
1189          * sync the page will be made read-only, which will flush_hash_page.
1190          * BIG ISSUE here: if the kernel uses a page from userspace without
1191          * unmapping it first, it may see the speculated version.
1192          */
1193         if (local && cpu_has_feature(CPU_FTR_TM) &&
1194             MSR_TM_ACTIVE(current->thread.regs->msr)) {
1195                 tm_enable();
1196                 tm_abort(TM_CAUSE_TLBI);
1197         }
1198 #endif
1199 }
1200
1201 void flush_hash_range(unsigned long number, int local)
1202 {
1203         if (ppc_md.flush_hash_range)
1204                 ppc_md.flush_hash_range(number, local);
1205         else {
1206                 int i;
1207                 struct ppc64_tlb_batch *batch =
1208                         &__get_cpu_var(ppc64_tlb_batch);
1209
1210                 for (i = 0; i < number; i++)
1211                         flush_hash_page(batch->vpn[i], batch->pte[i],
1212                                         batch->psize, batch->ssize, local);
1213         }
1214 }
1215
1216 /*
1217  * low_hash_fault is called when we the low level hash code failed
1218  * to instert a PTE due to an hypervisor error
1219  */
1220 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1221 {
1222         if (user_mode(regs)) {
1223 #ifdef CONFIG_PPC_SUBPAGE_PROT
1224                 if (rc == -2)
1225                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1226                 else
1227 #endif
1228                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1229         } else
1230                 bad_page_fault(regs, address, SIGBUS);
1231 }
1232
1233 #ifdef CONFIG_DEBUG_PAGEALLOC
1234 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1235 {
1236         unsigned long hash, hpteg;
1237         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1238         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1239         unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1240         int ret;
1241
1242         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1243         hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1244
1245         /* Don't create HPTE entries for bad address */
1246         if (!vsid)
1247                 return;
1248         ret = ppc_md.hpte_insert(hpteg, vpn, __pa(vaddr),
1249                                  mode, HPTE_V_BOLTED,
1250                                  mmu_linear_psize, mmu_kernel_ssize);
1251         BUG_ON (ret < 0);
1252         spin_lock(&linear_map_hash_lock);
1253         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1254         linear_map_hash_slots[lmi] = ret | 0x80;
1255         spin_unlock(&linear_map_hash_lock);
1256 }
1257
1258 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1259 {
1260         unsigned long hash, hidx, slot;
1261         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1262         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1263
1264         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1265         spin_lock(&linear_map_hash_lock);
1266         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1267         hidx = linear_map_hash_slots[lmi] & 0x7f;
1268         linear_map_hash_slots[lmi] = 0;
1269         spin_unlock(&linear_map_hash_lock);
1270         if (hidx & _PTEIDX_SECONDARY)
1271                 hash = ~hash;
1272         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1273         slot += hidx & _PTEIDX_GROUP_IX;
1274         ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_kernel_ssize, 0);
1275 }
1276
1277 void kernel_map_pages(struct page *page, int numpages, int enable)
1278 {
1279         unsigned long flags, vaddr, lmi;
1280         int i;
1281
1282         local_irq_save(flags);
1283         for (i = 0; i < numpages; i++, page++) {
1284                 vaddr = (unsigned long)page_address(page);
1285                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1286                 if (lmi >= linear_map_hash_count)
1287                         continue;
1288                 if (enable)
1289                         kernel_map_linear_page(vaddr, lmi);
1290                 else
1291                         kernel_unmap_linear_page(vaddr, lmi);
1292         }
1293         local_irq_restore(flags);
1294 }
1295 #endif /* CONFIG_DEBUG_PAGEALLOC */
1296
1297 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1298                                 phys_addr_t first_memblock_size)
1299 {
1300         /* We don't currently support the first MEMBLOCK not mapping 0
1301          * physical on those processors
1302          */
1303         BUG_ON(first_memblock_base != 0);
1304
1305         /* On LPAR systems, the first entry is our RMA region,
1306          * non-LPAR 64-bit hash MMU systems don't have a limitation
1307          * on real mode access, but using the first entry works well
1308          * enough. We also clamp it to 1G to avoid some funky things
1309          * such as RTAS bugs etc...
1310          */
1311         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1312
1313         /* Finally limit subsequent allocations */
1314         memblock_set_current_limit(ppc64_rma_size);
1315 }