arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  56 #define POWERNV_IOMMU_MAX_LEVELS        5
  57
  58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
  59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  60
  61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  62                             const char *fmt, ...)
  63 {
  64         struct va_format vaf;
  65         va_list args;
  66         char pfix[32];
  67
  68         va_start(args, fmt);
  69
  70         vaf.fmt = fmt;
  71         vaf.va = &args;
  72
  73         if (pe->flags & PNV_IODA_PE_DEV)
  74                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  75         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  76                 sprintf(pfix, "%04x:%02x     ",
  77                         pci_domain_nr(pe->pbus), pe->pbus->number);
  78 #ifdef CONFIG_PCI_IOV
  79         else if (pe->flags & PNV_IODA_PE_VF)
  80                 sprintf(pfix, "%04x:%02x:%2x.%d",
  81                         pci_domain_nr(pe->parent_dev->bus),
  82                         (pe->rid & 0xff00) >> 8,
  83                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  84 #endif /* CONFIG_PCI_IOV*/
  85
  86         printk("%spci %s: [PE# %.3d] %pV",
  87                level, pfix, pe->pe_number, &vaf);
  88
  89         va_end(args);
  90 }
  91
  92 static bool pnv_iommu_bypass_disabled __read_mostly;
  93
  94 static int __init iommu_setup(char *str)
  95 {
  96         if (!str)
  97                 return -EINVAL;
  98
  99         while (*str) {
 100                 if (!strncmp(str, "nobypass", 8)) {
 101                         pnv_iommu_bypass_disabled = true;
 102                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 103                         break;
 104                 }
 105                 str += strcspn(str, ",");
 106                 if (*str == ',')
 107                         str++;
 108         }
 109
 110         return 0;
 111 }
 112 early_param("iommu", iommu_setup);
 113
 114 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 115 {
 116         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 117                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 118 }
 119
 120 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 121 {
 122         phb->ioda.pe_array[pe_no].phb = phb;
 123         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 124
 125         return &phb->ioda.pe_array[pe_no];
 126 }
 127
 128 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 129 {
 130         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 131                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 132                         __func__, pe_no, phb->hose->global_number);
 133                 return;
 134         }
 135
 136         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 137                 pr_debug("%s: PE %d was reserved on PHB#%x\n",
 138                          __func__, pe_no, phb->hose->global_number);
 139
 140         pnv_ioda_init_pe(phb, pe_no);
 141 }
 142
 143 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 144 {
 145         unsigned long pe = phb->ioda.total_pe_num - 1;
 146
 147         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 148                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 149                         return pnv_ioda_init_pe(phb, pe);
 150         }
 151
 152         return NULL;
 153 }
 154
 155 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 156 {
 157         struct pnv_phb *phb = pe->phb;
 158
 159         WARN_ON(pe->pdev);
 160
 161         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 162         clear_bit(pe->pe_number, phb->ioda.pe_alloc);
 163 }
 164
 165 /* The default M64 BAR is shared by all PEs */
 166 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 167 {
 168         const char *desc;
 169         struct resource *r;
 170         s64 rc;
 171
 172         /* Configure the default M64 BAR */
 173         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 174                                          OPAL_M64_WINDOW_TYPE,
 175                                          phb->ioda.m64_bar_idx,
 176                                          phb->ioda.m64_base,
 177                                          0, /* unused */
 178                                          phb->ioda.m64_size);
 179         if (rc != OPAL_SUCCESS) {
 180                 desc = "configuring";
 181                 goto fail;
 182         }
 183
 184         /* Enable the default M64 BAR */
 185         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 186                                       OPAL_M64_WINDOW_TYPE,
 187                                       phb->ioda.m64_bar_idx,
 188                                       OPAL_ENABLE_M64_SPLIT);
 189         if (rc != OPAL_SUCCESS) {
 190                 desc = "enabling";
 191                 goto fail;
 192         }
 193
 194         /* Mark the M64 BAR assigned */
 195         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 196
 197         /*
 198          * Exclude the segments for reserved and root bus PE, which
 199          * are first or last two PEs.
 200          */
 201         r = &phb->hose->mem_resources[1];
 202         if (phb->ioda.reserved_pe_idx == 0)
 203                 r->start += (2 * phb->ioda.m64_segsize);
 204         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 205                 r->end -= (2 * phb->ioda.m64_segsize);
 206         else
 207                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 208                         phb->ioda.reserved_pe_idx);
 209
 210         return 0;
 211
 212 fail:
 213         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 214                 rc, desc, phb->ioda.m64_bar_idx);
 215         opal_pci_phb_mmio_enable(phb->opal_id,
 216                                  OPAL_M64_WINDOW_TYPE,
 217                                  phb->ioda.m64_bar_idx,
 218                                  OPAL_DISABLE_M64);
 219         return -EIO;
 220 }
 221
 222 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 223                                          unsigned long *pe_bitmap)
 224 {
 225         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 226         struct pnv_phb *phb = hose->private_data;
 227         struct resource *r;
 228         resource_size_t base, sgsz, start, end;
 229         int segno, i;
 230
 231         base = phb->ioda.m64_base;
 232         sgsz = phb->ioda.m64_segsize;
 233         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 234                 r = &pdev->resource[i];
 235                 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
 236                         continue;
 237
 238                 start = _ALIGN_DOWN(r->start - base, sgsz);
 239                 end = _ALIGN_UP(r->end - base, sgsz);
 240                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 241                         if (pe_bitmap)
 242                                 set_bit(segno, pe_bitmap);
 243                         else
 244                                 pnv_ioda_reserve_pe(phb, segno);
 245                 }
 246         }
 247 }
 248
 249 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 250 {
 251         struct resource *r;
 252         int index;
 253
 254         /*
 255          * There are 16 M64 BARs, each of which has 8 segments. So
 256          * there are as many M64 segments as the maximum number of
 257          * PEs, which is 128.
 258          */
 259         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 260                 unsigned long base, segsz = phb->ioda.m64_segsize;
 261                 int64_t rc;
 262
 263                 base = phb->ioda.m64_base +
 264                        index * PNV_IODA1_M64_SEGS * segsz;
 265                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 266                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 267                                 PNV_IODA1_M64_SEGS * segsz);
 268                 if (rc != OPAL_SUCCESS) {
 269                         pr_warn("  Error %lld setting M64 PHB#%d-BAR#%d\n",
 270                                 rc, phb->hose->global_number, index);
 271                         goto fail;
 272                 }
 273
 274                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 275                                 OPAL_M64_WINDOW_TYPE, index,
 276                                 OPAL_ENABLE_M64_SPLIT);
 277                 if (rc != OPAL_SUCCESS) {
 278                         pr_warn("  Error %lld enabling M64 PHB#%d-BAR#%d\n",
 279                                 rc, phb->hose->global_number, index);
 280                         goto fail;
 281                 }
 282         }
 283
 284         /*
 285          * Exclude the segments for reserved and root bus PE, which
 286          * are first or last two PEs.
 287          */
 288         r = &phb->hose->mem_resources[1];
 289         if (phb->ioda.reserved_pe_idx == 0)
 290                 r->start += (2 * phb->ioda.m64_segsize);
 291         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 292                 r->end -= (2 * phb->ioda.m64_segsize);
 293         else
 294                 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
 295                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 296
 297         return 0;
 298
 299 fail:
 300         for ( ; index >= 0; index--)
 301                 opal_pci_phb_mmio_enable(phb->opal_id,
 302                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 303
 304         return -EIO;
 305 }
 306
 307 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 308                                     unsigned long *pe_bitmap,
 309                                     bool all)
 310 {
 311         struct pci_dev *pdev;
 312
 313         list_for_each_entry(pdev, &bus->devices, bus_list) {
 314                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 315
 316                 if (all && pdev->subordinate)
 317                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 318                                                 pe_bitmap, all);
 319         }
 320 }
 321
 322 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 323 {
 324         struct pci_controller *hose = pci_bus_to_host(bus);
 325         struct pnv_phb *phb = hose->private_data;
 326         struct pnv_ioda_pe *master_pe, *pe;
 327         unsigned long size, *pe_alloc;
 328         int i;
 329
 330         /* Root bus shouldn't use M64 */
 331         if (pci_is_root_bus(bus))
 332                 return NULL;
 333
 334         /* Allocate bitmap */
 335         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 336         pe_alloc = kzalloc(size, GFP_KERNEL);
 337         if (!pe_alloc) {
 338                 pr_warn("%s: Out of memory !\n",
 339                         __func__);
 340                 return NULL;
 341         }
 342
 343         /* Figure out reserved PE numbers by the PE */
 344         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 345
 346         /*
 347          * the current bus might not own M64 window and that's all
 348          * contributed by its child buses. For the case, we needn't
 349          * pick M64 dependent PE#.
 350          */
 351         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 352                 kfree(pe_alloc);
 353                 return NULL;
 354         }
 355
 356         /*
 357          * Figure out the master PE and put all slave PEs to master
 358          * PE's list to form compound PE.
 359          */
 360         master_pe = NULL;
 361         i = -1;
 362         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 363                 phb->ioda.total_pe_num) {
 364                 pe = &phb->ioda.pe_array[i];
 365
 366                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 367                 if (!master_pe) {
 368                         pe->flags |= PNV_IODA_PE_MASTER;
 369                         INIT_LIST_HEAD(&pe->slaves);
 370                         master_pe = pe;
 371                 } else {
 372                         pe->flags |= PNV_IODA_PE_SLAVE;
 373                         pe->master = master_pe;
 374                         list_add_tail(&pe->list, &master_pe->slaves);
 375                 }
 376
 377                 /*
 378                  * P7IOC supports M64DT, which helps mapping M64 segment
 379                  * to one particular PE#. However, PHB3 has fixed mapping
 380                  * between M64 segment and PE#. In order to have same logic
 381                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 382                  * segment and PE# on P7IOC.
 383                  */
 384                 if (phb->type == PNV_PHB_IODA1) {
 385                         int64_t rc;
 386
 387                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 388                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 389                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 390                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 391                         if (rc != OPAL_SUCCESS)
 392                                 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
 393                                         __func__, rc, phb->hose->global_number,
 394                                         pe->pe_number);
 395                 }
 396         }
 397
 398         kfree(pe_alloc);
 399         return master_pe;
 400 }
 401
 402 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 403 {
 404         struct pci_controller *hose = phb->hose;
 405         struct device_node *dn = hose->dn;
 406         struct resource *res;
 407         const u32 *r;
 408         u64 pci_addr;
 409
 410         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 411                 pr_info("  Not support M64 window\n");
 412                 return;
 413         }
 414
 415         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 416                 pr_info("  Firmware too old to support M64 window\n");
 417                 return;
 418         }
 419
 420         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 421         if (!r) {
 422                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 423                         dn->full_name);
 424                 return;
 425         }
 426
 427         res = &hose->mem_resources[1];
 428         res->name = dn->full_name;
 429         res->start = of_translate_address(dn, r + 2);
 430         res->end = res->start + of_read_number(r + 4, 2) - 1;
 431         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 432         pci_addr = of_read_number(r, 2);
 433         hose->mem_offset[1] = res->start - pci_addr;
 434
 435         phb->ioda.m64_size = resource_size(res);
 436         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 437         phb->ioda.m64_base = pci_addr;
 438
 439         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 440                         res->start, res->end, pci_addr);
 441
 442         /* Use last M64 BAR to cover M64 window */
 443         phb->ioda.m64_bar_idx = 15;
 444         if (phb->type == PNV_PHB_IODA1)
 445                 phb->init_m64 = pnv_ioda1_init_m64;
 446         else
 447                 phb->init_m64 = pnv_ioda2_init_m64;
 448         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 449         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 450 }
 451
 452 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 453 {
 454         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 455         struct pnv_ioda_pe *slave;
 456         s64 rc;
 457
 458         /* Fetch master PE */
 459         if (pe->flags & PNV_IODA_PE_SLAVE) {
 460                 pe = pe->master;
 461                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 462                         return;
 463
 464                 pe_no = pe->pe_number;
 465         }
 466
 467         /* Freeze master PE */
 468         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 469                                      pe_no,
 470                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 471         if (rc != OPAL_SUCCESS) {
 472                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 473                         __func__, rc, phb->hose->global_number, pe_no);
 474                 return;
 475         }
 476
 477         /* Freeze slave PEs */
 478         if (!(pe->flags & PNV_IODA_PE_MASTER))
 479                 return;
 480
 481         list_for_each_entry(slave, &pe->slaves, list) {
 482                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 483                                              slave->pe_number,
 484                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 485                 if (rc != OPAL_SUCCESS)
 486                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 487                                 __func__, rc, phb->hose->global_number,
 488                                 slave->pe_number);
 489         }
 490 }
 491
 492 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 493 {
 494         struct pnv_ioda_pe *pe, *slave;
 495         s64 rc;
 496
 497         /* Find master PE */
 498         pe = &phb->ioda.pe_array[pe_no];
 499         if (pe->flags & PNV_IODA_PE_SLAVE) {
 500                 pe = pe->master;
 501                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 502                 pe_no = pe->pe_number;
 503         }
 504
 505         /* Clear frozen state for master PE */
 506         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 507         if (rc != OPAL_SUCCESS) {
 508                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 509                         __func__, rc, opt, phb->hose->global_number, pe_no);
 510                 return -EIO;
 511         }
 512
 513         if (!(pe->flags & PNV_IODA_PE_MASTER))
 514                 return 0;
 515
 516         /* Clear frozen state for slave PEs */
 517         list_for_each_entry(slave, &pe->slaves, list) {
 518                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 519                                              slave->pe_number,
 520                                              opt);
 521                 if (rc != OPAL_SUCCESS) {
 522                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 523                                 __func__, rc, opt, phb->hose->global_number,
 524                                 slave->pe_number);
 525                         return -EIO;
 526                 }
 527         }
 528
 529         return 0;
 530 }
 531
 532 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 533 {
 534         struct pnv_ioda_pe *slave, *pe;
 535         u8 fstate, state;
 536         __be16 pcierr;
 537         s64 rc;
 538
 539         /* Sanity check on PE number */
 540         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 541                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 542
 543         /*
 544          * Fetch the master PE and the PE instance might be
 545          * not initialized yet.
 546          */
 547         pe = &phb->ioda.pe_array[pe_no];
 548         if (pe->flags & PNV_IODA_PE_SLAVE) {
 549                 pe = pe->master;
 550                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 551                 pe_no = pe->pe_number;
 552         }
 553
 554         /* Check the master PE */
 555         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 556                                         &state, &pcierr, NULL);
 557         if (rc != OPAL_SUCCESS) {
 558                 pr_warn("%s: Failure %lld getting "
 559                         "PHB#%x-PE#%x state\n",
 560                         __func__, rc,
 561                         phb->hose->global_number, pe_no);
 562                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 563         }
 564
 565         /* Check the slave PE */
 566         if (!(pe->flags & PNV_IODA_PE_MASTER))
 567                 return state;
 568
 569         list_for_each_entry(slave, &pe->slaves, list) {
 570                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 571                                                 slave->pe_number,
 572                                                 &fstate,
 573                                                 &pcierr,
 574                                                 NULL);
 575                 if (rc != OPAL_SUCCESS) {
 576                         pr_warn("%s: Failure %lld getting "
 577                                 "PHB#%x-PE#%x state\n",
 578                                 __func__, rc,
 579                                 phb->hose->global_number, slave->pe_number);
 580                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 581                 }
 582
 583                 /*
 584                  * Override the result based on the ascending
 585                  * priority.
 586                  */
 587                 if (fstate > state)
 588                         state = fstate;
 589         }
 590
 591         return state;
 592 }
 593
 594 /* Currently those 2 are only used when MSIs are enabled, this will change
 595  * but in the meantime, we need to protect them to avoid warnings
 596  */
 597 #ifdef CONFIG_PCI_MSI
 598 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 599 {
 600         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 601         struct pnv_phb *phb = hose->private_data;
 602         struct pci_dn *pdn = pci_get_pdn(dev);
 603
 604         if (!pdn)
 605                 return NULL;
 606         if (pdn->pe_number == IODA_INVALID_PE)
 607                 return NULL;
 608         return &phb->ioda.pe_array[pdn->pe_number];
 609 }
 610 #endif /* CONFIG_PCI_MSI */
 611
 612 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 613                                   struct pnv_ioda_pe *parent,
 614                                   struct pnv_ioda_pe *child,
 615                                   bool is_add)
 616 {
 617         const char *desc = is_add ? "adding" : "removing";
 618         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 619                               OPAL_REMOVE_PE_FROM_DOMAIN;
 620         struct pnv_ioda_pe *slave;
 621         long rc;
 622
 623         /* Parent PE affects child PE */
 624         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 625                                 child->pe_number, op);
 626         if (rc != OPAL_SUCCESS) {
 627                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 628                         rc, desc);
 629                 return -ENXIO;
 630         }
 631
 632         if (!(child->flags & PNV_IODA_PE_MASTER))
 633                 return 0;
 634
 635         /* Compound case: parent PE affects slave PEs */
 636         list_for_each_entry(slave, &child->slaves, list) {
 637                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 638                                         slave->pe_number, op);
 639                 if (rc != OPAL_SUCCESS) {
 640                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 641                                 rc, desc);
 642                         return -ENXIO;
 643                 }
 644         }
 645
 646         return 0;
 647 }
 648
 649 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 650                               struct pnv_ioda_pe *pe,
 651                               bool is_add)
 652 {
 653         struct pnv_ioda_pe *slave;
 654         struct pci_dev *pdev = NULL;
 655         int ret;
 656
 657         /*
 658          * Clear PE frozen state. If it's master PE, we need
 659          * clear slave PE frozen state as well.
 660          */
 661         if (is_add) {
 662                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 663                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 664                 if (pe->flags & PNV_IODA_PE_MASTER) {
 665                         list_for_each_entry(slave, &pe->slaves, list)
 666                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 667                                                           slave->pe_number,
 668                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 669                 }
 670         }
 671
 672         /*
 673          * Associate PE in PELT. We need add the PE into the
 674          * corresponding PELT-V as well. Otherwise, the error
 675          * originated from the PE might contribute to other
 676          * PEs.
 677          */
 678         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 679         if (ret)
 680                 return ret;
 681
 682         /* For compound PEs, any one affects all of them */
 683         if (pe->flags & PNV_IODA_PE_MASTER) {
 684                 list_for_each_entry(slave, &pe->slaves, list) {
 685                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 686                         if (ret)
 687                                 return ret;
 688                 }
 689         }
 690
 691         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 692                 pdev = pe->pbus->self;
 693         else if (pe->flags & PNV_IODA_PE_DEV)
 694                 pdev = pe->pdev->bus->self;
 695 #ifdef CONFIG_PCI_IOV
 696         else if (pe->flags & PNV_IODA_PE_VF)
 697                 pdev = pe->parent_dev;
 698 #endif /* CONFIG_PCI_IOV */
 699         while (pdev) {
 700                 struct pci_dn *pdn = pci_get_pdn(pdev);
 701                 struct pnv_ioda_pe *parent;
 702
 703                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 704                         parent = &phb->ioda.pe_array[pdn->pe_number];
 705                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 706                         if (ret)
 707                                 return ret;
 708                 }
 709
 710                 pdev = pdev->bus->self;
 711         }
 712
 713         return 0;
 714 }
 715
 716 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 717 {
 718         struct pci_dev *parent;
 719         uint8_t bcomp, dcomp, fcomp;
 720         int64_t rc;
 721         long rid_end, rid;
 722
 723         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 724         if (pe->pbus) {
 725                 int count;
 726
 727                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 728                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 729                 parent = pe->pbus->self;
 730                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 731                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 732                 else
 733                         count = 1;
 734
 735                 switch(count) {
 736                 case  1: bcomp = OpalPciBusAll;         break;
 737                 case  2: bcomp = OpalPciBus7Bits;       break;
 738                 case  4: bcomp = OpalPciBus6Bits;       break;
 739                 case  8: bcomp = OpalPciBus5Bits;       break;
 740                 case 16: bcomp = OpalPciBus4Bits;       break;
 741                 case 32: bcomp = OpalPciBus3Bits;       break;
 742                 default:
 743                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 744                                 count);
 745                         /* Do an exact match only */
 746                         bcomp = OpalPciBusAll;
 747                 }
 748                 rid_end = pe->rid + (count << 8);
 749         } else {
 750 #ifdef CONFIG_PCI_IOV
 751                 if (pe->flags & PNV_IODA_PE_VF)
 752                         parent = pe->parent_dev;
 753                 else
 754 #endif
 755                         parent = pe->pdev->bus->self;
 756                 bcomp = OpalPciBusAll;
 757                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 758                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 759                 rid_end = pe->rid + 1;
 760         }
 761
 762         /* Clear the reverse map */
 763         for (rid = pe->rid; rid < rid_end; rid++)
 764                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 765
 766         /* Release from all parents PELT-V */
 767         while (parent) {
 768                 struct pci_dn *pdn = pci_get_pdn(parent);
 769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 770                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 771                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 772                         /* XXX What to do in case of error ? */
 773                 }
 774                 parent = parent->bus->self;
 775         }
 776
 777         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 778                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 779
 780         /* Disassociate PE in PELT */
 781         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 782                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 783         if (rc)
 784                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 785         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 786                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 787         if (rc)
 788                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 789
 790         pe->pbus = NULL;
 791         pe->pdev = NULL;
 792 #ifdef CONFIG_PCI_IOV
 793         pe->parent_dev = NULL;
 794 #endif
 795
 796         return 0;
 797 }
 798
 799 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 800 {
 801         struct pci_dev *parent;
 802         uint8_t bcomp, dcomp, fcomp;
 803         long rc, rid_end, rid;
 804
 805         /* Bus validation ? */
 806         if (pe->pbus) {
 807                 int count;
 808
 809                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 810                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 811                 parent = pe->pbus->self;
 812                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 813                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 814                 else
 815                         count = 1;
 816
 817                 switch(count) {
 818                 case  1: bcomp = OpalPciBusAll;         break;
 819                 case  2: bcomp = OpalPciBus7Bits;       break;
 820                 case  4: bcomp = OpalPciBus6Bits;       break;
 821                 case  8: bcomp = OpalPciBus5Bits;       break;
 822                 case 16: bcomp = OpalPciBus4Bits;       break;
 823                 case 32: bcomp = OpalPciBus3Bits;       break;
 824                 default:
 825                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 826                                 count);
 827                         /* Do an exact match only */
 828                         bcomp = OpalPciBusAll;
 829                 }
 830                 rid_end = pe->rid + (count << 8);
 831         } else {
 832 #ifdef CONFIG_PCI_IOV
 833                 if (pe->flags & PNV_IODA_PE_VF)
 834                         parent = pe->parent_dev;
 835                 else
 836 #endif /* CONFIG_PCI_IOV */
 837                         parent = pe->pdev->bus->self;
 838                 bcomp = OpalPciBusAll;
 839                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 840                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 841                 rid_end = pe->rid + 1;
 842         }
 843
 844         /*
 845          * Associate PE in PELT. We need add the PE into the
 846          * corresponding PELT-V as well. Otherwise, the error
 847          * originated from the PE might contribute to other
 848          * PEs.
 849          */
 850         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 851                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 852         if (rc) {
 853                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 854                 return -ENXIO;
 855         }
 856
 857         /*
 858          * Configure PELTV. NPUs don't have a PELTV table so skip
 859          * configuration on them.
 860          */
 861         if (phb->type != PNV_PHB_NPU)
 862                 pnv_ioda_set_peltv(phb, pe, true);
 863
 864         /* Setup reverse map */
 865         for (rid = pe->rid; rid < rid_end; rid++)
 866                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 867
 868         /* Setup one MVTs on IODA1 */
 869         if (phb->type != PNV_PHB_IODA1) {
 870                 pe->mve_number = 0;
 871                 goto out;
 872         }
 873
 874         pe->mve_number = pe->pe_number;
 875         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 876         if (rc != OPAL_SUCCESS) {
 877                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 878                        rc, pe->mve_number);
 879                 pe->mve_number = -1;
 880         } else {
 881                 rc = opal_pci_set_mve_enable(phb->opal_id,
 882                                              pe->mve_number, OPAL_ENABLE_MVE);
 883                 if (rc) {
 884                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 885                                rc, pe->mve_number);
 886                         pe->mve_number = -1;
 887                 }
 888         }
 889
 890 out:
 891         return 0;
 892 }
 893
 894 #ifdef CONFIG_PCI_IOV
 895 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 896 {
 897         struct pci_dn *pdn = pci_get_pdn(dev);
 898         int i;
 899         struct resource *res, res2;
 900         resource_size_t size;
 901         u16 num_vfs;
 902
 903         if (!dev->is_physfn)
 904                 return -EINVAL;
 905
 906         /*
 907          * "offset" is in VFs.  The M64 windows are sized so that when they
 908          * are segmented, each segment is the same size as the IOV BAR.
 909          * Each segment is in a separate PE, and the high order bits of the
 910          * address are the PE number.  Therefore, each VF's BAR is in a
 911          * separate PE, and changing the IOV BAR start address changes the
 912          * range of PEs the VFs are in.
 913          */
 914         num_vfs = pdn->num_vfs;
 915         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 916                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 917                 if (!res->flags || !res->parent)
 918                         continue;
 919
 920                 /*
 921                  * The actual IOV BAR range is determined by the start address
 922                  * and the actual size for num_vfs VFs BAR.  This check is to
 923                  * make sure that after shifting, the range will not overlap
 924                  * with another device.
 925                  */
 926                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 927                 res2.flags = res->flags;
 928                 res2.start = res->start + (size * offset);
 929                 res2.end = res2.start + (size * num_vfs) - 1;
 930
 931                 if (res2.end > res->end) {
 932                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 933                                 i, &res2, res, num_vfs, offset);
 934                         return -EBUSY;
 935                 }
 936         }
 937
 938         /*
 939          * After doing so, there would be a "hole" in the /proc/iomem when
 940          * offset is a positive value. It looks like the device return some
 941          * mmio back to the system, which actually no one could use it.
 942          */
 943         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 944                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 945                 if (!res->flags || !res->parent)
 946                         continue;
 947
 948                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 949                 res2 = *res;
 950                 res->start += size * offset;
 951
 952                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
 953                          i, &res2, res, (offset > 0) ? "En" : "Dis",
 954                          num_vfs, offset);
 955                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 956         }
 957         return 0;
 958 }
 959 #endif /* CONFIG_PCI_IOV */
 960
 961 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 962 {
 963         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 964         struct pnv_phb *phb = hose->private_data;
 965         struct pci_dn *pdn = pci_get_pdn(dev);
 966         struct pnv_ioda_pe *pe;
 967
 968         if (!pdn) {
 969                 pr_err("%s: Device tree node not associated properly\n",
 970                            pci_name(dev));
 971                 return NULL;
 972         }
 973         if (pdn->pe_number != IODA_INVALID_PE)
 974                 return NULL;
 975
 976         pe = pnv_ioda_alloc_pe(phb);
 977         if (!pe) {
 978                 pr_warning("%s: Not enough PE# available, disabling device\n",
 979                            pci_name(dev));
 980                 return NULL;
 981         }
 982
 983         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 984          * pointer in the PE data structure, both should be destroyed at the
 985          * same time. However, this needs to be looked at more closely again
 986          * once we actually start removing things (Hotplug, SR-IOV, ...)
 987          *
 988          * At some point we want to remove the PDN completely anyways
 989          */
 990         pci_dev_get(dev);
 991         pdn->pcidev = dev;
 992         pdn->pe_number = pe->pe_number;
 993         pe->flags = PNV_IODA_PE_DEV;
 994         pe->pdev = dev;
 995         pe->pbus = NULL;
 996         pe->mve_number = -1;
 997         pe->rid = dev->bus->number << 8 | pdn->devfn;
 998
 999         pe_info(pe, "Associated device to PE\n");
1000
1001         if (pnv_ioda_configure_pe(phb, pe)) {
1002                 /* XXX What do we do here ? */
1003                 pnv_ioda_free_pe(pe);
1004                 pdn->pe_number = IODA_INVALID_PE;
1005                 pe->pdev = NULL;
1006                 pci_dev_put(dev);
1007                 return NULL;
1008         }
1009
1010         /* Put PE to the list */
1011         list_add_tail(&pe->list, &phb->ioda.pe_list);
1012
1013         return pe;
1014 }
1015
1016 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1017 {
1018         struct pci_dev *dev;
1019
1020         list_for_each_entry(dev, &bus->devices, bus_list) {
1021                 struct pci_dn *pdn = pci_get_pdn(dev);
1022
1023                 if (pdn == NULL) {
1024                         pr_warn("%s: No device node associated with device !\n",
1025                                 pci_name(dev));
1026                         continue;
1027                 }
1028
1029                 /*
1030                  * In partial hotplug case, the PCI device might be still
1031                  * associated with the PE and needn't attach it to the PE
1032                  * again.
1033                  */
1034                 if (pdn->pe_number != IODA_INVALID_PE)
1035                         continue;
1036
1037                 pe->device_count++;
1038                 pdn->pcidev = dev;
1039                 pdn->pe_number = pe->pe_number;
1040                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1041                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1042         }
1043 }
1044
1045 /*
1046  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1047  * single PCI bus. Another one that contains the primary PCI bus and its
1048  * subordinate PCI devices and buses. The second type of PE is normally
1049  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1050  */
1051 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1052 {
1053         struct pci_controller *hose = pci_bus_to_host(bus);
1054         struct pnv_phb *phb = hose->private_data;
1055         struct pnv_ioda_pe *pe = NULL;
1056         unsigned int pe_num;
1057
1058         /*
1059          * In partial hotplug case, the PE instance might be still alive.
1060          * We should reuse it instead of allocating a new one.
1061          */
1062         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1063         if (pe_num != IODA_INVALID_PE) {
1064                 pe = &phb->ioda.pe_array[pe_num];
1065                 pnv_ioda_setup_same_PE(bus, pe);
1066                 return NULL;
1067         }
1068
1069         /* PE number for root bus should have been reserved */
1070         if (pci_is_root_bus(bus) &&
1071             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1072                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1073
1074         /* Check if PE is determined by M64 */
1075         if (!pe && phb->pick_m64_pe)
1076                 pe = phb->pick_m64_pe(bus, all);
1077
1078         /* The PE number isn't pinned by M64 */
1079         if (!pe)
1080                 pe = pnv_ioda_alloc_pe(phb);
1081
1082         if (!pe) {
1083                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1084                         __func__, pci_domain_nr(bus), bus->number);
1085                 return NULL;
1086         }
1087
1088         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1089         pe->pbus = bus;
1090         pe->pdev = NULL;
1091         pe->mve_number = -1;
1092         pe->rid = bus->busn_res.start << 8;
1093
1094         if (all)
1095                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1096                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1097         else
1098                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1099                         bus->busn_res.start, pe->pe_number);
1100
1101         if (pnv_ioda_configure_pe(phb, pe)) {
1102                 /* XXX What do we do here ? */
1103                 pnv_ioda_free_pe(pe);
1104                 pe->pbus = NULL;
1105                 return NULL;
1106         }
1107
1108         /* Associate it with all child devices */
1109         pnv_ioda_setup_same_PE(bus, pe);
1110
1111         /* Put PE to the list */
1112         list_add_tail(&pe->list, &phb->ioda.pe_list);
1113
1114         return pe;
1115 }
1116
1117 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1118 {
1119         int pe_num, found_pe = false, rc;
1120         long rid;
1121         struct pnv_ioda_pe *pe;
1122         struct pci_dev *gpu_pdev;
1123         struct pci_dn *npu_pdn;
1124         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1125         struct pnv_phb *phb = hose->private_data;
1126
1127         /*
1128          * Due to a hardware errata PE#0 on the NPU is reserved for
1129          * error handling. This means we only have three PEs remaining
1130          * which need to be assigned to four links, implying some
1131          * links must share PEs.
1132          *
1133          * To achieve this we assign PEs such that NPUs linking the
1134          * same GPU get assigned the same PE.
1135          */
1136         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1137         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1138                 pe = &phb->ioda.pe_array[pe_num];
1139                 if (!pe->pdev)
1140                         continue;
1141
1142                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1143                         /*
1144                          * This device has the same peer GPU so should
1145                          * be assigned the same PE as the existing
1146                          * peer NPU.
1147                          */
1148                         dev_info(&npu_pdev->dev,
1149                                 "Associating to existing PE %d\n", pe_num);
1150                         pci_dev_get(npu_pdev);
1151                         npu_pdn = pci_get_pdn(npu_pdev);
1152                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1153                         npu_pdn->pcidev = npu_pdev;
1154                         npu_pdn->pe_number = pe_num;
1155                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1156
1157                         /* Map the PE to this link */
1158                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1159                                         OpalPciBusAll,
1160                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1161                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1162                                         OPAL_MAP_PE);
1163                         WARN_ON(rc != OPAL_SUCCESS);
1164                         found_pe = true;
1165                         break;
1166                 }
1167         }
1168
1169         if (!found_pe)
1170                 /*
1171                  * Could not find an existing PE so allocate a new
1172                  * one.
1173                  */
1174                 return pnv_ioda_setup_dev_PE(npu_pdev);
1175         else
1176                 return pe;
1177 }
1178
1179 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1180 {
1181         struct pci_dev *pdev;
1182
1183         list_for_each_entry(pdev, &bus->devices, bus_list)
1184                 pnv_ioda_setup_npu_PE(pdev);
1185 }
1186
1187 static void pnv_pci_ioda_setup_PEs(void)
1188 {
1189         struct pci_controller *hose, *tmp;
1190         struct pnv_phb *phb;
1191
1192         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1193                 phb = hose->private_data;
1194                 if (phb->type == PNV_PHB_NPU) {
1195                         /* PE#0 is needed for error reporting */
1196                         pnv_ioda_reserve_pe(phb, 0);
1197                         pnv_ioda_setup_npu_PEs(hose->bus);
1198                 }
1199         }
1200 }
1201
1202 #ifdef CONFIG_PCI_IOV
1203 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1204 {
1205         struct pci_bus        *bus;
1206         struct pci_controller *hose;
1207         struct pnv_phb        *phb;
1208         struct pci_dn         *pdn;
1209         int                    i, j;
1210         int                    m64_bars;
1211
1212         bus = pdev->bus;
1213         hose = pci_bus_to_host(bus);
1214         phb = hose->private_data;
1215         pdn = pci_get_pdn(pdev);
1216
1217         if (pdn->m64_single_mode)
1218                 m64_bars = num_vfs;
1219         else
1220                 m64_bars = 1;
1221
1222         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1223                 for (j = 0; j < m64_bars; j++) {
1224                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1225                                 continue;
1226                         opal_pci_phb_mmio_enable(phb->opal_id,
1227                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1228                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1229                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1230                 }
1231
1232         kfree(pdn->m64_map);
1233         return 0;
1234 }
1235
1236 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1237 {
1238         struct pci_bus        *bus;
1239         struct pci_controller *hose;
1240         struct pnv_phb        *phb;
1241         struct pci_dn         *pdn;
1242         unsigned int           win;
1243         struct resource       *res;
1244         int                    i, j;
1245         int64_t                rc;
1246         int                    total_vfs;
1247         resource_size_t        size, start;
1248         int                    pe_num;
1249         int                    m64_bars;
1250
1251         bus = pdev->bus;
1252         hose = pci_bus_to_host(bus);
1253         phb = hose->private_data;
1254         pdn = pci_get_pdn(pdev);
1255         total_vfs = pci_sriov_get_totalvfs(pdev);
1256
1257         if (pdn->m64_single_mode)
1258                 m64_bars = num_vfs;
1259         else
1260                 m64_bars = 1;
1261
1262         pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1263         if (!pdn->m64_map)
1264                 return -ENOMEM;
1265         /* Initialize the m64_map to IODA_INVALID_M64 */
1266         for (i = 0; i < m64_bars ; i++)
1267                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1268                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1269
1270
1271         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1272                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1273                 if (!res->flags || !res->parent)
1274                         continue;
1275
1276                 for (j = 0; j < m64_bars; j++) {
1277                         do {
1278                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1279                                                 phb->ioda.m64_bar_idx + 1, 0);
1280
1281                                 if (win >= phb->ioda.m64_bar_idx + 1)
1282                                         goto m64_failed;
1283                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1284
1285                         pdn->m64_map[j][i] = win;
1286
1287                         if (pdn->m64_single_mode) {
1288                                 size = pci_iov_resource_size(pdev,
1289                                                         PCI_IOV_RESOURCES + i);
1290                                 start = res->start + size * j;
1291                         } else {
1292                                 size = resource_size(res);
1293                                 start = res->start;
1294                         }
1295
1296                         /* Map the M64 here */
1297                         if (pdn->m64_single_mode) {
1298                                 pe_num = pdn->pe_num_map[j];
1299                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1300                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1301                                                 pdn->m64_map[j][i], 0);
1302                         }
1303
1304                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1305                                                  OPAL_M64_WINDOW_TYPE,
1306                                                  pdn->m64_map[j][i],
1307                                                  start,
1308                                                  0, /* unused */
1309                                                  size);
1310
1311
1312                         if (rc != OPAL_SUCCESS) {
1313                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1314                                         win, rc);
1315                                 goto m64_failed;
1316                         }
1317
1318                         if (pdn->m64_single_mode)
1319                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1320                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1321                         else
1322                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1323                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1324
1325                         if (rc != OPAL_SUCCESS) {
1326                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1327                                         win, rc);
1328                                 goto m64_failed;
1329                         }
1330                 }
1331         }
1332         return 0;
1333
1334 m64_failed:
1335         pnv_pci_vf_release_m64(pdev, num_vfs);
1336         return -EBUSY;
1337 }
1338
1339 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1340                 int num);
1341 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1342
1343 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1344 {
1345         struct iommu_table    *tbl;
1346         int64_t               rc;
1347
1348         tbl = pe->table_group.tables[0];
1349         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1350         if (rc)
1351                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1352
1353         pnv_pci_ioda2_set_bypass(pe, false);
1354         if (pe->table_group.group) {
1355                 iommu_group_put(pe->table_group.group);
1356                 BUG_ON(pe->table_group.group);
1357         }
1358         pnv_pci_ioda2_table_free_pages(tbl);
1359         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1360 }
1361
1362 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1363 {
1364         struct pci_bus        *bus;
1365         struct pci_controller *hose;
1366         struct pnv_phb        *phb;
1367         struct pnv_ioda_pe    *pe, *pe_n;
1368         struct pci_dn         *pdn;
1369
1370         bus = pdev->bus;
1371         hose = pci_bus_to_host(bus);
1372         phb = hose->private_data;
1373         pdn = pci_get_pdn(pdev);
1374
1375         if (!pdev->is_physfn)
1376                 return;
1377
1378         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1379                 if (pe->parent_dev != pdev)
1380                         continue;
1381
1382                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1383
1384                 /* Remove from list */
1385                 mutex_lock(&phb->ioda.pe_list_mutex);
1386                 list_del(&pe->list);
1387                 mutex_unlock(&phb->ioda.pe_list_mutex);
1388
1389                 pnv_ioda_deconfigure_pe(phb, pe);
1390
1391                 pnv_ioda_free_pe(pe);
1392         }
1393 }
1394
1395 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1396 {
1397         struct pci_bus        *bus;
1398         struct pci_controller *hose;
1399         struct pnv_phb        *phb;
1400         struct pnv_ioda_pe    *pe;
1401         struct pci_dn         *pdn;
1402         struct pci_sriov      *iov;
1403         u16                    num_vfs, i;
1404
1405         bus = pdev->bus;
1406         hose = pci_bus_to_host(bus);
1407         phb = hose->private_data;
1408         pdn = pci_get_pdn(pdev);
1409         iov = pdev->sriov;
1410         num_vfs = pdn->num_vfs;
1411
1412         /* Release VF PEs */
1413         pnv_ioda_release_vf_PE(pdev);
1414
1415         if (phb->type == PNV_PHB_IODA2) {
1416                 if (!pdn->m64_single_mode)
1417                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1418
1419                 /* Release M64 windows */
1420                 pnv_pci_vf_release_m64(pdev, num_vfs);
1421
1422                 /* Release PE numbers */
1423                 if (pdn->m64_single_mode) {
1424                         for (i = 0; i < num_vfs; i++) {
1425                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1426                                         continue;
1427
1428                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1429                                 pnv_ioda_free_pe(pe);
1430                         }
1431                 } else
1432                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1433                 /* Releasing pe_num_map */
1434                 kfree(pdn->pe_num_map);
1435         }
1436 }
1437
1438 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1439                                        struct pnv_ioda_pe *pe);
1440 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1441 {
1442         struct pci_bus        *bus;
1443         struct pci_controller *hose;
1444         struct pnv_phb        *phb;
1445         struct pnv_ioda_pe    *pe;
1446         int                    pe_num;
1447         u16                    vf_index;
1448         struct pci_dn         *pdn;
1449
1450         bus = pdev->bus;
1451         hose = pci_bus_to_host(bus);
1452         phb = hose->private_data;
1453         pdn = pci_get_pdn(pdev);
1454
1455         if (!pdev->is_physfn)
1456                 return;
1457
1458         /* Reserve PE for each VF */
1459         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1460                 if (pdn->m64_single_mode)
1461                         pe_num = pdn->pe_num_map[vf_index];
1462                 else
1463                         pe_num = *pdn->pe_num_map + vf_index;
1464
1465                 pe = &phb->ioda.pe_array[pe_num];
1466                 pe->pe_number = pe_num;
1467                 pe->phb = phb;
1468                 pe->flags = PNV_IODA_PE_VF;
1469                 pe->pbus = NULL;
1470                 pe->parent_dev = pdev;
1471                 pe->mve_number = -1;
1472                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1473                            pci_iov_virtfn_devfn(pdev, vf_index);
1474
1475                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1476                         hose->global_number, pdev->bus->number,
1477                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1478                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1479
1480                 if (pnv_ioda_configure_pe(phb, pe)) {
1481                         /* XXX What do we do here ? */
1482                         pnv_ioda_free_pe(pe);
1483                         pe->pdev = NULL;
1484                         continue;
1485                 }
1486
1487                 /* Put PE to the list */
1488                 mutex_lock(&phb->ioda.pe_list_mutex);
1489                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1490                 mutex_unlock(&phb->ioda.pe_list_mutex);
1491
1492                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1493         }
1494 }
1495
1496 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1497 {
1498         struct pci_bus        *bus;
1499         struct pci_controller *hose;
1500         struct pnv_phb        *phb;
1501         struct pnv_ioda_pe    *pe;
1502         struct pci_dn         *pdn;
1503         int                    ret;
1504         u16                    i;
1505
1506         bus = pdev->bus;
1507         hose = pci_bus_to_host(bus);
1508         phb = hose->private_data;
1509         pdn = pci_get_pdn(pdev);
1510
1511         if (phb->type == PNV_PHB_IODA2) {
1512                 if (!pdn->vfs_expanded) {
1513                         dev_info(&pdev->dev, "don't support this SRIOV device"
1514                                 " with non 64bit-prefetchable IOV BAR\n");
1515                         return -ENOSPC;
1516                 }
1517
1518                 /*
1519                  * When M64 BARs functions in Single PE mode, the number of VFs
1520                  * could be enabled must be less than the number of M64 BARs.
1521                  */
1522                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1523                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1524                         return -EBUSY;
1525                 }
1526
1527                 /* Allocating pe_num_map */
1528                 if (pdn->m64_single_mode)
1529                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1530                                         GFP_KERNEL);
1531                 else
1532                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1533
1534                 if (!pdn->pe_num_map)
1535                         return -ENOMEM;
1536
1537                 if (pdn->m64_single_mode)
1538                         for (i = 0; i < num_vfs; i++)
1539                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1540
1541                 /* Calculate available PE for required VFs */
1542                 if (pdn->m64_single_mode) {
1543                         for (i = 0; i < num_vfs; i++) {
1544                                 pe = pnv_ioda_alloc_pe(phb);
1545                                 if (!pe) {
1546                                         ret = -EBUSY;
1547                                         goto m64_failed;
1548                                 }
1549
1550                                 pdn->pe_num_map[i] = pe->pe_number;
1551                         }
1552                 } else {
1553                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1554                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1555                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1556                                 0, num_vfs, 0);
1557                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1558                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1559                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1560                                 kfree(pdn->pe_num_map);
1561                                 return -EBUSY;
1562                         }
1563                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1564                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1565                 }
1566                 pdn->num_vfs = num_vfs;
1567
1568                 /* Assign M64 window accordingly */
1569                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1570                 if (ret) {
1571                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1572                         goto m64_failed;
1573                 }
1574
1575                 /*
1576                  * When using one M64 BAR to map one IOV BAR, we need to shift
1577                  * the IOV BAR according to the PE# allocated to the VFs.
1578                  * Otherwise, the PE# for the VF will conflict with others.
1579                  */
1580                 if (!pdn->m64_single_mode) {
1581                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1582                         if (ret)
1583                                 goto m64_failed;
1584                 }
1585         }
1586
1587         /* Setup VF PEs */
1588         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1589
1590         return 0;
1591
1592 m64_failed:
1593         if (pdn->m64_single_mode) {
1594                 for (i = 0; i < num_vfs; i++) {
1595                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1596                                 continue;
1597
1598                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1599                         pnv_ioda_free_pe(pe);
1600                 }
1601         } else
1602                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1603
1604         /* Releasing pe_num_map */
1605         kfree(pdn->pe_num_map);
1606
1607         return ret;
1608 }
1609
1610 int pcibios_sriov_disable(struct pci_dev *pdev)
1611 {
1612         pnv_pci_sriov_disable(pdev);
1613
1614         /* Release PCI data */
1615         remove_dev_pci_data(pdev);
1616         return 0;
1617 }
1618
1619 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1620 {
1621         /* Allocate PCI data */
1622         add_dev_pci_data(pdev);
1623
1624         return pnv_pci_sriov_enable(pdev, num_vfs);
1625 }
1626 #endif /* CONFIG_PCI_IOV */
1627
1628 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1629 {
1630         struct pci_dn *pdn = pci_get_pdn(pdev);
1631         struct pnv_ioda_pe *pe;
1632
1633         /*
1634          * The function can be called while the PE#
1635          * hasn't been assigned. Do nothing for the
1636          * case.
1637          */
1638         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1639                 return;
1640
1641         pe = &phb->ioda.pe_array[pdn->pe_number];
1642         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1643         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1644         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1645         /*
1646          * Note: iommu_add_device() will fail here as
1647          * for physical PE: the device is already added by now;
1648          * for virtual PE: sysfs entries are not ready yet and
1649          * tce_iommu_bus_notifier will add the device to a group later.
1650          */
1651 }
1652
1653 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1654 {
1655         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1656         struct pnv_phb *phb = hose->private_data;
1657         struct pci_dn *pdn = pci_get_pdn(pdev);
1658         struct pnv_ioda_pe *pe;
1659         uint64_t top;
1660         bool bypass = false;
1661
1662         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1663                 return -ENODEV;;
1664
1665         pe = &phb->ioda.pe_array[pdn->pe_number];
1666         if (pe->tce_bypass_enabled) {
1667                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1668                 bypass = (dma_mask >= top);
1669         }
1670
1671         if (bypass) {
1672                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1673                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1674         } else {
1675                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1676                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1677         }
1678         *pdev->dev.dma_mask = dma_mask;
1679
1680         /* Update peer npu devices */
1681         pnv_npu_try_dma_set_bypass(pdev, bypass);
1682
1683         return 0;
1684 }
1685
1686 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1687 {
1688         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1689         struct pnv_phb *phb = hose->private_data;
1690         struct pci_dn *pdn = pci_get_pdn(pdev);
1691         struct pnv_ioda_pe *pe;
1692         u64 end, mask;
1693
1694         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1695                 return 0;
1696
1697         pe = &phb->ioda.pe_array[pdn->pe_number];
1698         if (!pe->tce_bypass_enabled)
1699                 return __dma_get_required_mask(&pdev->dev);
1700
1701
1702         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1703         mask = 1ULL << (fls64(end) - 1);
1704         mask += mask - 1;
1705
1706         return mask;
1707 }
1708
1709 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1710                                    struct pci_bus *bus)
1711 {
1712         struct pci_dev *dev;
1713
1714         list_for_each_entry(dev, &bus->devices, bus_list) {
1715                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1716                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1717                 iommu_add_device(&dev->dev);
1718
1719                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1720                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1721         }
1722 }
1723
1724 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1725                                                      bool real_mode)
1726 {
1727         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1728                 (phb->regs + 0x210);
1729 }
1730
1731 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1732                 unsigned long index, unsigned long npages, bool rm)
1733 {
1734         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1735                         &tbl->it_group_list, struct iommu_table_group_link,
1736                         next);
1737         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1738                         struct pnv_ioda_pe, table_group);
1739         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1740         unsigned long start, end, inc;
1741
1742         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1743         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1744                         npages - 1);
1745
1746         /* p7ioc-style invalidation, 2 TCEs per write */
1747         start |= (1ull << 63);
1748         end |= (1ull << 63);
1749         inc = 16;
1750         end |= inc - 1; /* round up end to be different than start */
1751
1752         mb(); /* Ensure above stores are visible */
1753         while (start <= end) {
1754                 if (rm)
1755                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1756                 else
1757                         __raw_writeq(cpu_to_be64(start), invalidate);
1758                 start += inc;
1759         }
1760
1761         /*
1762          * The iommu layer will do another mb() for us on build()
1763          * and we don't care on free()
1764          */
1765 }
1766
1767 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1768                 long npages, unsigned long uaddr,
1769                 enum dma_data_direction direction,
1770                 struct dma_attrs *attrs)
1771 {
1772         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1773                         attrs);
1774
1775         if (!ret)
1776                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1777
1778         return ret;
1779 }
1780
1781 #ifdef CONFIG_IOMMU_API
1782 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1783                 unsigned long *hpa, enum dma_data_direction *direction)
1784 {
1785         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1786
1787         if (!ret)
1788                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1789
1790         return ret;
1791 }
1792 #endif
1793
1794 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1795                 long npages)
1796 {
1797         pnv_tce_free(tbl, index, npages);
1798
1799         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1800 }
1801
1802 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1803         .set = pnv_ioda1_tce_build,
1804 #ifdef CONFIG_IOMMU_API
1805         .exchange = pnv_ioda1_tce_xchg,
1806 #endif
1807         .clear = pnv_ioda1_tce_free,
1808         .get = pnv_tce_get,
1809 };
1810
1811 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1812 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1813 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1814
1815 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1816 {
1817         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1818         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1819
1820         mb(); /* Ensure previous TCE table stores are visible */
1821         if (rm)
1822                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1823         else
1824                 __raw_writeq(cpu_to_be64(val), invalidate);
1825 }
1826
1827 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1828 {
1829         /* 01xb - invalidate TCEs that match the specified PE# */
1830         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1831         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1832
1833         mb(); /* Ensure above stores are visible */
1834         __raw_writeq(cpu_to_be64(val), invalidate);
1835 }
1836
1837 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1838                                         unsigned shift, unsigned long index,
1839                                         unsigned long npages)
1840 {
1841         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1842         unsigned long start, end, inc;
1843
1844         /* We'll invalidate DMA address in PE scope */
1845         start = PHB3_TCE_KILL_INVAL_ONE;
1846         start |= (pe->pe_number & 0xFF);
1847         end = start;
1848
1849         /* Figure out the start, end and step */
1850         start |= (index << shift);
1851         end |= ((index + npages - 1) << shift);
1852         inc = (0x1ull << shift);
1853         mb();
1854
1855         while (start <= end) {
1856                 if (rm)
1857                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1858                 else
1859                         __raw_writeq(cpu_to_be64(start), invalidate);
1860                 start += inc;
1861         }
1862 }
1863
1864 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1865 {
1866         struct pnv_phb *phb = pe->phb;
1867
1868         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1869                 pnv_pci_phb3_tce_invalidate_pe(pe);
1870         else
1871                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1872                                   pe->pe_number, 0, 0, 0);
1873 }
1874
1875 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1876                 unsigned long index, unsigned long npages, bool rm)
1877 {
1878         struct iommu_table_group_link *tgl;
1879
1880         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1881                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1882                                 struct pnv_ioda_pe, table_group);
1883                 struct pnv_phb *phb = pe->phb;
1884                 unsigned int shift = tbl->it_page_shift;
1885
1886                 if (phb->type == PNV_PHB_NPU) {
1887                         /*
1888                          * The NVLink hardware does not support TCE kill
1889                          * per TCE entry so we have to invalidate
1890                          * the entire cache for it.
1891                          */
1892                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1893                         continue;
1894                 }
1895                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1896                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1897                                                     index, npages);
1898                 else if (rm)
1899                         opal_rm_pci_tce_kill(phb->opal_id,
1900                                              OPAL_PCI_TCE_KILL_PAGES,
1901                                              pe->pe_number, 1u << shift,
1902                                              index << shift, npages);
1903                 else
1904                         opal_pci_tce_kill(phb->opal_id,
1905                                           OPAL_PCI_TCE_KILL_PAGES,
1906                                           pe->pe_number, 1u << shift,
1907                                           index << shift, npages);
1908         }
1909 }
1910
1911 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1912                 long npages, unsigned long uaddr,
1913                 enum dma_data_direction direction,
1914                 struct dma_attrs *attrs)
1915 {
1916         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1917                         attrs);
1918
1919         if (!ret)
1920                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1921
1922         return ret;
1923 }
1924
1925 #ifdef CONFIG_IOMMU_API
1926 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1927                 unsigned long *hpa, enum dma_data_direction *direction)
1928 {
1929         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1930
1931         if (!ret)
1932                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1933
1934         return ret;
1935 }
1936 #endif
1937
1938 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1939                 long npages)
1940 {
1941         pnv_tce_free(tbl, index, npages);
1942
1943         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1944 }
1945
1946 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1947 {
1948         pnv_pci_ioda2_table_free_pages(tbl);
1949         iommu_free_table(tbl, "pnv");
1950 }
1951
1952 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1953         .set = pnv_ioda2_tce_build,
1954 #ifdef CONFIG_IOMMU_API
1955         .exchange = pnv_ioda2_tce_xchg,
1956 #endif
1957         .clear = pnv_ioda2_tce_free,
1958         .get = pnv_tce_get,
1959         .free = pnv_ioda2_table_free,
1960 };
1961
1962 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1963 {
1964         unsigned int *weight = (unsigned int *)data;
1965
1966         /* This is quite simplistic. The "base" weight of a device
1967          * is 10. 0 means no DMA is to be accounted for it.
1968          */
1969         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1970                 return 0;
1971
1972         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1973             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1974             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1975                 *weight += 3;
1976         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1977                 *weight += 15;
1978         else
1979                 *weight += 10;
1980
1981         return 0;
1982 }
1983
1984 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
1985 {
1986         unsigned int weight = 0;
1987
1988         /* SRIOV VF has same DMA32 weight as its PF */
1989 #ifdef CONFIG_PCI_IOV
1990         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
1991                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
1992                 return weight;
1993         }
1994 #endif
1995
1996         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
1997                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
1998         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
1999                 struct pci_dev *pdev;
2000
2001                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2002                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2003         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2004                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2005         }
2006
2007         return weight;
2008 }
2009
2010 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2011                                        struct pnv_ioda_pe *pe)
2012 {
2013
2014         struct page *tce_mem = NULL;
2015         struct iommu_table *tbl;
2016         unsigned int weight, total_weight = 0;
2017         unsigned int tce32_segsz, base, segs, avail, i;
2018         int64_t rc;
2019         void *addr;
2020
2021         /* XXX FIXME: Handle 64-bit only DMA devices */
2022         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2023         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2024         weight = pnv_pci_ioda_pe_dma_weight(pe);
2025         if (!weight)
2026                 return;
2027
2028         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2029                      &total_weight);
2030         segs = (weight * phb->ioda.dma32_count) / total_weight;
2031         if (!segs)
2032                 segs = 1;
2033
2034         /*
2035          * Allocate contiguous DMA32 segments. We begin with the expected
2036          * number of segments. With one more attempt, the number of DMA32
2037          * segments to be allocated is decreased by one until one segment
2038          * is allocated successfully.
2039          */
2040         do {
2041                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2042                         for (avail = 0, i = base; i < base + segs; i++) {
2043                                 if (phb->ioda.dma32_segmap[i] ==
2044                                     IODA_INVALID_PE)
2045                                         avail++;
2046                         }
2047
2048                         if (avail == segs)
2049                                 goto found;
2050                 }
2051         } while (--segs);
2052
2053         if (!segs) {
2054                 pe_warn(pe, "No available DMA32 segments\n");
2055                 return;
2056         }
2057
2058 found:
2059         tbl = pnv_pci_table_alloc(phb->hose->node);
2060         iommu_register_group(&pe->table_group, phb->hose->global_number,
2061                         pe->pe_number);
2062         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2063
2064         /* Grab a 32-bit TCE table */
2065         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2066                 weight, total_weight, base, segs);
2067         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2068                 base * PNV_IODA1_DMA32_SEGSIZE,
2069                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2070
2071         /* XXX Currently, we allocate one big contiguous table for the
2072          * TCEs. We only really need one chunk per 256M of TCE space
2073          * (ie per segment) but that's an optimization for later, it
2074          * requires some added smarts with our get/put_tce implementation
2075          *
2076          * Each TCE page is 4KB in size and each TCE entry occupies 8
2077          * bytes
2078          */
2079         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2080         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2081                                    get_order(tce32_segsz * segs));
2082         if (!tce_mem) {
2083                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2084                 goto fail;
2085         }
2086         addr = page_address(tce_mem);
2087         memset(addr, 0, tce32_segsz * segs);
2088
2089         /* Configure HW */
2090         for (i = 0; i < segs; i++) {
2091                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2092                                               pe->pe_number,
2093                                               base + i, 1,
2094                                               __pa(addr) + tce32_segsz * i,
2095                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2096                 if (rc) {
2097                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2098                                " err %ld\n", rc);
2099                         goto fail;
2100                 }
2101         }
2102
2103         /* Setup DMA32 segment mapping */
2104         for (i = base; i < base + segs; i++)
2105                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2106
2107         /* Setup linux iommu table */
2108         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2109                                   base * PNV_IODA1_DMA32_SEGSIZE,
2110                                   IOMMU_PAGE_SHIFT_4K);
2111
2112         tbl->it_ops = &pnv_ioda1_iommu_ops;
2113         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2114         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2115         iommu_init_table(tbl, phb->hose->node);
2116
2117         if (pe->flags & PNV_IODA_PE_DEV) {
2118                 /*
2119                  * Setting table base here only for carrying iommu_group
2120                  * further down to let iommu_add_device() do the job.
2121                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2122                  */
2123                 set_iommu_table_base(&pe->pdev->dev, tbl);
2124                 iommu_add_device(&pe->pdev->dev);
2125         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2126                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2127
2128         return;
2129  fail:
2130         /* XXX Failure: Try to fallback to 64-bit only ? */
2131         if (tce_mem)
2132                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2133         if (tbl) {
2134                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2135                 iommu_free_table(tbl, "pnv");
2136         }
2137 }
2138
2139 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2140                 int num, struct iommu_table *tbl)
2141 {
2142         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2143                         table_group);
2144         struct pnv_phb *phb = pe->phb;
2145         int64_t rc;
2146         const unsigned long size = tbl->it_indirect_levels ?
2147                         tbl->it_level_size : tbl->it_size;
2148         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2149         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2150
2151         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2152                         start_addr, start_addr + win_size - 1,
2153                         IOMMU_PAGE_SIZE(tbl));
2154
2155         /*
2156          * Map TCE table through TVT. The TVE index is the PE number
2157          * shifted by 1 bit for 32-bits DMA space.
2158          */
2159         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2160                         pe->pe_number,
2161                         (pe->pe_number << 1) + num,
2162                         tbl->it_indirect_levels + 1,
2163                         __pa(tbl->it_base),
2164                         size << 3,
2165                         IOMMU_PAGE_SIZE(tbl));
2166         if (rc) {
2167                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2168                 return rc;
2169         }
2170
2171         pnv_pci_link_table_and_group(phb->hose->node, num,
2172                         tbl, &pe->table_group);
2173         pnv_pci_phb3_tce_invalidate_pe(pe);
2174
2175         return 0;
2176 }
2177
2178 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2179 {
2180         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2181         int64_t rc;
2182
2183         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2184         if (enable) {
2185                 phys_addr_t top = memblock_end_of_DRAM();
2186
2187                 top = roundup_pow_of_two(top);
2188                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2189                                                      pe->pe_number,
2190                                                      window_id,
2191                                                      pe->tce_bypass_base,
2192                                                      top);
2193         } else {
2194                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2195                                                      pe->pe_number,
2196                                                      window_id,
2197                                                      pe->tce_bypass_base,
2198                                                      0);
2199         }
2200         if (rc)
2201                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2202         else
2203                 pe->tce_bypass_enabled = enable;
2204 }
2205
2206 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2207                 __u32 page_shift, __u64 window_size, __u32 levels,
2208                 struct iommu_table *tbl);
2209
2210 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2211                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2212                 struct iommu_table **ptbl)
2213 {
2214         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2215                         table_group);
2216         int nid = pe->phb->hose->node;
2217         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2218         long ret;
2219         struct iommu_table *tbl;
2220
2221         tbl = pnv_pci_table_alloc(nid);
2222         if (!tbl)
2223                 return -ENOMEM;
2224
2225         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2226                         bus_offset, page_shift, window_size,
2227                         levels, tbl);
2228         if (ret) {
2229                 iommu_free_table(tbl, "pnv");
2230                 return ret;
2231         }
2232
2233         tbl->it_ops = &pnv_ioda2_iommu_ops;
2234
2235         *ptbl = tbl;
2236
2237         return 0;
2238 }
2239
2240 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2241 {
2242         struct iommu_table *tbl = NULL;
2243         long rc;
2244
2245         /*
2246          * crashkernel= specifies the kdump kernel's maximum memory at
2247          * some offset and there is no guaranteed the result is a power
2248          * of 2, which will cause errors later.
2249          */
2250         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2251
2252         /*
2253          * In memory constrained environments, e.g. kdump kernel, the
2254          * DMA window can be larger than available memory, which will
2255          * cause errors later.
2256          */
2257         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2258
2259         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2260                         IOMMU_PAGE_SHIFT_4K,
2261                         window_size,
2262                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2263         if (rc) {
2264                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2265                                 rc);
2266                 return rc;
2267         }
2268
2269         iommu_init_table(tbl, pe->phb->hose->node);
2270
2271         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2272         if (rc) {
2273                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2274                                 rc);
2275                 pnv_ioda2_table_free(tbl);
2276                 return rc;
2277         }
2278
2279         if (!pnv_iommu_bypass_disabled)
2280                 pnv_pci_ioda2_set_bypass(pe, true);
2281
2282         /*
2283          * Setting table base here only for carrying iommu_group
2284          * further down to let iommu_add_device() do the job.
2285          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2286          */
2287         if (pe->flags & PNV_IODA_PE_DEV)
2288                 set_iommu_table_base(&pe->pdev->dev, tbl);
2289
2290         return 0;
2291 }
2292
2293 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2294 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2295                 int num)
2296 {
2297         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2298                         table_group);
2299         struct pnv_phb *phb = pe->phb;
2300         long ret;
2301
2302         pe_info(pe, "Removing DMA window #%d\n", num);
2303
2304         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2305                         (pe->pe_number << 1) + num,
2306                         0/* levels */, 0/* table address */,
2307                         0/* table size */, 0/* page size */);
2308         if (ret)
2309                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2310         else
2311                 pnv_pci_phb3_tce_invalidate_pe(pe);
2312
2313         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2314
2315         return ret;
2316 }
2317 #endif
2318
2319 #ifdef CONFIG_IOMMU_API
2320 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2321                 __u64 window_size, __u32 levels)
2322 {
2323         unsigned long bytes = 0;
2324         const unsigned window_shift = ilog2(window_size);
2325         unsigned entries_shift = window_shift - page_shift;
2326         unsigned table_shift = entries_shift + 3;
2327         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2328         unsigned long direct_table_size;
2329
2330         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2331                         (window_size > memory_hotplug_max()) ||
2332                         !is_power_of_2(window_size))
2333                 return 0;
2334
2335         /* Calculate a direct table size from window_size and levels */
2336         entries_shift = (entries_shift + levels - 1) / levels;
2337         table_shift = entries_shift + 3;
2338         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2339         direct_table_size =  1UL << table_shift;
2340
2341         for ( ; levels; --levels) {
2342                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2343
2344                 tce_table_size /= direct_table_size;
2345                 tce_table_size <<= 3;
2346                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2347         }
2348
2349         return bytes;
2350 }
2351
2352 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2353 {
2354         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2355                                                 table_group);
2356         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2357         struct iommu_table *tbl = pe->table_group.tables[0];
2358
2359         pnv_pci_ioda2_set_bypass(pe, false);
2360         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2361         pnv_ioda2_table_free(tbl);
2362 }
2363
2364 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2365 {
2366         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2367                                                 table_group);
2368
2369         pnv_pci_ioda2_setup_default_config(pe);
2370 }
2371
2372 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2373         .get_table_size = pnv_pci_ioda2_get_table_size,
2374         .create_table = pnv_pci_ioda2_create_table,
2375         .set_window = pnv_pci_ioda2_set_window,
2376         .unset_window = pnv_pci_ioda2_unset_window,
2377         .take_ownership = pnv_ioda2_take_ownership,
2378         .release_ownership = pnv_ioda2_release_ownership,
2379 };
2380
2381 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2382 {
2383         struct pci_controller *hose;
2384         struct pnv_phb *phb;
2385         struct pnv_ioda_pe **ptmppe = opaque;
2386         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2387         struct pci_dn *pdn = pci_get_pdn(pdev);
2388
2389         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2390                 return 0;
2391
2392         hose = pci_bus_to_host(pdev->bus);
2393         phb = hose->private_data;
2394         if (phb->type != PNV_PHB_NPU)
2395                 return 0;
2396
2397         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2398
2399         return 1;
2400 }
2401
2402 /*
2403  * This returns PE of associated NPU.
2404  * This assumes that NPU is in the same IOMMU group with GPU and there is
2405  * no other PEs.
2406  */
2407 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2408                 struct iommu_table_group *table_group)
2409 {
2410         struct pnv_ioda_pe *npe = NULL;
2411         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2412                         gpe_table_group_to_npe_cb);
2413
2414         BUG_ON(!ret || !npe);
2415
2416         return npe;
2417 }
2418
2419 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2420                 int num, struct iommu_table *tbl)
2421 {
2422         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2423
2424         if (ret)
2425                 return ret;
2426
2427         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2428         if (ret)
2429                 pnv_pci_ioda2_unset_window(table_group, num);
2430
2431         return ret;
2432 }
2433
2434 static long pnv_pci_ioda2_npu_unset_window(
2435                 struct iommu_table_group *table_group,
2436                 int num)
2437 {
2438         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2439
2440         if (ret)
2441                 return ret;
2442
2443         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2444 }
2445
2446 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2447 {
2448         /*
2449          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2450          * the iommu_table if 32bit DMA is enabled.
2451          */
2452         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2453         pnv_ioda2_take_ownership(table_group);
2454 }
2455
2456 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2457         .get_table_size = pnv_pci_ioda2_get_table_size,
2458         .create_table = pnv_pci_ioda2_create_table,
2459         .set_window = pnv_pci_ioda2_npu_set_window,
2460         .unset_window = pnv_pci_ioda2_npu_unset_window,
2461         .take_ownership = pnv_ioda2_npu_take_ownership,
2462         .release_ownership = pnv_ioda2_release_ownership,
2463 };
2464
2465 static void pnv_pci_ioda_setup_iommu_api(void)
2466 {
2467         struct pci_controller *hose, *tmp;
2468         struct pnv_phb *phb;
2469         struct pnv_ioda_pe *pe, *gpe;
2470
2471         /*
2472          * Now we have all PHBs discovered, time to add NPU devices to
2473          * the corresponding IOMMU groups.
2474          */
2475         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2476                 phb = hose->private_data;
2477
2478                 if (phb->type != PNV_PHB_NPU)
2479                         continue;
2480
2481                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2482                         gpe = pnv_pci_npu_setup_iommu(pe);
2483                         if (gpe)
2484                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2485                 }
2486         }
2487 }
2488 #else /* !CONFIG_IOMMU_API */
2489 static void pnv_pci_ioda_setup_iommu_api(void) { };
2490 #endif
2491
2492 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2493                 unsigned levels, unsigned long limit,
2494                 unsigned long *current_offset, unsigned long *total_allocated)
2495 {
2496         struct page *tce_mem = NULL;
2497         __be64 *addr, *tmp;
2498         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2499         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2500         unsigned entries = 1UL << (shift - 3);
2501         long i;
2502
2503         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2504         if (!tce_mem) {
2505                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2506                 return NULL;
2507         }
2508         addr = page_address(tce_mem);
2509         memset(addr, 0, allocated);
2510         *total_allocated += allocated;
2511
2512         --levels;
2513         if (!levels) {
2514                 *current_offset += allocated;
2515                 return addr;
2516         }
2517
2518         for (i = 0; i < entries; ++i) {
2519                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2520                                 levels, limit, current_offset, total_allocated);
2521                 if (!tmp)
2522                         break;
2523
2524                 addr[i] = cpu_to_be64(__pa(tmp) |
2525                                 TCE_PCI_READ | TCE_PCI_WRITE);
2526
2527                 if (*current_offset >= limit)
2528                         break;
2529         }
2530
2531         return addr;
2532 }
2533
2534 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2535                 unsigned long size, unsigned level);
2536
2537 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2538                 __u32 page_shift, __u64 window_size, __u32 levels,
2539                 struct iommu_table *tbl)
2540 {
2541         void *addr;
2542         unsigned long offset = 0, level_shift, total_allocated = 0;
2543         const unsigned window_shift = ilog2(window_size);
2544         unsigned entries_shift = window_shift - page_shift;
2545         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2546         const unsigned long tce_table_size = 1UL << table_shift;
2547
2548         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2549                 return -EINVAL;
2550
2551         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2552                 return -EINVAL;
2553
2554         /* Adjust direct table size from window_size and levels */
2555         entries_shift = (entries_shift + levels - 1) / levels;
2556         level_shift = entries_shift + 3;
2557         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2558
2559         /* Allocate TCE table */
2560         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2561                         levels, tce_table_size, &offset, &total_allocated);
2562
2563         /* addr==NULL means that the first level allocation failed */
2564         if (!addr)
2565                 return -ENOMEM;
2566
2567         /*
2568          * First level was allocated but some lower level failed as
2569          * we did not allocate as much as we wanted,
2570          * release partially allocated table.
2571          */
2572         if (offset < tce_table_size) {
2573                 pnv_pci_ioda2_table_do_free_pages(addr,
2574                                 1ULL << (level_shift - 3), levels - 1);
2575                 return -ENOMEM;
2576         }
2577
2578         /* Setup linux iommu table */
2579         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2580                         page_shift);
2581         tbl->it_level_size = 1ULL << (level_shift - 3);
2582         tbl->it_indirect_levels = levels - 1;
2583         tbl->it_allocated_size = total_allocated;
2584
2585         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2586                         window_size, tce_table_size, bus_offset);
2587
2588         return 0;
2589 }
2590
2591 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2592                 unsigned long size, unsigned level)
2593 {
2594         const unsigned long addr_ul = (unsigned long) addr &
2595                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2596
2597         if (level) {
2598                 long i;
2599                 u64 *tmp = (u64 *) addr_ul;
2600
2601                 for (i = 0; i < size; ++i) {
2602                         unsigned long hpa = be64_to_cpu(tmp[i]);
2603
2604                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2605                                 continue;
2606
2607                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2608                                         level - 1);
2609                 }
2610         }
2611
2612         free_pages(addr_ul, get_order(size << 3));
2613 }
2614
2615 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2616 {
2617         const unsigned long size = tbl->it_indirect_levels ?
2618                         tbl->it_level_size : tbl->it_size;
2619
2620         if (!tbl->it_size)
2621                 return;
2622
2623         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2624                         tbl->it_indirect_levels);
2625 }
2626
2627 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2628                                        struct pnv_ioda_pe *pe)
2629 {
2630         int64_t rc;
2631
2632         if (!pnv_pci_ioda_pe_dma_weight(pe))
2633                 return;
2634
2635         /* TVE #1 is selected by PCI address bit 59 */
2636         pe->tce_bypass_base = 1ull << 59;
2637
2638         iommu_register_group(&pe->table_group, phb->hose->global_number,
2639                         pe->pe_number);
2640
2641         /* The PE will reserve all possible 32-bits space */
2642         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2643                 phb->ioda.m32_pci_base);
2644
2645         /* Setup linux iommu table */
2646         pe->table_group.tce32_start = 0;
2647         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2648         pe->table_group.max_dynamic_windows_supported =
2649                         IOMMU_TABLE_GROUP_MAX_TABLES;
2650         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2651         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2652 #ifdef CONFIG_IOMMU_API
2653         pe->table_group.ops = &pnv_pci_ioda2_ops;
2654 #endif
2655
2656         rc = pnv_pci_ioda2_setup_default_config(pe);
2657         if (rc)
2658                 return;
2659
2660         if (pe->flags & PNV_IODA_PE_DEV)
2661                 iommu_add_device(&pe->pdev->dev);
2662         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2663                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2664 }
2665
2666 #ifdef CONFIG_PCI_MSI
2667 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2668 {
2669         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2670         struct irq_chip *chip = irq_data_get_irq_chip(d);
2671         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2672                                            ioda.irq_chip);
2673         int64_t rc;
2674
2675         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2676         WARN_ON_ONCE(rc);
2677
2678         icp_native_eoi(d);
2679 }
2680
2681
2682 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2683 {
2684         struct irq_data *idata;
2685         struct irq_chip *ichip;
2686
2687         /* The MSI EOI OPAL call is only needed on PHB3 */
2688         if (phb->model != PNV_PHB_MODEL_PHB3)
2689                 return;
2690
2691         if (!phb->ioda.irq_chip_init) {
2692                 /*
2693                  * First time we setup an MSI IRQ, we need to setup the
2694                  * corresponding IRQ chip to route correctly.
2695                  */
2696                 idata = irq_get_irq_data(virq);
2697                 ichip = irq_data_get_irq_chip(idata);
2698                 phb->ioda.irq_chip_init = 1;
2699                 phb->ioda.irq_chip = *ichip;
2700                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2701         }
2702         irq_set_chip(virq, &phb->ioda.irq_chip);
2703 }
2704
2705 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2706                                   unsigned int hwirq, unsigned int virq,
2707                                   unsigned int is_64, struct msi_msg *msg)
2708 {
2709         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2710         unsigned int xive_num = hwirq - phb->msi_base;
2711         __be32 data;
2712         int rc;
2713
2714         /* No PE assigned ? bail out ... no MSI for you ! */
2715         if (pe == NULL)
2716                 return -ENXIO;
2717
2718         /* Check if we have an MVE */
2719         if (pe->mve_number < 0)
2720                 return -ENXIO;
2721
2722         /* Force 32-bit MSI on some broken devices */
2723         if (dev->no_64bit_msi)
2724                 is_64 = 0;
2725
2726         /* Assign XIVE to PE */
2727         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2728         if (rc) {
2729                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2730                         pci_name(dev), rc, xive_num);
2731                 return -EIO;
2732         }
2733
2734         if (is_64) {
2735                 __be64 addr64;
2736
2737                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2738                                      &addr64, &data);
2739                 if (rc) {
2740                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2741                                 pci_name(dev), rc);
2742                         return -EIO;
2743                 }
2744                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2745                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2746         } else {
2747                 __be32 addr32;
2748
2749                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2750                                      &addr32, &data);
2751                 if (rc) {
2752                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2753                                 pci_name(dev), rc);
2754                         return -EIO;
2755                 }
2756                 msg->address_hi = 0;
2757                 msg->address_lo = be32_to_cpu(addr32);
2758         }
2759         msg->data = be32_to_cpu(data);
2760
2761         pnv_set_msi_irq_chip(phb, virq);
2762
2763         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2764                  " address=%x_%08x data=%x PE# %d\n",
2765                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2766                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2767
2768         return 0;
2769 }
2770
2771 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2772 {
2773         unsigned int count;
2774         const __be32 *prop = of_get_property(phb->hose->dn,
2775                                              "ibm,opal-msi-ranges", NULL);
2776         if (!prop) {
2777                 /* BML Fallback */
2778                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2779         }
2780         if (!prop)
2781                 return;
2782
2783         phb->msi_base = be32_to_cpup(prop);
2784         count = be32_to_cpup(prop + 1);
2785         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2786                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2787                        phb->hose->global_number);
2788                 return;
2789         }
2790
2791         phb->msi_setup = pnv_pci_ioda_msi_setup;
2792         phb->msi32_support = 1;
2793         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2794                 count, phb->msi_base);
2795 }
2796 #else
2797 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2798 #endif /* CONFIG_PCI_MSI */
2799
2800 #ifdef CONFIG_PCI_IOV
2801 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2802 {
2803         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2804         struct pnv_phb *phb = hose->private_data;
2805         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2806         struct resource *res;
2807         int i;
2808         resource_size_t size, total_vf_bar_sz;
2809         struct pci_dn *pdn;
2810         int mul, total_vfs;
2811
2812         if (!pdev->is_physfn || pdev->is_added)
2813                 return;
2814
2815         pdn = pci_get_pdn(pdev);
2816         pdn->vfs_expanded = 0;
2817         pdn->m64_single_mode = false;
2818
2819         total_vfs = pci_sriov_get_totalvfs(pdev);
2820         mul = phb->ioda.total_pe_num;
2821         total_vf_bar_sz = 0;
2822
2823         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2824                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2825                 if (!res->flags || res->parent)
2826                         continue;
2827                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2828                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2829                                         " non M64 VF BAR%d: %pR. \n",
2830                                  i, res);
2831                         goto truncate_iov;
2832                 }
2833
2834                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2835                                 i + PCI_IOV_RESOURCES);
2836
2837                 /*
2838                  * If bigger than quarter of M64 segment size, just round up
2839                  * power of two.
2840                  *
2841                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2842                  * with other devices, IOV BAR size is expanded to be
2843                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2844                  * segment size , the expanded size would equal to half of the
2845                  * whole M64 space size, which will exhaust the M64 Space and
2846                  * limit the system flexibility.  This is a design decision to
2847                  * set the boundary to quarter of the M64 segment size.
2848                  */
2849                 if (total_vf_bar_sz > gate) {
2850                         mul = roundup_pow_of_two(total_vfs);
2851                         dev_info(&pdev->dev,
2852                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2853                                 total_vf_bar_sz, gate, mul);
2854                         pdn->m64_single_mode = true;
2855                         break;
2856                 }
2857         }
2858
2859         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2860                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2861                 if (!res->flags || res->parent)
2862                         continue;
2863
2864                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2865                 /*
2866                  * On PHB3, the minimum size alignment of M64 BAR in single
2867                  * mode is 32MB.
2868                  */
2869                 if (pdn->m64_single_mode && (size < SZ_32M))
2870                         goto truncate_iov;
2871                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2872                 res->end = res->start + size * mul - 1;
2873                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2874                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2875                          i, res, mul);
2876         }
2877         pdn->vfs_expanded = mul;
2878
2879         return;
2880
2881 truncate_iov:
2882         /* To save MMIO space, IOV BAR is truncated. */
2883         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2884                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2885                 res->flags = 0;
2886                 res->end = res->start - 1;
2887         }
2888 }
2889 #endif /* CONFIG_PCI_IOV */
2890
2891 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2892                                   struct resource *res)
2893 {
2894         struct pnv_phb *phb = pe->phb;
2895         struct pci_bus_region region;
2896         int index;
2897         int64_t rc;
2898
2899         if (!res || !res->flags || res->start > res->end)
2900                 return;
2901
2902         if (res->flags & IORESOURCE_IO) {
2903                 region.start = res->start - phb->ioda.io_pci_base;
2904                 region.end   = res->end - phb->ioda.io_pci_base;
2905                 index = region.start / phb->ioda.io_segsize;
2906
2907                 while (index < phb->ioda.total_pe_num &&
2908                        region.start <= region.end) {
2909                         phb->ioda.io_segmap[index] = pe->pe_number;
2910                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2911                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2912                         if (rc != OPAL_SUCCESS) {
2913                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
2914                                        __func__, rc, index, pe->pe_number);
2915                                 break;
2916                         }
2917
2918                         region.start += phb->ioda.io_segsize;
2919                         index++;
2920                 }
2921         } else if ((res->flags & IORESOURCE_MEM) &&
2922                    !pnv_pci_is_mem_pref_64(res->flags)) {
2923                 region.start = res->start -
2924                                phb->hose->mem_offset[0] -
2925                                phb->ioda.m32_pci_base;
2926                 region.end   = res->end -
2927                                phb->hose->mem_offset[0] -
2928                                phb->ioda.m32_pci_base;
2929                 index = region.start / phb->ioda.m32_segsize;
2930
2931                 while (index < phb->ioda.total_pe_num &&
2932                        region.start <= region.end) {
2933                         phb->ioda.m32_segmap[index] = pe->pe_number;
2934                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2935                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2936                         if (rc != OPAL_SUCCESS) {
2937                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
2938                                        __func__, rc, index, pe->pe_number);
2939                                 break;
2940                         }
2941
2942                         region.start += phb->ioda.m32_segsize;
2943                         index++;
2944                 }
2945         }
2946 }
2947
2948 /*
2949  * This function is supposed to be called on basis of PE from top
2950  * to bottom style. So the the I/O or MMIO segment assigned to
2951  * parent PE could be overrided by its child PEs if necessary.
2952  */
2953 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
2954 {
2955         struct pci_dev *pdev;
2956         int i;
2957
2958         /*
2959          * NOTE: We only care PCI bus based PE for now. For PCI
2960          * device based PE, for example SRIOV sensitive VF should
2961          * be figured out later.
2962          */
2963         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2964
2965         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
2966                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2967                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
2968
2969                 /*
2970                  * If the PE contains all subordinate PCI buses, the
2971                  * windows of the child bridges should be mapped to
2972                  * the PE as well.
2973                  */
2974                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
2975                         continue;
2976                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
2977                         pnv_ioda_setup_pe_res(pe,
2978                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
2979         }
2980 }
2981
2982 static void pnv_pci_ioda_create_dbgfs(void)
2983 {
2984 #ifdef CONFIG_DEBUG_FS
2985         struct pci_controller *hose, *tmp;
2986         struct pnv_phb *phb;
2987         char name[16];
2988
2989         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2990                 phb = hose->private_data;
2991
2992                 /* Notify initialization of PHB done */
2993                 phb->initialized = 1;
2994
2995                 sprintf(name, "PCI%04x", hose->global_number);
2996                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2997                 if (!phb->dbgfs)
2998                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2999                                 __func__, hose->global_number);
3000         }
3001 #endif /* CONFIG_DEBUG_FS */
3002 }
3003
3004 static void pnv_pci_ioda_fixup(void)
3005 {
3006         pnv_pci_ioda_setup_PEs();
3007         pnv_pci_ioda_setup_iommu_api();
3008         pnv_pci_ioda_create_dbgfs();
3009
3010 #ifdef CONFIG_EEH
3011         eeh_init();
3012         eeh_addr_cache_build();
3013 #endif
3014 }
3015
3016 /*
3017  * Returns the alignment for I/O or memory windows for P2P
3018  * bridges. That actually depends on how PEs are segmented.
3019  * For now, we return I/O or M32 segment size for PE sensitive
3020  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3021  * 1MiB for memory) will be returned.
3022  *
3023  * The current PCI bus might be put into one PE, which was
3024  * create against the parent PCI bridge. For that case, we
3025  * needn't enlarge the alignment so that we can save some
3026  * resources.
3027  */
3028 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3029                                                 unsigned long type)
3030 {
3031         struct pci_dev *bridge;
3032         struct pci_controller *hose = pci_bus_to_host(bus);
3033         struct pnv_phb *phb = hose->private_data;
3034         int num_pci_bridges = 0;
3035
3036         bridge = bus->self;
3037         while (bridge) {
3038                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3039                         num_pci_bridges++;
3040                         if (num_pci_bridges >= 2)
3041                                 return 1;
3042                 }
3043
3044                 bridge = bridge->bus->self;
3045         }
3046
3047         /* We fail back to M32 if M64 isn't supported */
3048         if (phb->ioda.m64_segsize &&
3049             pnv_pci_is_mem_pref_64(type))
3050                 return phb->ioda.m64_segsize;
3051         if (type & IORESOURCE_MEM)
3052                 return phb->ioda.m32_segsize;
3053
3054         return phb->ioda.io_segsize;
3055 }
3056
3057 /*
3058  * We are updating root port or the upstream port of the
3059  * bridge behind the root port with PHB's windows in order
3060  * to accommodate the changes on required resources during
3061  * PCI (slot) hotplug, which is connected to either root
3062  * port or the downstream ports of PCIe switch behind the
3063  * root port.
3064  */
3065 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3066                                            unsigned long type)
3067 {
3068         struct pci_controller *hose = pci_bus_to_host(bus);
3069         struct pnv_phb *phb = hose->private_data;
3070         struct pci_dev *bridge = bus->self;
3071         struct resource *r, *w;
3072         bool msi_region = false;
3073         int i;
3074
3075         /* Check if we need apply fixup to the bridge's windows */
3076         if (!pci_is_root_bus(bridge->bus) &&
3077             !pci_is_root_bus(bridge->bus->self->bus))
3078                 return;
3079
3080         /* Fixup the resources */
3081         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3082                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3083                 if (!r->flags || !r->parent)
3084                         continue;
3085
3086                 w = NULL;
3087                 if (r->flags & type & IORESOURCE_IO)
3088                         w = &hose->io_resource;
3089                 else if (pnv_pci_is_mem_pref_64(r->flags) &&
3090                          (type & IORESOURCE_PREFETCH) &&
3091                          phb->ioda.m64_segsize)
3092                         w = &hose->mem_resources[1];
3093                 else if (r->flags & type & IORESOURCE_MEM) {
3094                         w = &hose->mem_resources[0];
3095                         msi_region = true;
3096                 }
3097
3098                 r->start = w->start;
3099                 r->end = w->end;
3100
3101                 /* The 64KB 32-bits MSI region shouldn't be included in
3102                  * the 32-bits bridge window. Otherwise, we can see strange
3103                  * issues. One of them is EEH error observed on Garrison.
3104                  *
3105                  * Exclude top 1MB region which is the minimal alignment of
3106                  * 32-bits bridge window.
3107                  */
3108                 if (msi_region) {
3109                         r->end += 0x10000;
3110                         r->end -= 0x100000;
3111                 }
3112         }
3113 }
3114
3115 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3116 {
3117         struct pci_controller *hose = pci_bus_to_host(bus);
3118         struct pnv_phb *phb = hose->private_data;
3119         struct pci_dev *bridge = bus->self;
3120         struct pnv_ioda_pe *pe;
3121         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3122
3123         /* Extend bridge's windows if necessary */
3124         pnv_pci_fixup_bridge_resources(bus, type);
3125
3126         /* The PE for root bus should be realized before any one else */
3127         if (!phb->ioda.root_pe_populated) {
3128                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3129                 if (pe) {
3130                         phb->ioda.root_pe_idx = pe->pe_number;
3131                         phb->ioda.root_pe_populated = true;
3132                 }
3133         }
3134
3135         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3136         if (list_empty(&bus->devices))
3137                 return;
3138
3139         /* Reserve PEs according to used M64 resources */
3140         if (phb->reserve_m64_pe)
3141                 phb->reserve_m64_pe(bus, NULL, all);
3142
3143         /*
3144          * Assign PE. We might run here because of partial hotplug.
3145          * For the case, we just pick up the existing PE and should
3146          * not allocate resources again.
3147          */
3148         pe = pnv_ioda_setup_bus_PE(bus, all);
3149         if (!pe)
3150                 return;
3151
3152         pnv_ioda_setup_pe_seg(pe);
3153         switch (phb->type) {
3154         case PNV_PHB_IODA1:
3155                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3156                 break;
3157         case PNV_PHB_IODA2:
3158                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3159                 break;
3160         default:
3161                 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3162                         __func__, phb->hose->global_number, phb->type);
3163         }
3164 }
3165
3166 #ifdef CONFIG_PCI_IOV
3167 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3168                                                       int resno)
3169 {
3170         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3171         struct pnv_phb *phb = hose->private_data;
3172         struct pci_dn *pdn = pci_get_pdn(pdev);
3173         resource_size_t align;
3174
3175         /*
3176          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3177          * SR-IOV. While from hardware perspective, the range mapped by M64
3178          * BAR should be size aligned.
3179          *
3180          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3181          * powernv-specific hardware restriction is gone. But if just use the
3182          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3183          * in one segment of M64 #15, which introduces the PE conflict between
3184          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3185          * m64_segsize.
3186          *
3187          * This function returns the total IOV BAR size if M64 BAR is in
3188          * Shared PE mode or just VF BAR size if not.
3189          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3190          * M64 segment size if IOV BAR size is less.
3191          */
3192         align = pci_iov_resource_size(pdev, resno);
3193         if (!pdn->vfs_expanded)
3194                 return align;
3195         if (pdn->m64_single_mode)
3196                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3197
3198         return pdn->vfs_expanded * align;
3199 }
3200 #endif /* CONFIG_PCI_IOV */
3201
3202 /* Prevent enabling devices for which we couldn't properly
3203  * assign a PE
3204  */
3205 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3206 {
3207         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3208         struct pnv_phb *phb = hose->private_data;
3209         struct pci_dn *pdn;
3210
3211         /* The function is probably called while the PEs have
3212          * not be created yet. For example, resource reassignment
3213          * during PCI probe period. We just skip the check if
3214          * PEs isn't ready.
3215          */
3216         if (!phb->initialized)
3217                 return true;
3218
3219         pdn = pci_get_pdn(dev);
3220         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3221                 return false;
3222
3223         return true;
3224 }
3225
3226 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3227                                        int num)
3228 {
3229         struct pnv_ioda_pe *pe = container_of(table_group,
3230                                               struct pnv_ioda_pe, table_group);
3231         struct pnv_phb *phb = pe->phb;
3232         unsigned int idx;
3233         long rc;
3234
3235         pe_info(pe, "Removing DMA window #%d\n", num);
3236         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3237                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3238                         continue;
3239
3240                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3241                                                 idx, 0, 0ul, 0ul, 0ul);
3242                 if (rc != OPAL_SUCCESS) {
3243                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3244                                 rc, idx);
3245                         return rc;
3246                 }
3247
3248                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3249         }
3250
3251         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3252         return OPAL_SUCCESS;
3253 }
3254
3255 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3256 {
3257         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3258         struct iommu_table *tbl = pe->table_group.tables[0];
3259         int64_t rc;
3260
3261         if (!weight)
3262                 return;
3263
3264         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3265         if (rc != OPAL_SUCCESS)
3266                 return;
3267
3268         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3269         if (pe->table_group.group) {
3270                 iommu_group_put(pe->table_group.group);
3271                 WARN_ON(pe->table_group.group);
3272         }
3273
3274         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3275         iommu_free_table(tbl, "pnv");
3276 }
3277
3278 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3279 {
3280         struct iommu_table *tbl = pe->table_group.tables[0];
3281         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3282 #ifdef CONFIG_IOMMU_API
3283         int64_t rc;
3284 #endif
3285
3286         if (!weight)
3287                 return;
3288
3289 #ifdef CONFIG_IOMMU_API
3290         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3291         if (rc)
3292                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3293 #endif
3294
3295         pnv_pci_ioda2_set_bypass(pe, false);
3296         if (pe->table_group.group) {
3297                 iommu_group_put(pe->table_group.group);
3298                 WARN_ON(pe->table_group.group);
3299         }
3300
3301         pnv_pci_ioda2_table_free_pages(tbl);
3302         iommu_free_table(tbl, "pnv");
3303 }
3304
3305 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3306                                  unsigned short win,
3307                                  unsigned int *map)
3308 {
3309         struct pnv_phb *phb = pe->phb;
3310         int idx;
3311         int64_t rc;
3312
3313         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3314                 if (map[idx] != pe->pe_number)
3315                         continue;
3316
3317                 if (win == OPAL_M64_WINDOW_TYPE)
3318                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3319                                         phb->ioda.reserved_pe_idx, win,
3320                                         idx / PNV_IODA1_M64_SEGS,
3321                                         idx % PNV_IODA1_M64_SEGS);
3322                 else
3323                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3324                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3325
3326                 if (rc != OPAL_SUCCESS)
3327                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3328                                 rc, win, idx);
3329
3330                 map[idx] = IODA_INVALID_PE;
3331         }
3332 }
3333
3334 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3335 {
3336         struct pnv_phb *phb = pe->phb;
3337
3338         if (phb->type == PNV_PHB_IODA1) {
3339                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3340                                      phb->ioda.io_segmap);
3341                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3342                                      phb->ioda.m32_segmap);
3343                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3344                                      phb->ioda.m64_segmap);
3345         } else if (phb->type == PNV_PHB_IODA2) {
3346                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3347                                      phb->ioda.m32_segmap);
3348         }
3349 }
3350
3351 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3352 {
3353         struct pnv_phb *phb = pe->phb;
3354         struct pnv_ioda_pe *slave, *tmp;
3355
3356         /* Release slave PEs in compound PE */
3357         if (pe->flags & PNV_IODA_PE_MASTER) {
3358                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list)
3359                         pnv_ioda_release_pe(slave);
3360         }
3361
3362         list_del(&pe->list);
3363         switch (phb->type) {
3364         case PNV_PHB_IODA1:
3365                 pnv_pci_ioda1_release_pe_dma(pe);
3366                 break;
3367         case PNV_PHB_IODA2:
3368                 pnv_pci_ioda2_release_pe_dma(pe);
3369                 break;
3370         default:
3371                 WARN_ON(1);
3372         }
3373
3374         pnv_ioda_release_pe_seg(pe);
3375         pnv_ioda_deconfigure_pe(pe->phb, pe);
3376         pnv_ioda_free_pe(pe);
3377 }
3378
3379 static void pnv_pci_release_device(struct pci_dev *pdev)
3380 {
3381         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3382         struct pnv_phb *phb = hose->private_data;
3383         struct pci_dn *pdn = pci_get_pdn(pdev);
3384         struct pnv_ioda_pe *pe;
3385
3386         if (pdev->is_virtfn)
3387                 return;
3388
3389         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3390                 return;
3391
3392         pe = &phb->ioda.pe_array[pdn->pe_number];
3393         WARN_ON(--pe->device_count < 0);
3394         if (pe->device_count == 0)
3395                 pnv_ioda_release_pe(pe);
3396 }
3397
3398 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3399 {
3400         struct pnv_phb *phb = hose->private_data;
3401
3402         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3403                        OPAL_ASSERT_RESET);
3404 }
3405
3406 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3407         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3408         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3409 #ifdef CONFIG_PCI_MSI
3410         .setup_msi_irqs         = pnv_setup_msi_irqs,
3411         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3412 #endif
3413         .enable_device_hook     = pnv_pci_enable_device_hook,
3414         .release_device         = pnv_pci_release_device,
3415         .window_alignment       = pnv_pci_window_alignment,
3416         .setup_bridge           = pnv_pci_setup_bridge,
3417         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3418         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3419         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3420         .shutdown               = pnv_pci_ioda_shutdown,
3421 };
3422
3423 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3424 {
3425         dev_err_once(&npdev->dev,
3426                         "%s operation unsupported for NVLink devices\n",
3427                         __func__);
3428         return -EPERM;
3429 }
3430
3431 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3432         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3433 #ifdef CONFIG_PCI_MSI
3434         .setup_msi_irqs         = pnv_setup_msi_irqs,
3435         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3436 #endif
3437         .enable_device_hook     = pnv_pci_enable_device_hook,
3438         .window_alignment       = pnv_pci_window_alignment,
3439         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3440         .dma_set_mask           = pnv_npu_dma_set_mask,
3441         .shutdown               = pnv_pci_ioda_shutdown,
3442 };
3443
3444 #ifdef CONFIG_CXL_BASE
3445 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3446         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3447         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3448 #ifdef CONFIG_PCI_MSI
3449         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3450         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3451 #endif
3452         .enable_device_hook     = pnv_cxl_enable_device_hook,
3453         .disable_device         = pnv_cxl_disable_device,
3454         .release_device         = pnv_pci_release_device,
3455         .window_alignment       = pnv_pci_window_alignment,
3456         .setup_bridge           = pnv_pci_setup_bridge,
3457         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3458         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3459         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3460         .shutdown               = pnv_pci_ioda_shutdown,
3461 };
3462 #endif
3463
3464 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3465                                          u64 hub_id, int ioda_type)
3466 {
3467         struct pci_controller *hose;
3468         struct pnv_phb *phb;
3469         unsigned long size, m64map_off, m32map_off, pemap_off;
3470         unsigned long iomap_off = 0, dma32map_off = 0;
3471         struct resource r;
3472         const __be64 *prop64;
3473         const __be32 *prop32;
3474         int len;
3475         unsigned int segno;
3476         u64 phb_id;
3477         void *aux;
3478         long rc;
3479
3480         pr_info("Initializing %s PHB (%s)\n",
3481                 pnv_phb_names[ioda_type], of_node_full_name(np));
3482
3483         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3484         if (!prop64) {
3485                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3486                 return;
3487         }
3488         phb_id = be64_to_cpup(prop64);
3489         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3490
3491         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3492
3493         /* Allocate PCI controller */
3494         phb->hose = hose = pcibios_alloc_controller(np);
3495         if (!phb->hose) {
3496                 pr_err("  Can't allocate PCI controller for %s\n",
3497                        np->full_name);
3498                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3499                 return;
3500         }
3501
3502         spin_lock_init(&phb->lock);
3503         prop32 = of_get_property(np, "bus-range", &len);
3504         if (prop32 && len == 8) {
3505                 hose->first_busno = be32_to_cpu(prop32[0]);
3506                 hose->last_busno = be32_to_cpu(prop32[1]);
3507         } else {
3508                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3509                 hose->first_busno = 0;
3510                 hose->last_busno = 0xff;
3511         }
3512         hose->private_data = phb;
3513         phb->hub_id = hub_id;
3514         phb->opal_id = phb_id;
3515         phb->type = ioda_type;
3516         mutex_init(&phb->ioda.pe_alloc_mutex);
3517
3518         /* Detect specific models for error handling */
3519         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3520                 phb->model = PNV_PHB_MODEL_P7IOC;
3521         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3522                 phb->model = PNV_PHB_MODEL_PHB3;
3523         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3524                 phb->model = PNV_PHB_MODEL_NPU;
3525         else
3526                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3527
3528         /* Parse 32-bit and IO ranges (if any) */
3529         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3530
3531         /* Get registers */
3532         if (!of_address_to_resource(np, 0, &r)) {
3533                 phb->regs_phys = r.start;
3534                 phb->regs = ioremap(r.start, resource_size(&r));
3535                 if (phb->regs == NULL)
3536                         pr_err("  Failed to map registers !\n");
3537         }
3538
3539         /* Initialize more IODA stuff */
3540         phb->ioda.total_pe_num = 1;
3541         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3542         if (prop32)
3543                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3544         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3545         if (prop32)
3546                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3547
3548         /* Invalidate RID to PE# mapping */
3549         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3550                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3551
3552         /* Parse 64-bit MMIO range */
3553         pnv_ioda_parse_m64_window(phb);
3554
3555         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3556         /* FW Has already off top 64k of M32 space (MSI space) */
3557         phb->ioda.m32_size += 0x10000;
3558
3559         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3560         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3561         phb->ioda.io_size = hose->pci_io_size;
3562         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3563         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3564
3565         /* Calculate how many 32-bit TCE segments we have */
3566         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3567                                 PNV_IODA1_DMA32_SEGSIZE;
3568
3569         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3570         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3571                         sizeof(unsigned long));
3572         m64map_off = size;
3573         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3574         m32map_off = size;
3575         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3576         if (phb->type == PNV_PHB_IODA1) {
3577                 iomap_off = size;
3578                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3579                 dma32map_off = size;
3580                 size += phb->ioda.dma32_count *
3581                         sizeof(phb->ioda.dma32_segmap[0]);
3582         }
3583         pemap_off = size;
3584         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3585         aux = memblock_virt_alloc(size, 0);
3586         phb->ioda.pe_alloc = aux;
3587         phb->ioda.m64_segmap = aux + m64map_off;
3588         phb->ioda.m32_segmap = aux + m32map_off;
3589         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3590                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3591                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3592         }
3593         if (phb->type == PNV_PHB_IODA1) {
3594                 phb->ioda.io_segmap = aux + iomap_off;
3595                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3596                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3597
3598                 phb->ioda.dma32_segmap = aux + dma32map_off;
3599                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3600                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3601         }
3602         phb->ioda.pe_array = aux + pemap_off;
3603
3604         /*
3605          * Choose PE number for root bus, which shouldn't have
3606          * M64 resources consumed by its child devices. To pick
3607          * the PE number adjacent to the reserved one if possible.
3608          */
3609         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3610         if (phb->ioda.reserved_pe_idx == 0) {
3611                 phb->ioda.root_pe_idx = 1;
3612                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3613         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3614                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3615                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3616         } else {
3617                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3618         }
3619
3620         INIT_LIST_HEAD(&phb->ioda.pe_list);
3621         mutex_init(&phb->ioda.pe_list_mutex);
3622
3623         /* Calculate how many 32-bit TCE segments we have */
3624         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3625                                 PNV_IODA1_DMA32_SEGSIZE;
3626
3627 #if 0 /* We should really do that ... */
3628         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3629                                          window_type,
3630                                          window_num,
3631                                          starting_real_address,
3632                                          starting_pci_address,
3633                                          segment_size);
3634 #endif
3635
3636         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3637                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3638                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3639         if (phb->ioda.m64_size)
3640                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3641                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3642         if (phb->ioda.io_size)
3643                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3644                         phb->ioda.io_size, phb->ioda.io_segsize);
3645
3646
3647         phb->hose->ops = &pnv_pci_ops;
3648         phb->get_pe_state = pnv_ioda_get_pe_state;
3649         phb->freeze_pe = pnv_ioda_freeze_pe;
3650         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3651
3652         /* Setup MSI support */
3653         pnv_pci_init_ioda_msis(phb);
3654
3655         /*
3656          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3657          * to let the PCI core do resource assignment. It's supposed
3658          * that the PCI core will do correct I/O and MMIO alignment
3659          * for the P2P bridge bars so that each PCI bus (excluding
3660          * the child P2P bridges) can form individual PE.
3661          */
3662         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3663
3664         if (phb->type == PNV_PHB_NPU) {
3665                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3666         } else {
3667                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3668                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3669         }
3670
3671 #ifdef CONFIG_PCI_IOV
3672         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3673         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3674 #endif
3675
3676         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3677
3678         /* Reset IODA tables to a clean state */
3679         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3680         if (rc)
3681                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3682
3683         /* If we're running in kdump kerenl, the previous kerenl never
3684          * shutdown PCI devices correctly. We already got IODA table
3685          * cleaned out. So we have to issue PHB reset to stop all PCI
3686          * transactions from previous kerenl.
3687          */
3688         if (is_kdump_kernel()) {
3689                 pr_info("  Issue PHB reset ...\n");
3690                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3691                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3692         }
3693
3694         /* Remove M64 resource if we can't configure it successfully */
3695         if (!phb->init_m64 || phb->init_m64(phb))
3696                 hose->mem_resources[1].flags = 0;
3697 }
3698
3699 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3700 {
3701         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3702 }
3703
3704 void __init pnv_pci_init_npu_phb(struct device_node *np)
3705 {
3706         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3707 }
3708
3709 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3710 {
3711         struct device_node *phbn;
3712         const __be64 *prop64;
3713         u64 hub_id;
3714
3715         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3716
3717         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3718         if (!prop64) {
3719                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3720                 return;
3721         }
3722         hub_id = be64_to_cpup(prop64);
3723         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3724
3725         /* Count child PHBs */
3726         for_each_child_of_node(np, phbn) {
3727                 /* Look for IODA1 PHBs */
3728                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3729                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3730         }
3731 }