2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/ioport.h>
26 #include <linux/percpu.h>
27 #include <linux/memblock.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89 static unsigned long cpu_pgsz_mask;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
98 static int cmp_p64(const void *a, const void *b)
100 const struct linux_prom64_registers *x = a, *y = b;
102 if (x->phys_addr > y->phys_addr)
104 if (x->phys_addr < y->phys_addr)
109 static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
127 prom_printf("Couldn't get %s property from /memory.\n",
132 /* Sanitize what we got from the firmware, by page aligning
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
145 size -= new_base - base;
146 if ((long) size < 0L)
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly;
173 unsigned long kern_size __read_mostly;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64;
177 extern unsigned int sparc_ramdisk_image;
178 extern unsigned int sparc_ramdisk_size;
180 struct page *mem_map_zero __read_mostly;
181 EXPORT_SYMBOL(mem_map_zero);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
185 unsigned long sparc64_kern_pri_context __read_mostly;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187 unsigned long sparc64_kern_sec_context __read_mostly;
189 int num_kernel_image_mappings;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page *page)
200 BUG_ON(tlb_type == hypervisor);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping(page) != NULL));
210 if (page_mapping(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224 static inline void set_dcache_dirty(struct page *page, int this_cpu)
226 unsigned long mask = this_cpu;
227 unsigned long non_cpu_bits;
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
232 __asm__ __volatile__("1:\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
247 unsigned long mask = (1UL << PG_dcache_dirty);
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
271 unsigned long tsb_addr = (unsigned long) ent;
273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
274 tsb_addr = __pa(tsb_addr);
276 __tsb_insert(tsb_addr, tag, pte);
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
281 static void flush_dcache(unsigned long pfn)
285 page = pfn_to_page(pfn);
287 unsigned long pg_flags;
289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
293 int this_cpu = get_cpu();
295 /* This is just to optimize away some function calls
299 flush_dcache_page_impl(page);
301 smp_flush_dcache_page_impl(page, cpu);
303 clear_dcache_dirty_cpu(page, cpu);
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
327 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
329 struct mm_struct *mm;
333 if (tlb_type != hypervisor) {
334 unsigned long pfn = pte_pfn(pte);
342 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
343 if (!pte_accessible(mm, pte))
346 spin_lock_irqsave(&mm->context.lock, flags);
348 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
349 if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) &&
351 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
352 address, pte_val(pte));
355 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
356 address, pte_val(pte));
358 spin_unlock_irqrestore(&mm->context.lock, flags);
361 void flush_dcache_page(struct page *page)
363 struct address_space *mapping;
366 if (tlb_type == hypervisor)
369 /* Do not bother with the expensive D-cache flush if it
370 * is merely the zero page. The 'bigcore' testcase in GDB
371 * causes this case to run millions of times.
373 if (page == ZERO_PAGE(0))
376 this_cpu = get_cpu();
378 mapping = page_mapping(page);
379 if (mapping && !mapping_mapped(mapping)) {
380 int dirty = test_bit(PG_dcache_dirty, &page->flags);
382 int dirty_cpu = dcache_dirty_cpu(page);
384 if (dirty_cpu == this_cpu)
386 smp_flush_dcache_page_impl(page, dirty_cpu);
388 set_dcache_dirty(page, this_cpu);
390 /* We could delay the flush for the !page_mapping
391 * case too. But that case is for exec env/arg
392 * pages and those are %99 certainly going to get
393 * faulted into the tlb (and thus flushed) anyways.
395 flush_dcache_page_impl(page);
401 EXPORT_SYMBOL(flush_dcache_page);
403 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
405 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
406 if (tlb_type == spitfire) {
409 /* This code only runs on Spitfire cpus so this is
410 * why we can assume _PAGE_PADDR_4U.
412 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
413 unsigned long paddr, mask = _PAGE_PADDR_4U;
415 if (kaddr >= PAGE_OFFSET)
416 paddr = kaddr & mask;
418 pgd_t *pgdp = pgd_offset_k(kaddr);
419 pud_t *pudp = pud_offset(pgdp, kaddr);
420 pmd_t *pmdp = pmd_offset(pudp, kaddr);
421 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
423 paddr = pte_val(*ptep) & mask;
425 __flush_icache_page(paddr);
429 EXPORT_SYMBOL(flush_icache_range);
431 void mmu_info(struct seq_file *m)
433 static const char *pgsz_strings[] = {
434 "8K", "64K", "512K", "4MB", "32MB",
435 "256MB", "2GB", "16GB",
439 if (tlb_type == cheetah)
440 seq_printf(m, "MMU Type\t: Cheetah\n");
441 else if (tlb_type == cheetah_plus)
442 seq_printf(m, "MMU Type\t: Cheetah+\n");
443 else if (tlb_type == spitfire)
444 seq_printf(m, "MMU Type\t: Spitfire\n");
445 else if (tlb_type == hypervisor)
446 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
448 seq_printf(m, "MMU Type\t: ???\n");
450 seq_printf(m, "MMU PGSZs\t: ");
452 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
453 if (cpu_pgsz_mask & (1UL << i)) {
454 seq_printf(m, "%s%s",
455 printed ? "," : "", pgsz_strings[i]);
461 #ifdef CONFIG_DEBUG_DCFLUSH
462 seq_printf(m, "DCPageFlushes\t: %d\n",
463 atomic_read(&dcpage_flushes));
465 seq_printf(m, "DCPageFlushesXC\t: %d\n",
466 atomic_read(&dcpage_flushes_xcall));
467 #endif /* CONFIG_SMP */
468 #endif /* CONFIG_DEBUG_DCFLUSH */
471 struct linux_prom_translation prom_trans[512] __read_mostly;
472 unsigned int prom_trans_ents __read_mostly;
474 unsigned long kern_locked_tte_data;
476 /* The obp translations are saved based on 8k pagesize, since obp can
477 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
478 * HI_OBP_ADDRESS range are handled in ktlb.S.
480 static inline int in_obp_range(unsigned long vaddr)
482 return (vaddr >= LOW_OBP_ADDRESS &&
483 vaddr < HI_OBP_ADDRESS);
486 static int cmp_ptrans(const void *a, const void *b)
488 const struct linux_prom_translation *x = a, *y = b;
490 if (x->virt > y->virt)
492 if (x->virt < y->virt)
497 /* Read OBP translations property into 'prom_trans[]'. */
498 static void __init read_obp_translations(void)
500 int n, node, ents, first, last, i;
502 node = prom_finddevice("/virtual-memory");
503 n = prom_getproplen(node, "translations");
504 if (unlikely(n == 0 || n == -1)) {
505 prom_printf("prom_mappings: Couldn't get size.\n");
508 if (unlikely(n > sizeof(prom_trans))) {
509 prom_printf("prom_mappings: Size %d is too big.\n", n);
513 if ((n = prom_getproperty(node, "translations",
514 (char *)&prom_trans[0],
515 sizeof(prom_trans))) == -1) {
516 prom_printf("prom_mappings: Couldn't get property.\n");
520 n = n / sizeof(struct linux_prom_translation);
524 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
527 /* Now kick out all the non-OBP entries. */
528 for (i = 0; i < ents; i++) {
529 if (in_obp_range(prom_trans[i].virt))
533 for (; i < ents; i++) {
534 if (!in_obp_range(prom_trans[i].virt))
539 for (i = 0; i < (last - first); i++) {
540 struct linux_prom_translation *src = &prom_trans[i + first];
541 struct linux_prom_translation *dest = &prom_trans[i];
545 for (; i < ents; i++) {
546 struct linux_prom_translation *dest = &prom_trans[i];
547 dest->virt = dest->size = dest->data = 0x0UL;
550 prom_trans_ents = last - first;
552 if (tlb_type == spitfire) {
553 /* Clear diag TTE bits. */
554 for (i = 0; i < prom_trans_ents; i++)
555 prom_trans[i].data &= ~0x0003fe0000000000UL;
558 /* Force execute bit on. */
559 for (i = 0; i < prom_trans_ents; i++)
560 prom_trans[i].data |= (tlb_type == hypervisor ?
561 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
564 static void __init hypervisor_tlb_lock(unsigned long vaddr,
568 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
571 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
572 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
577 static unsigned long kern_large_tte(unsigned long paddr);
579 static void __init remap_kernel(void)
581 unsigned long phys_page, tte_vaddr, tte_data;
582 int i, tlb_ent = sparc64_highest_locked_tlbent();
584 tte_vaddr = (unsigned long) KERNBASE;
585 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
586 tte_data = kern_large_tte(phys_page);
588 kern_locked_tte_data = tte_data;
590 /* Now lock us into the TLBs via Hypervisor or OBP. */
591 if (tlb_type == hypervisor) {
592 for (i = 0; i < num_kernel_image_mappings; i++) {
593 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
594 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
595 tte_vaddr += 0x400000;
596 tte_data += 0x400000;
599 for (i = 0; i < num_kernel_image_mappings; i++) {
600 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
601 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
602 tte_vaddr += 0x400000;
603 tte_data += 0x400000;
605 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
607 if (tlb_type == cheetah_plus) {
608 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
609 CTX_CHEETAH_PLUS_NUC);
610 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
611 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
616 static void __init inherit_prom_mappings(void)
618 /* Now fixup OBP's idea about where we really are mapped. */
619 printk("Remapping the kernel... ");
624 void prom_world(int enter)
629 __asm__ __volatile__("flushw");
632 void __flush_dcache_range(unsigned long start, unsigned long end)
636 if (tlb_type == spitfire) {
639 for (va = start; va < end; va += 32) {
640 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
644 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647 for (va = start; va < end; va += 32)
648 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
652 "i" (ASI_DCACHE_INVALIDATE));
655 EXPORT_SYMBOL(__flush_dcache_range);
657 /* get_new_mmu_context() uses "cache + 1". */
658 DEFINE_SPINLOCK(ctx_alloc_lock);
659 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
660 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
661 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
662 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
664 /* Caller does TLB context flushing on local CPU if necessary.
665 * The caller also ensures that CTX_VALID(mm->context) is false.
667 * We must be careful about boundary cases so that we never
668 * let the user have CTX 0 (nucleus) or we ever use a CTX
669 * version of zero (and thus NO_CONTEXT would not be caught
670 * by version mis-match tests in mmu_context.h).
672 * Always invoked with interrupts disabled.
674 void get_new_mmu_context(struct mm_struct *mm)
676 unsigned long ctx, new_ctx;
677 unsigned long orig_pgsz_bits;
680 spin_lock(&ctx_alloc_lock);
681 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
682 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
683 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
685 if (new_ctx >= (1 << CTX_NR_BITS)) {
686 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
687 if (new_ctx >= ctx) {
689 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
692 new_ctx = CTX_FIRST_VERSION;
694 /* Don't call memset, for 16 entries that's just
697 mmu_context_bmap[0] = 3;
698 mmu_context_bmap[1] = 0;
699 mmu_context_bmap[2] = 0;
700 mmu_context_bmap[3] = 0;
701 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
702 mmu_context_bmap[i + 0] = 0;
703 mmu_context_bmap[i + 1] = 0;
704 mmu_context_bmap[i + 2] = 0;
705 mmu_context_bmap[i + 3] = 0;
711 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
712 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
714 tlb_context_cache = new_ctx;
715 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
716 spin_unlock(&ctx_alloc_lock);
718 if (unlikely(new_version))
719 smp_new_mmu_context_version();
722 static int numa_enabled = 1;
723 static int numa_debug;
725 static int __init early_numa(char *p)
730 if (strstr(p, "off"))
733 if (strstr(p, "debug"))
738 early_param("numa", early_numa);
740 #define numadbg(f, a...) \
741 do { if (numa_debug) \
742 printk(KERN_INFO f, ## a); \
745 static void __init find_ramdisk(unsigned long phys_base)
747 #ifdef CONFIG_BLK_DEV_INITRD
748 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
749 unsigned long ramdisk_image;
751 /* Older versions of the bootloader only supported a
752 * 32-bit physical address for the ramdisk image
753 * location, stored at sparc_ramdisk_image. Newer
754 * SILO versions set sparc_ramdisk_image to zero and
755 * provide a full 64-bit physical address at
756 * sparc_ramdisk_image64.
758 ramdisk_image = sparc_ramdisk_image;
760 ramdisk_image = sparc_ramdisk_image64;
762 /* Another bootloader quirk. The bootloader normalizes
763 * the physical address to KERNBASE, so we have to
764 * factor that back out and add in the lowest valid
765 * physical page address to get the true physical address.
767 ramdisk_image -= KERNBASE;
768 ramdisk_image += phys_base;
770 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
771 ramdisk_image, sparc_ramdisk_size);
773 initrd_start = ramdisk_image;
774 initrd_end = ramdisk_image + sparc_ramdisk_size;
776 memblock_reserve(initrd_start, sparc_ramdisk_size);
778 initrd_start += PAGE_OFFSET;
779 initrd_end += PAGE_OFFSET;
784 struct node_mem_mask {
788 static struct node_mem_mask node_masks[MAX_NUMNODES];
789 static int num_node_masks;
791 #ifdef CONFIG_NEED_MULTIPLE_NODES
793 int numa_cpu_lookup_table[NR_CPUS];
794 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
796 struct mdesc_mblock {
799 u64 offset; /* RA-to-PA */
801 static struct mdesc_mblock *mblocks;
802 static int num_mblocks;
804 static unsigned long ra_to_pa(unsigned long addr)
808 for (i = 0; i < num_mblocks; i++) {
809 struct mdesc_mblock *m = &mblocks[i];
811 if (addr >= m->base &&
812 addr < (m->base + m->size)) {
820 static int find_node(unsigned long addr)
824 addr = ra_to_pa(addr);
825 for (i = 0; i < num_node_masks; i++) {
826 struct node_mem_mask *p = &node_masks[i];
828 if ((addr & p->mask) == p->val)
831 /* The following condition has been observed on LDOM guests.*/
832 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
833 " rule. Some physical memory will be owned by node 0.");
837 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
839 *nid = find_node(start);
841 while (start < end) {
842 int n = find_node(start);
856 /* This must be invoked after performing all of the necessary
857 * memblock_set_node() calls for 'nid'. We need to be able to get
858 * correct data from get_pfn_range_for_nid().
860 static void __init allocate_node_data(int nid)
862 struct pglist_data *p;
863 unsigned long start_pfn, end_pfn;
864 #ifdef CONFIG_NEED_MULTIPLE_NODES
867 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
869 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
872 NODE_DATA(nid) = __va(paddr);
873 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
875 NODE_DATA(nid)->node_id = nid;
880 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
881 p->node_start_pfn = start_pfn;
882 p->node_spanned_pages = end_pfn - start_pfn;
885 static void init_node_masks_nonnuma(void)
887 #ifdef CONFIG_NEED_MULTIPLE_NODES
891 numadbg("Initializing tables for non-numa.\n");
893 node_masks[0].mask = node_masks[0].val = 0;
896 #ifdef CONFIG_NEED_MULTIPLE_NODES
897 for (i = 0; i < NR_CPUS; i++)
898 numa_cpu_lookup_table[i] = 0;
900 cpumask_setall(&numa_cpumask_lookup_table[0]);
904 #ifdef CONFIG_NEED_MULTIPLE_NODES
905 struct pglist_data *node_data[MAX_NUMNODES];
907 EXPORT_SYMBOL(numa_cpu_lookup_table);
908 EXPORT_SYMBOL(numa_cpumask_lookup_table);
909 EXPORT_SYMBOL(node_data);
911 struct mdesc_mlgroup {
917 static struct mdesc_mlgroup *mlgroups;
918 static int num_mlgroups;
920 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
925 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
926 u64 target = mdesc_arc_target(md, arc);
929 val = mdesc_get_property(md, target,
931 if (val && *val == cfg_handle)
937 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
940 u64 arc, candidate, best_latency = ~(u64)0;
942 candidate = MDESC_NODE_NULL;
943 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
944 u64 target = mdesc_arc_target(md, arc);
945 const char *name = mdesc_node_name(md, target);
948 if (strcmp(name, "pio-latency-group"))
951 val = mdesc_get_property(md, target, "latency", NULL);
955 if (*val < best_latency) {
961 if (candidate == MDESC_NODE_NULL)
964 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
967 int of_node_to_nid(struct device_node *dp)
969 const struct linux_prom64_registers *regs;
970 struct mdesc_handle *md;
975 /* This is the right thing to do on currently supported
976 * SUN4U NUMA platforms as well, as the PCI controller does
977 * not sit behind any particular memory controller.
982 regs = of_get_property(dp, "reg", NULL);
986 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
992 mdesc_for_each_node_by_name(md, grp, "group") {
993 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1005 static void __init add_node_ranges(void)
1007 struct memblock_region *reg;
1009 for_each_memblock(memory, reg) {
1010 unsigned long size = reg->size;
1011 unsigned long start, end;
1015 while (start < end) {
1016 unsigned long this_end;
1019 this_end = memblock_nid_range(start, end, &nid);
1021 numadbg("Setting memblock NUMA node nid[%d] "
1022 "start[%lx] end[%lx]\n",
1023 nid, start, this_end);
1025 memblock_set_node(start, this_end - start,
1026 &memblock.memory, nid);
1032 static int __init grab_mlgroups(struct mdesc_handle *md)
1034 unsigned long paddr;
1038 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1043 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1048 mlgroups = __va(paddr);
1049 num_mlgroups = count;
1052 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1053 struct mdesc_mlgroup *m = &mlgroups[count++];
1058 val = mdesc_get_property(md, node, "latency", NULL);
1060 val = mdesc_get_property(md, node, "address-match", NULL);
1062 val = mdesc_get_property(md, node, "address-mask", NULL);
1065 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1066 "match[%llx] mask[%llx]\n",
1067 count - 1, m->node, m->latency, m->match, m->mask);
1073 static int __init grab_mblocks(struct mdesc_handle *md)
1075 unsigned long paddr;
1079 mdesc_for_each_node_by_name(md, node, "mblock")
1084 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1089 mblocks = __va(paddr);
1090 num_mblocks = count;
1093 mdesc_for_each_node_by_name(md, node, "mblock") {
1094 struct mdesc_mblock *m = &mblocks[count++];
1097 val = mdesc_get_property(md, node, "base", NULL);
1099 val = mdesc_get_property(md, node, "size", NULL);
1101 val = mdesc_get_property(md, node,
1102 "address-congruence-offset", NULL);
1104 /* The address-congruence-offset property is optional.
1105 * Explicity zero it be identifty this.
1112 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1113 count - 1, m->base, m->size, m->offset);
1119 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1120 u64 grp, cpumask_t *mask)
1124 cpumask_clear(mask);
1126 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1127 u64 target = mdesc_arc_target(md, arc);
1128 const char *name = mdesc_node_name(md, target);
1131 if (strcmp(name, "cpu"))
1133 id = mdesc_get_property(md, target, "id", NULL);
1134 if (*id < nr_cpu_ids)
1135 cpumask_set_cpu(*id, mask);
1139 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1143 for (i = 0; i < num_mlgroups; i++) {
1144 struct mdesc_mlgroup *m = &mlgroups[i];
1145 if (m->node == node)
1151 int __node_distance(int from, int to)
1153 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1154 pr_warn("Returning default NUMA distance value for %d->%d\n",
1156 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1158 return numa_latency[from][to];
1161 static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1165 for (i = 0; i < MAX_NUMNODES; i++) {
1166 struct node_mem_mask *n = &node_masks[i];
1168 if ((grp->mask == n->mask) && (grp->match == n->val))
1174 static void find_numa_latencies_for_group(struct mdesc_handle *md, u64 grp,
1179 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1181 u64 target = mdesc_arc_target(md, arc);
1182 struct mdesc_mlgroup *m = find_mlgroup(target);
1186 tnode = find_best_numa_node_for_mlgroup(m);
1187 if (tnode == MAX_NUMNODES)
1189 numa_latency[index][tnode] = m->latency;
1193 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1196 struct mdesc_mlgroup *candidate = NULL;
1197 u64 arc, best_latency = ~(u64)0;
1198 struct node_mem_mask *n;
1200 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1201 u64 target = mdesc_arc_target(md, arc);
1202 struct mdesc_mlgroup *m = find_mlgroup(target);
1205 if (m->latency < best_latency) {
1207 best_latency = m->latency;
1213 if (num_node_masks != index) {
1214 printk(KERN_ERR "Inconsistent NUMA state, "
1215 "index[%d] != num_node_masks[%d]\n",
1216 index, num_node_masks);
1220 n = &node_masks[num_node_masks++];
1222 n->mask = candidate->mask;
1223 n->val = candidate->match;
1225 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1226 index, n->mask, n->val, candidate->latency);
1231 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1237 numa_parse_mdesc_group_cpus(md, grp, &mask);
1239 for_each_cpu(cpu, &mask)
1240 numa_cpu_lookup_table[cpu] = index;
1241 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1244 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1245 for_each_cpu(cpu, &mask)
1250 return numa_attach_mlgroup(md, grp, index);
1253 static int __init numa_parse_mdesc(void)
1255 struct mdesc_handle *md = mdesc_grab();
1256 int i, j, err, count;
1259 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1260 if (node == MDESC_NODE_NULL) {
1265 err = grab_mblocks(md);
1269 err = grab_mlgroups(md);
1274 mdesc_for_each_node_by_name(md, node, "group") {
1275 err = numa_parse_mdesc_group(md, node, count);
1282 mdesc_for_each_node_by_name(md, node, "group") {
1283 find_numa_latencies_for_group(md, node, count);
1287 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1288 for (i = 0; i < MAX_NUMNODES; i++) {
1289 u64 self_latency = numa_latency[i][i];
1291 for (j = 0; j < MAX_NUMNODES; j++) {
1292 numa_latency[i][j] =
1293 (numa_latency[i][j] * LOCAL_DISTANCE) /
1300 for (i = 0; i < num_node_masks; i++) {
1301 allocate_node_data(i);
1311 static int __init numa_parse_jbus(void)
1313 unsigned long cpu, index;
1315 /* NUMA node id is encoded in bits 36 and higher, and there is
1316 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1319 for_each_present_cpu(cpu) {
1320 numa_cpu_lookup_table[cpu] = index;
1321 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1322 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1323 node_masks[index].val = cpu << 36UL;
1327 num_node_masks = index;
1331 for (index = 0; index < num_node_masks; index++) {
1332 allocate_node_data(index);
1333 node_set_online(index);
1339 static int __init numa_parse_sun4u(void)
1341 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1344 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1345 if ((ver >> 32UL) == __JALAPENO_ID ||
1346 (ver >> 32UL) == __SERRANO_ID)
1347 return numa_parse_jbus();
1352 static int __init bootmem_init_numa(void)
1357 numadbg("bootmem_init_numa()\n");
1359 /* Some sane defaults for numa latency values */
1360 for (i = 0; i < MAX_NUMNODES; i++) {
1361 for (j = 0; j < MAX_NUMNODES; j++)
1362 numa_latency[i][j] = (i == j) ?
1363 LOCAL_DISTANCE : REMOTE_DISTANCE;
1367 if (tlb_type == hypervisor)
1368 err = numa_parse_mdesc();
1370 err = numa_parse_sun4u();
1377 static int bootmem_init_numa(void)
1384 static void __init bootmem_init_nonnuma(void)
1386 unsigned long top_of_ram = memblock_end_of_DRAM();
1387 unsigned long total_ram = memblock_phys_mem_size();
1389 numadbg("bootmem_init_nonnuma()\n");
1391 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1392 top_of_ram, total_ram);
1393 printk(KERN_INFO "Memory hole size: %ldMB\n",
1394 (top_of_ram - total_ram) >> 20);
1396 init_node_masks_nonnuma();
1397 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1398 allocate_node_data(0);
1402 static unsigned long __init bootmem_init(unsigned long phys_base)
1404 unsigned long end_pfn;
1406 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1407 max_pfn = max_low_pfn = end_pfn;
1408 min_low_pfn = (phys_base >> PAGE_SHIFT);
1410 if (bootmem_init_numa() < 0)
1411 bootmem_init_nonnuma();
1413 /* Dump memblock with node info. */
1414 memblock_dump_all();
1416 /* XXX cpu notifier XXX */
1418 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1424 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1425 static int pall_ents __initdata;
1427 static unsigned long max_phys_bits = 40;
1429 bool kern_addr_valid(unsigned long addr)
1436 if ((long)addr < 0L) {
1437 unsigned long pa = __pa(addr);
1439 if ((addr >> max_phys_bits) != 0UL)
1442 return pfn_valid(pa >> PAGE_SHIFT);
1445 if (addr >= (unsigned long) KERNBASE &&
1446 addr < (unsigned long)&_end)
1449 pgd = pgd_offset_k(addr);
1453 pud = pud_offset(pgd, addr);
1457 if (pud_large(*pud))
1458 return pfn_valid(pud_pfn(*pud));
1460 pmd = pmd_offset(pud, addr);
1464 if (pmd_large(*pmd))
1465 return pfn_valid(pmd_pfn(*pmd));
1467 pte = pte_offset_kernel(pmd, addr);
1471 return pfn_valid(pte_pfn(*pte));
1473 EXPORT_SYMBOL(kern_addr_valid);
1475 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1479 const unsigned long mask16gb = (1UL << 34) - 1UL;
1480 u64 pte_val = vstart;
1482 /* Each PUD is 8GB */
1483 if ((vstart & mask16gb) ||
1484 (vend - vstart <= mask16gb)) {
1485 pte_val ^= kern_linear_pte_xor[2];
1486 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1488 return vstart + PUD_SIZE;
1491 pte_val ^= kern_linear_pte_xor[3];
1492 pte_val |= _PAGE_PUD_HUGE;
1494 vend = vstart + mask16gb + 1UL;
1495 while (vstart < vend) {
1496 pud_val(*pud) = pte_val;
1498 pte_val += PUD_SIZE;
1505 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1508 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1514 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1518 const unsigned long mask256mb = (1UL << 28) - 1UL;
1519 const unsigned long mask2gb = (1UL << 31) - 1UL;
1520 u64 pte_val = vstart;
1522 /* Each PMD is 8MB */
1523 if ((vstart & mask256mb) ||
1524 (vend - vstart <= mask256mb)) {
1525 pte_val ^= kern_linear_pte_xor[0];
1526 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1528 return vstart + PMD_SIZE;
1531 if ((vstart & mask2gb) ||
1532 (vend - vstart <= mask2gb)) {
1533 pte_val ^= kern_linear_pte_xor[1];
1534 pte_val |= _PAGE_PMD_HUGE;
1535 vend = vstart + mask256mb + 1UL;
1537 pte_val ^= kern_linear_pte_xor[2];
1538 pte_val |= _PAGE_PMD_HUGE;
1539 vend = vstart + mask2gb + 1UL;
1542 while (vstart < vend) {
1543 pmd_val(*pmd) = pte_val;
1545 pte_val += PMD_SIZE;
1553 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1556 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1562 static unsigned long __ref kernel_map_range(unsigned long pstart,
1563 unsigned long pend, pgprot_t prot,
1566 unsigned long vstart = PAGE_OFFSET + pstart;
1567 unsigned long vend = PAGE_OFFSET + pend;
1568 unsigned long alloc_bytes = 0UL;
1570 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1571 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1576 while (vstart < vend) {
1577 unsigned long this_end, paddr = __pa(vstart);
1578 pgd_t *pgd = pgd_offset_k(vstart);
1583 if (pgd_none(*pgd)) {
1586 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1587 alloc_bytes += PAGE_SIZE;
1588 pgd_populate(&init_mm, pgd, new);
1590 pud = pud_offset(pgd, vstart);
1591 if (pud_none(*pud)) {
1594 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1595 vstart = kernel_map_hugepud(vstart, vend, pud);
1598 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1599 alloc_bytes += PAGE_SIZE;
1600 pud_populate(&init_mm, pud, new);
1603 pmd = pmd_offset(pud, vstart);
1604 if (pmd_none(*pmd)) {
1607 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1608 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1611 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1612 alloc_bytes += PAGE_SIZE;
1613 pmd_populate_kernel(&init_mm, pmd, new);
1616 pte = pte_offset_kernel(pmd, vstart);
1617 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1618 if (this_end > vend)
1621 while (vstart < this_end) {
1622 pte_val(*pte) = (paddr | pgprot_val(prot));
1624 vstart += PAGE_SIZE;
1633 static void __init flush_all_kernel_tsbs(void)
1637 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1638 struct tsb *ent = &swapper_tsb[i];
1640 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1642 #ifndef CONFIG_DEBUG_PAGEALLOC
1643 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1644 struct tsb *ent = &swapper_4m_tsb[i];
1646 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1651 extern unsigned int kvmap_linear_patch[1];
1653 static void __init kernel_physical_mapping_init(void)
1655 unsigned long i, mem_alloced = 0UL;
1656 bool use_huge = true;
1658 #ifdef CONFIG_DEBUG_PAGEALLOC
1661 for (i = 0; i < pall_ents; i++) {
1662 unsigned long phys_start, phys_end;
1664 phys_start = pall[i].phys_addr;
1665 phys_end = phys_start + pall[i].reg_size;
1667 mem_alloced += kernel_map_range(phys_start, phys_end,
1668 PAGE_KERNEL, use_huge);
1671 printk("Allocated %ld bytes for kernel page tables.\n",
1674 kvmap_linear_patch[0] = 0x01000000; /* nop */
1675 flushi(&kvmap_linear_patch[0]);
1677 flush_all_kernel_tsbs();
1682 #ifdef CONFIG_DEBUG_PAGEALLOC
1683 void __kernel_map_pages(struct page *page, int numpages, int enable)
1685 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1686 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1688 kernel_map_range(phys_start, phys_end,
1689 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1691 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1692 PAGE_OFFSET + phys_end);
1694 /* we should perform an IPI and flush all tlbs,
1695 * but that can deadlock->flush only current cpu.
1697 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1698 PAGE_OFFSET + phys_end);
1702 unsigned long __init find_ecache_flush_span(unsigned long size)
1706 for (i = 0; i < pavail_ents; i++) {
1707 if (pavail[i].reg_size >= size)
1708 return pavail[i].phys_addr;
1714 unsigned long PAGE_OFFSET;
1715 EXPORT_SYMBOL(PAGE_OFFSET);
1717 unsigned long VMALLOC_END = 0x0000010000000000UL;
1718 EXPORT_SYMBOL(VMALLOC_END);
1720 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1721 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1723 static void __init setup_page_offset(void)
1725 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1726 /* Cheetah/Panther support a full 64-bit virtual
1727 * address, so we can use all that our page tables
1730 sparc64_va_hole_top = 0xfff0000000000000UL;
1731 sparc64_va_hole_bottom = 0x0010000000000000UL;
1734 } else if (tlb_type == hypervisor) {
1735 switch (sun4v_chip_type) {
1736 case SUN4V_CHIP_NIAGARA1:
1737 case SUN4V_CHIP_NIAGARA2:
1738 /* T1 and T2 support 48-bit virtual addresses. */
1739 sparc64_va_hole_top = 0xffff800000000000UL;
1740 sparc64_va_hole_bottom = 0x0000800000000000UL;
1744 case SUN4V_CHIP_NIAGARA3:
1745 /* T3 supports 48-bit virtual addresses. */
1746 sparc64_va_hole_top = 0xffff800000000000UL;
1747 sparc64_va_hole_bottom = 0x0000800000000000UL;
1751 case SUN4V_CHIP_NIAGARA4:
1752 case SUN4V_CHIP_NIAGARA5:
1753 case SUN4V_CHIP_SPARC64X:
1754 case SUN4V_CHIP_SPARC_M6:
1755 /* T4 and later support 52-bit virtual addresses. */
1756 sparc64_va_hole_top = 0xfff8000000000000UL;
1757 sparc64_va_hole_bottom = 0x0008000000000000UL;
1760 case SUN4V_CHIP_SPARC_M7:
1761 case SUN4V_CHIP_SPARC_SN:
1763 /* M7 and later support 52-bit virtual addresses. */
1764 sparc64_va_hole_top = 0xfff8000000000000UL;
1765 sparc64_va_hole_bottom = 0x0008000000000000UL;
1771 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1772 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1777 PAGE_OFFSET = sparc64_va_hole_top;
1778 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1779 (sparc64_va_hole_bottom >> 2));
1781 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1782 PAGE_OFFSET, max_phys_bits);
1783 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1784 VMALLOC_START, VMALLOC_END);
1785 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1786 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1789 static void __init tsb_phys_patch(void)
1791 struct tsb_ldquad_phys_patch_entry *pquad;
1792 struct tsb_phys_patch_entry *p;
1794 pquad = &__tsb_ldquad_phys_patch;
1795 while (pquad < &__tsb_ldquad_phys_patch_end) {
1796 unsigned long addr = pquad->addr;
1798 if (tlb_type == hypervisor)
1799 *(unsigned int *) addr = pquad->sun4v_insn;
1801 *(unsigned int *) addr = pquad->sun4u_insn;
1803 __asm__ __volatile__("flush %0"
1810 p = &__tsb_phys_patch;
1811 while (p < &__tsb_phys_patch_end) {
1812 unsigned long addr = p->addr;
1814 *(unsigned int *) addr = p->insn;
1816 __asm__ __volatile__("flush %0"
1824 /* Don't mark as init, we give this to the Hypervisor. */
1825 #ifndef CONFIG_DEBUG_PAGEALLOC
1826 #define NUM_KTSB_DESCR 2
1828 #define NUM_KTSB_DESCR 1
1830 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1832 /* The swapper TSBs are loaded with a base sequence of:
1834 * sethi %uhi(SYMBOL), REG1
1835 * sethi %hi(SYMBOL), REG2
1836 * or REG1, %ulo(SYMBOL), REG1
1837 * or REG2, %lo(SYMBOL), REG2
1838 * sllx REG1, 32, REG1
1839 * or REG1, REG2, REG1
1841 * When we use physical addressing for the TSB accesses, we patch the
1842 * first four instructions in the above sequence.
1845 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1847 unsigned long high_bits, low_bits;
1849 high_bits = (pa >> 32) & 0xffffffff;
1850 low_bits = (pa >> 0) & 0xffffffff;
1852 while (start < end) {
1853 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1855 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1856 __asm__ __volatile__("flush %0" : : "r" (ia));
1858 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1859 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1861 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1862 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
1864 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1865 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
1871 static void ktsb_phys_patch(void)
1873 extern unsigned int __swapper_tsb_phys_patch;
1874 extern unsigned int __swapper_tsb_phys_patch_end;
1875 unsigned long ktsb_pa;
1877 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1878 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1879 &__swapper_tsb_phys_patch_end, ktsb_pa);
1880 #ifndef CONFIG_DEBUG_PAGEALLOC
1882 extern unsigned int __swapper_4m_tsb_phys_patch;
1883 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1884 ktsb_pa = (kern_base +
1885 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1886 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1887 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1892 static void __init sun4v_ktsb_init(void)
1894 unsigned long ktsb_pa;
1896 /* First KTSB for PAGE_SIZE mappings. */
1897 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1899 switch (PAGE_SIZE) {
1902 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1903 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1907 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1908 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1912 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1913 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1916 case 4 * 1024 * 1024:
1917 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1918 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1922 ktsb_descr[0].assoc = 1;
1923 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1924 ktsb_descr[0].ctx_idx = 0;
1925 ktsb_descr[0].tsb_base = ktsb_pa;
1926 ktsb_descr[0].resv = 0;
1928 #ifndef CONFIG_DEBUG_PAGEALLOC
1929 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1930 ktsb_pa = (kern_base +
1931 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1933 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1934 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1935 HV_PGSZ_MASK_256MB |
1937 HV_PGSZ_MASK_16GB) &
1939 ktsb_descr[1].assoc = 1;
1940 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1941 ktsb_descr[1].ctx_idx = 0;
1942 ktsb_descr[1].tsb_base = ktsb_pa;
1943 ktsb_descr[1].resv = 0;
1947 void sun4v_ktsb_register(void)
1949 unsigned long pa, ret;
1951 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1953 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1955 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1956 "errors with %lx\n", pa, ret);
1961 static void __init sun4u_linear_pte_xor_finalize(void)
1963 #ifndef CONFIG_DEBUG_PAGEALLOC
1964 /* This is where we would add Panther support for
1965 * 32MB and 256MB pages.
1970 static void __init sun4v_linear_pte_xor_finalize(void)
1972 unsigned long pagecv_flag;
1974 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1975 * enables MCD error. Do not set bit 9 on M7 processor.
1977 switch (sun4v_chip_type) {
1978 case SUN4V_CHIP_SPARC_M7:
1979 case SUN4V_CHIP_SPARC_SN:
1983 pagecv_flag = _PAGE_CV_4V;
1986 #ifndef CONFIG_DEBUG_PAGEALLOC
1987 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1988 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1990 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
1991 _PAGE_P_4V | _PAGE_W_4V);
1993 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1996 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1997 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1999 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2000 _PAGE_P_4V | _PAGE_W_4V);
2002 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2005 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2006 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2008 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2009 _PAGE_P_4V | _PAGE_W_4V);
2011 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2016 /* paging_init() sets up the page tables */
2018 static unsigned long last_valid_pfn;
2020 static void sun4u_pgprot_init(void);
2021 static void sun4v_pgprot_init(void);
2023 static phys_addr_t __init available_memory(void)
2025 phys_addr_t available = 0ULL;
2026 phys_addr_t pa_start, pa_end;
2029 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2031 available = available + (pa_end - pa_start);
2036 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2037 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2038 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2039 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2040 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2041 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2043 /* We need to exclude reserved regions. This exclusion will include
2044 * vmlinux and initrd. To be more precise the initrd size could be used to
2045 * compute a new lower limit because it is freed later during initialization.
2047 static void __init reduce_memory(phys_addr_t limit_ram)
2049 phys_addr_t avail_ram = available_memory();
2050 phys_addr_t pa_start, pa_end;
2053 if (limit_ram >= avail_ram)
2056 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2058 phys_addr_t region_size = pa_end - pa_start;
2059 phys_addr_t clip_start = pa_start;
2061 avail_ram = avail_ram - region_size;
2062 /* Are we consuming too much? */
2063 if (avail_ram < limit_ram) {
2064 phys_addr_t give_back = limit_ram - avail_ram;
2066 region_size = region_size - give_back;
2067 clip_start = clip_start + give_back;
2070 memblock_remove(clip_start, region_size);
2072 if (avail_ram <= limit_ram)
2078 void __init paging_init(void)
2080 unsigned long end_pfn, shift, phys_base;
2081 unsigned long real_end, i;
2084 setup_page_offset();
2086 /* These build time checkes make sure that the dcache_dirty_cpu()
2087 * page->flags usage will work.
2089 * When a page gets marked as dcache-dirty, we store the
2090 * cpu number starting at bit 32 in the page->flags. Also,
2091 * functions like clear_dcache_dirty_cpu use the cpu mask
2092 * in 13-bit signed-immediate instruction fields.
2096 * Page flags must not reach into upper 32 bits that are used
2097 * for the cpu number
2099 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2102 * The bit fields placed in the high range must not reach below
2103 * the 32 bit boundary. Otherwise we cannot place the cpu field
2104 * at the 32 bit boundary.
2106 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2107 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2109 BUILD_BUG_ON(NR_CPUS > 4096);
2111 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2112 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2114 /* Invalidate both kernel TSBs. */
2115 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2116 #ifndef CONFIG_DEBUG_PAGEALLOC
2117 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2120 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2121 * bit on M7 processor. This is a conflicting usage of the same
2122 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2123 * Detection error on all pages and this will lead to problems
2124 * later. Kernel does not run with MCD enabled and hence rest
2125 * of the required steps to fully configure memory corruption
2126 * detection are not taken. We need to ensure TTE.mcde is not
2127 * set on M7 processor. Compute the value of cacheability
2128 * flag for use later taking this into consideration.
2130 switch (sun4v_chip_type) {
2131 case SUN4V_CHIP_SPARC_M7:
2132 case SUN4V_CHIP_SPARC_SN:
2133 page_cache4v_flag = _PAGE_CP_4V;
2136 page_cache4v_flag = _PAGE_CACHE_4V;
2140 if (tlb_type == hypervisor)
2141 sun4v_pgprot_init();
2143 sun4u_pgprot_init();
2145 if (tlb_type == cheetah_plus ||
2146 tlb_type == hypervisor) {
2151 if (tlb_type == hypervisor)
2152 sun4v_patch_tlb_handlers();
2154 /* Find available physical memory...
2156 * Read it twice in order to work around a bug in openfirmware.
2157 * The call to grab this table itself can cause openfirmware to
2158 * allocate memory, which in turn can take away some space from
2159 * the list of available memory. Reading it twice makes sure
2160 * we really do get the final value.
2162 read_obp_translations();
2163 read_obp_memory("reg", &pall[0], &pall_ents);
2164 read_obp_memory("available", &pavail[0], &pavail_ents);
2165 read_obp_memory("available", &pavail[0], &pavail_ents);
2167 phys_base = 0xffffffffffffffffUL;
2168 for (i = 0; i < pavail_ents; i++) {
2169 phys_base = min(phys_base, pavail[i].phys_addr);
2170 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2173 memblock_reserve(kern_base, kern_size);
2175 find_ramdisk(phys_base);
2177 if (cmdline_memory_size)
2178 reduce_memory(cmdline_memory_size);
2180 memblock_allow_resize();
2181 memblock_dump_all();
2183 set_bit(0, mmu_context_bmap);
2185 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2187 real_end = (unsigned long)_end;
2188 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2189 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2190 num_kernel_image_mappings);
2192 /* Set kernel pgd to upper alias so physical page computations
2195 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2197 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2199 inherit_prom_mappings();
2201 /* Ok, we can use our TLB miss and window trap handlers safely. */
2206 prom_build_devicetree();
2207 of_populate_present_mask();
2209 of_fill_in_cpu_data();
2212 if (tlb_type == hypervisor) {
2214 mdesc_populate_present_mask(cpu_all_mask);
2216 mdesc_fill_in_cpu_data(cpu_all_mask);
2218 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2220 sun4v_linear_pte_xor_finalize();
2223 sun4v_ktsb_register();
2225 unsigned long impl, ver;
2227 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2228 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2230 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2231 impl = ((ver >> 32) & 0xffff);
2232 if (impl == PANTHER_IMPL)
2233 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2234 HV_PGSZ_MASK_256MB);
2236 sun4u_linear_pte_xor_finalize();
2239 /* Flush the TLBs and the 4M TSB so that the updated linear
2240 * pte XOR settings are realized for all mappings.
2243 #ifndef CONFIG_DEBUG_PAGEALLOC
2244 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2248 /* Setup bootmem... */
2249 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2251 /* Once the OF device tree and MDESC have been setup, we know
2252 * the list of possible cpus. Therefore we can allocate the
2255 for_each_possible_cpu(i) {
2256 node = cpu_to_node(i);
2258 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2261 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2266 kernel_physical_mapping_init();
2269 unsigned long max_zone_pfns[MAX_NR_ZONES];
2271 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2273 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2275 free_area_init_nodes(max_zone_pfns);
2278 printk("Booting Linux...\n");
2281 int page_in_phys_avail(unsigned long paddr)
2287 for (i = 0; i < pavail_ents; i++) {
2288 unsigned long start, end;
2290 start = pavail[i].phys_addr;
2291 end = start + pavail[i].reg_size;
2293 if (paddr >= start && paddr < end)
2296 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2298 #ifdef CONFIG_BLK_DEV_INITRD
2299 if (paddr >= __pa(initrd_start) &&
2300 paddr < __pa(PAGE_ALIGN(initrd_end)))
2307 static void __init register_page_bootmem_info(void)
2309 #ifdef CONFIG_NEED_MULTIPLE_NODES
2312 for_each_online_node(i)
2313 if (NODE_DATA(i)->node_spanned_pages)
2314 register_page_bootmem_info_node(NODE_DATA(i));
2317 void __init mem_init(void)
2319 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2321 register_page_bootmem_info();
2325 * Set up the zero page, mark it reserved, so that page count
2326 * is not manipulated when freeing the page from user ptes.
2328 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2329 if (mem_map_zero == NULL) {
2330 prom_printf("paging_init: Cannot alloc zero page.\n");
2333 mark_page_reserved(mem_map_zero);
2335 mem_init_print_info(NULL);
2337 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2338 cheetah_ecache_flush_init();
2341 void free_initmem(void)
2343 unsigned long addr, initend;
2346 /* If the physical memory maps were trimmed by kernel command
2347 * line options, don't even try freeing this initmem stuff up.
2348 * The kernel image could have been in the trimmed out region
2349 * and if so the freeing below will free invalid page structs.
2351 if (cmdline_memory_size)
2355 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2357 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2358 initend = (unsigned long)(__init_end) & PAGE_MASK;
2359 for (; addr < initend; addr += PAGE_SIZE) {
2363 ((unsigned long) __va(kern_base)) -
2364 ((unsigned long) KERNBASE));
2365 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2368 free_reserved_page(virt_to_page(page));
2372 #ifdef CONFIG_BLK_DEV_INITRD
2373 void free_initrd_mem(unsigned long start, unsigned long end)
2375 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2380 pgprot_t PAGE_KERNEL __read_mostly;
2381 EXPORT_SYMBOL(PAGE_KERNEL);
2383 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2384 pgprot_t PAGE_COPY __read_mostly;
2386 pgprot_t PAGE_SHARED __read_mostly;
2387 EXPORT_SYMBOL(PAGE_SHARED);
2389 unsigned long pg_iobits __read_mostly;
2391 unsigned long _PAGE_IE __read_mostly;
2392 EXPORT_SYMBOL(_PAGE_IE);
2394 unsigned long _PAGE_E __read_mostly;
2395 EXPORT_SYMBOL(_PAGE_E);
2397 unsigned long _PAGE_CACHE __read_mostly;
2398 EXPORT_SYMBOL(_PAGE_CACHE);
2400 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2401 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2404 unsigned long pte_base;
2406 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2407 _PAGE_CP_4U | _PAGE_CV_4U |
2408 _PAGE_P_4U | _PAGE_W_4U);
2409 if (tlb_type == hypervisor)
2410 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2411 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2413 pte_base |= _PAGE_PMD_HUGE;
2415 vstart = vstart & PMD_MASK;
2416 vend = ALIGN(vend, PMD_SIZE);
2417 for (; vstart < vend; vstart += PMD_SIZE) {
2418 pgd_t *pgd = pgd_offset_k(vstart);
2423 if (pgd_none(*pgd)) {
2424 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2428 pgd_populate(&init_mm, pgd, new);
2431 pud = pud_offset(pgd, vstart);
2432 if (pud_none(*pud)) {
2433 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2437 pud_populate(&init_mm, pud, new);
2440 pmd = pmd_offset(pud, vstart);
2442 pte = pmd_val(*pmd);
2443 if (!(pte & _PAGE_VALID)) {
2444 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2449 pmd_val(*pmd) = pte_base | __pa(block);
2456 void vmemmap_free(unsigned long start, unsigned long end)
2459 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2461 static void prot_init_common(unsigned long page_none,
2462 unsigned long page_shared,
2463 unsigned long page_copy,
2464 unsigned long page_readonly,
2465 unsigned long page_exec_bit)
2467 PAGE_COPY = __pgprot(page_copy);
2468 PAGE_SHARED = __pgprot(page_shared);
2470 protection_map[0x0] = __pgprot(page_none);
2471 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2472 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2473 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2474 protection_map[0x4] = __pgprot(page_readonly);
2475 protection_map[0x5] = __pgprot(page_readonly);
2476 protection_map[0x6] = __pgprot(page_copy);
2477 protection_map[0x7] = __pgprot(page_copy);
2478 protection_map[0x8] = __pgprot(page_none);
2479 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2480 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2481 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2482 protection_map[0xc] = __pgprot(page_readonly);
2483 protection_map[0xd] = __pgprot(page_readonly);
2484 protection_map[0xe] = __pgprot(page_shared);
2485 protection_map[0xf] = __pgprot(page_shared);
2488 static void __init sun4u_pgprot_init(void)
2490 unsigned long page_none, page_shared, page_copy, page_readonly;
2491 unsigned long page_exec_bit;
2494 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2495 _PAGE_CACHE_4U | _PAGE_P_4U |
2496 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2498 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2499 _PAGE_CACHE_4U | _PAGE_P_4U |
2500 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2501 _PAGE_EXEC_4U | _PAGE_L_4U);
2503 _PAGE_IE = _PAGE_IE_4U;
2504 _PAGE_E = _PAGE_E_4U;
2505 _PAGE_CACHE = _PAGE_CACHE_4U;
2507 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2508 __ACCESS_BITS_4U | _PAGE_E_4U);
2510 #ifdef CONFIG_DEBUG_PAGEALLOC
2511 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2513 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2516 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2517 _PAGE_P_4U | _PAGE_W_4U);
2519 for (i = 1; i < 4; i++)
2520 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2522 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2523 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2524 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2527 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2528 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2529 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2530 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2531 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2532 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2533 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2535 page_exec_bit = _PAGE_EXEC_4U;
2537 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2541 static void __init sun4v_pgprot_init(void)
2543 unsigned long page_none, page_shared, page_copy, page_readonly;
2544 unsigned long page_exec_bit;
2547 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2548 page_cache4v_flag | _PAGE_P_4V |
2549 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2551 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2553 _PAGE_IE = _PAGE_IE_4V;
2554 _PAGE_E = _PAGE_E_4V;
2555 _PAGE_CACHE = page_cache4v_flag;
2557 #ifdef CONFIG_DEBUG_PAGEALLOC
2558 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2560 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2563 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2566 for (i = 1; i < 4; i++)
2567 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2569 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2570 __ACCESS_BITS_4V | _PAGE_E_4V);
2572 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2573 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2574 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2575 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2577 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2578 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2579 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2580 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2581 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2582 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2583 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2585 page_exec_bit = _PAGE_EXEC_4V;
2587 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2591 unsigned long pte_sz_bits(unsigned long sz)
2593 if (tlb_type == hypervisor) {
2597 return _PAGE_SZ8K_4V;
2599 return _PAGE_SZ64K_4V;
2601 return _PAGE_SZ512K_4V;
2602 case 4 * 1024 * 1024:
2603 return _PAGE_SZ4MB_4V;
2609 return _PAGE_SZ8K_4U;
2611 return _PAGE_SZ64K_4U;
2613 return _PAGE_SZ512K_4U;
2614 case 4 * 1024 * 1024:
2615 return _PAGE_SZ4MB_4U;
2620 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2624 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2625 pte_val(pte) |= (((unsigned long)space) << 32);
2626 pte_val(pte) |= pte_sz_bits(page_size);
2631 static unsigned long kern_large_tte(unsigned long paddr)
2635 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2636 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2637 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2638 if (tlb_type == hypervisor)
2639 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2640 page_cache4v_flag | _PAGE_P_4V |
2641 _PAGE_EXEC_4V | _PAGE_W_4V);
2646 /* If not locked, zap it. */
2647 void __flush_tlb_all(void)
2649 unsigned long pstate;
2652 __asm__ __volatile__("flushw\n\t"
2653 "rdpr %%pstate, %0\n\t"
2654 "wrpr %0, %1, %%pstate"
2657 if (tlb_type == hypervisor) {
2658 sun4v_mmu_demap_all();
2659 } else if (tlb_type == spitfire) {
2660 for (i = 0; i < 64; i++) {
2661 /* Spitfire Errata #32 workaround */
2662 /* NOTE: Always runs on spitfire, so no
2663 * cheetah+ page size encodings.
2665 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2669 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2671 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2672 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2675 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2676 spitfire_put_dtlb_data(i, 0x0UL);
2679 /* Spitfire Errata #32 workaround */
2680 /* NOTE: Always runs on spitfire, so no
2681 * cheetah+ page size encodings.
2683 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2687 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2689 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2690 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2693 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2694 spitfire_put_itlb_data(i, 0x0UL);
2697 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2698 cheetah_flush_dtlb_all();
2699 cheetah_flush_itlb_all();
2701 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2705 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2706 unsigned long address)
2708 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
2712 pte = (pte_t *) page_address(page);
2717 pgtable_t pte_alloc_one(struct mm_struct *mm,
2718 unsigned long address)
2720 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
2723 if (!pgtable_page_ctor(page)) {
2724 free_hot_cold_page(page, 0);
2727 return (pte_t *) page_address(page);
2730 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2732 free_page((unsigned long)pte);
2735 static void __pte_free(pgtable_t pte)
2737 struct page *page = virt_to_page(pte);
2739 pgtable_page_dtor(page);
2743 void pte_free(struct mm_struct *mm, pgtable_t pte)
2748 void pgtable_free(void *table, bool is_page)
2753 kmem_cache_free(pgtable_cache, table);
2756 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2757 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2760 unsigned long pte, flags;
2761 struct mm_struct *mm;
2764 if (!pmd_large(entry) || !pmd_young(entry))
2767 pte = pmd_val(entry);
2769 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2770 if (!(pte & _PAGE_VALID))
2773 /* We are fabricating 8MB pages using 4MB real hw pages. */
2774 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2778 spin_lock_irqsave(&mm->context.lock, flags);
2780 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2781 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2784 spin_unlock_irqrestore(&mm->context.lock, flags);
2786 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2788 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2789 static void context_reload(void *__data)
2791 struct mm_struct *mm = __data;
2793 if (mm == current->mm)
2794 load_secondary_context(mm);
2797 void hugetlb_setup(struct pt_regs *regs)
2799 struct mm_struct *mm = current->mm;
2800 struct tsb_config *tp;
2802 if (faulthandler_disabled() || !mm) {
2803 const struct exception_table_entry *entry;
2805 entry = search_exception_tables(regs->tpc);
2807 regs->tpc = entry->fixup;
2808 regs->tnpc = regs->tpc + 4;
2811 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2812 die_if_kernel("HugeTSB in atomic", regs);
2815 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2816 if (likely(tp->tsb == NULL))
2817 tsb_grow(mm, MM_TSB_HUGE, 0);
2819 tsb_context_switch(mm);
2822 /* On UltraSPARC-III+ and later, configure the second half of
2823 * the Data-TLB for huge pages.
2825 if (tlb_type == cheetah_plus) {
2826 bool need_context_reload = false;
2829 spin_lock_irq(&ctx_alloc_lock);
2830 ctx = mm->context.sparc64_ctx_val;
2831 ctx &= ~CTX_PGSZ_MASK;
2832 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2833 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2835 if (ctx != mm->context.sparc64_ctx_val) {
2836 /* When changing the page size fields, we
2837 * must perform a context flush so that no
2838 * stale entries match. This flush must
2839 * occur with the original context register
2842 do_flush_tlb_mm(mm);
2844 /* Reload the context register of all processors
2845 * also executing in this address space.
2847 mm->context.sparc64_ctx_val = ctx;
2848 need_context_reload = true;
2850 spin_unlock_irq(&ctx_alloc_lock);
2852 if (need_context_reload)
2853 on_each_cpu(context_reload, mm, 0);
2858 static struct resource code_resource = {
2859 .name = "Kernel code",
2860 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2863 static struct resource data_resource = {
2864 .name = "Kernel data",
2865 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2868 static struct resource bss_resource = {
2869 .name = "Kernel bss",
2870 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2873 static inline resource_size_t compute_kern_paddr(void *addr)
2875 return (resource_size_t) (addr - KERNBASE + kern_base);
2878 static void __init kernel_lds_init(void)
2880 code_resource.start = compute_kern_paddr(_text);
2881 code_resource.end = compute_kern_paddr(_etext - 1);
2882 data_resource.start = compute_kern_paddr(_etext);
2883 data_resource.end = compute_kern_paddr(_edata - 1);
2884 bss_resource.start = compute_kern_paddr(__bss_start);
2885 bss_resource.end = compute_kern_paddr(_end - 1);
2888 static int __init report_memory(void)
2891 struct resource *res;
2895 for (i = 0; i < pavail_ents; i++) {
2896 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2899 pr_warn("Failed to allocate source.\n");
2903 res->name = "System RAM";
2904 res->start = pavail[i].phys_addr;
2905 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2906 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
2908 if (insert_resource(&iomem_resource, res) < 0) {
2909 pr_warn("Resource insertion failed.\n");
2913 insert_resource(res, &code_resource);
2914 insert_resource(res, &data_resource);
2915 insert_resource(res, &bss_resource);
2920 arch_initcall(report_memory);
2923 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2925 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2928 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2930 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2931 if (start < LOW_OBP_ADDRESS) {
2932 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2933 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2935 if (end > HI_OBP_ADDRESS) {
2936 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2937 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2940 flush_tsb_kernel_range(start, end);
2941 do_flush_tlb_kernel_range(start, end);