2 * ultra.S: Don't expand these all over the place...
4 * Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
8 #include <asm/pgtable.h>
10 #include <asm/spitfire.h>
11 #include <asm/mmu_context.h>
15 #include <asm/thread_info.h>
16 #include <asm/cacheflush.h>
17 #include <asm/hypervisor.h>
18 #include <asm/cpudata.h>
20 /* Basically, most of the Spitfire vs. Cheetah madness
21 * has to do with the fact that Cheetah does not support
22 * IMMU flushes out of the secondary context. Someone needs
23 * to throw a south lake birthday party for the folks
24 * in Microelectronics who refused to fix this shit.
27 /* This file is meant to be read efficiently by the CPU, not humans.
28 * Staraj sie tego nikomu nie pierdolnac...
33 __flush_tlb_mm: /* 19 insns */
34 /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
35 ldxa [%o1] ASI_DMMU, %g2
37 bne,pn %icc, __spitfire_flush_tlb_mm_slow
39 stxa %g0, [%g3] ASI_DMMU_DEMAP
40 stxa %g0, [%g3] ASI_IMMU_DEMAP
41 sethi %hi(KERNBASE), %g3
56 .globl __flush_tlb_page
57 __flush_tlb_page: /* 22 insns */
58 /* %o0 = context, %o1 = vaddr */
60 andn %g7, PSTATE_IE, %g2
62 mov SECONDARY_CONTEXT, %o4
63 ldxa [%o4] ASI_DMMU, %g2
64 stxa %o0, [%o4] ASI_DMMU
69 stxa %g0, [%o3] ASI_IMMU_DEMAP
70 1: stxa %g0, [%o3] ASI_DMMU_DEMAP
72 stxa %g2, [%o4] ASI_DMMU
73 sethi %hi(KERNBASE), %o4
76 wrpr %g7, 0x0, %pstate
83 .globl __flush_tlb_pending
84 __flush_tlb_pending: /* 27 insns */
85 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
88 andn %g7, PSTATE_IE, %g2
90 mov SECONDARY_CONTEXT, %o4
91 ldxa [%o4] ASI_DMMU, %g2
92 stxa %o0, [%o4] ASI_DMMU
93 1: sub %o1, (1 << 3), %o1
99 stxa %g0, [%o3] ASI_IMMU_DEMAP
100 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
104 stxa %g2, [%o4] ASI_DMMU
105 sethi %hi(KERNBASE), %o4
108 wrpr %g7, 0x0, %pstate
115 .globl __flush_tlb_kernel_range
116 __flush_tlb_kernel_range: /* 19 insns */
117 /* %o0=start, %o1=end */
120 sethi %hi(PAGE_SIZE), %o4
123 or %o0, 0x20, %o0 ! Nucleus
124 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
125 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
129 2: sethi %hi(KERNBASE), %o3
138 __spitfire_flush_tlb_mm_slow:
140 wrpr %g1, PSTATE_IE, %pstate
141 stxa %o0, [%o1] ASI_DMMU
142 stxa %g0, [%g3] ASI_DMMU_DEMAP
143 stxa %g0, [%g3] ASI_IMMU_DEMAP
145 stxa %g2, [%o1] ASI_DMMU
146 sethi %hi(KERNBASE), %o1
152 * The following code flushes one page_size worth.
154 .section .kprobes.text, "ax"
156 .globl __flush_icache_page
157 __flush_icache_page: /* %o0 = phys_page */
158 srlx %o0, PAGE_SHIFT, %o0
159 sethi %hi(PAGE_OFFSET), %g1
160 sllx %o0, PAGE_SHIFT, %o0
161 sethi %hi(PAGE_SIZE), %g2
162 ldx [%g1 + %lo(PAGE_OFFSET)], %g1
164 1: subcc %g2, 32, %g2
170 #ifdef DCACHE_ALIASING_POSSIBLE
172 #if (PAGE_SHIFT != 13)
173 #error only page shift of 13 is supported by dcache flush
176 #define DTAG_MASK 0x3
178 /* This routine is Spitfire specific so the hardcoded
179 * D-cache size and line-size are OK.
182 .globl __flush_dcache_page
183 __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
184 sethi %hi(PAGE_OFFSET), %g1
185 ldx [%g1 + %lo(PAGE_OFFSET)], %g1
186 sub %o0, %g1, %o0 ! physical address
187 srlx %o0, 11, %o0 ! make D-cache TAG
188 sethi %hi(1 << 14), %o2 ! D-cache size
189 sub %o2, (1 << 5), %o2 ! D-cache line size
190 1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
191 andcc %o3, DTAG_MASK, %g0 ! Valid?
192 be,pn %xcc, 2f ! Nope, branch
193 andn %o3, DTAG_MASK, %o3 ! Clear valid bits
194 cmp %o3, %o0 ! TAG match?
195 bne,pt %xcc, 2f ! Nope, branch
197 stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
200 sub %o2, (1 << 5), %o2 ! D-cache line size
202 /* The I-cache does not snoop local stores so we
203 * better flush that too when necessary.
205 brnz,pt %o1, __flush_icache_page
210 #endif /* DCACHE_ALIASING_POSSIBLE */
214 /* Cheetah specific versions, patched at boot time. */
215 __cheetah_flush_tlb_mm: /* 19 insns */
217 andn %g7, PSTATE_IE, %g2
218 wrpr %g2, 0x0, %pstate
220 mov PRIMARY_CONTEXT, %o2
222 ldxa [%o2] ASI_DMMU, %g2
223 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1
224 sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1
225 or %o0, %o1, %o0 /* Preserve nucleus page size fields */
226 stxa %o0, [%o2] ASI_DMMU
227 stxa %g0, [%g3] ASI_DMMU_DEMAP
228 stxa %g0, [%g3] ASI_IMMU_DEMAP
229 stxa %g2, [%o2] ASI_DMMU
230 sethi %hi(KERNBASE), %o2
234 wrpr %g7, 0x0, %pstate
236 __cheetah_flush_tlb_page: /* 22 insns */
237 /* %o0 = context, %o1 = vaddr */
239 andn %g7, PSTATE_IE, %g2
240 wrpr %g2, 0x0, %pstate
242 mov PRIMARY_CONTEXT, %o4
243 ldxa [%o4] ASI_DMMU, %g2
244 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
245 sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
246 or %o0, %o3, %o0 /* Preserve nucleus page size fields */
247 stxa %o0, [%o4] ASI_DMMU
251 stxa %g0, [%o3] ASI_IMMU_DEMAP
252 1: stxa %g0, [%o3] ASI_DMMU_DEMAP
254 stxa %g2, [%o4] ASI_DMMU
255 sethi %hi(KERNBASE), %o4
259 wrpr %g7, 0x0, %pstate
261 __cheetah_flush_tlb_pending: /* 27 insns */
262 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
265 andn %g7, PSTATE_IE, %g2
266 wrpr %g2, 0x0, %pstate
268 mov PRIMARY_CONTEXT, %o4
269 ldxa [%o4] ASI_DMMU, %g2
270 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
271 sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
272 or %o0, %o3, %o0 /* Preserve nucleus page size fields */
273 stxa %o0, [%o4] ASI_DMMU
274 1: sub %o1, (1 << 3), %o1
279 stxa %g0, [%o3] ASI_IMMU_DEMAP
280 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
284 stxa %g2, [%o4] ASI_DMMU
285 sethi %hi(KERNBASE), %o4
289 wrpr %g7, 0x0, %pstate
291 #ifdef DCACHE_ALIASING_POSSIBLE
292 __cheetah_flush_dcache_page: /* 11 insns */
293 sethi %hi(PAGE_OFFSET), %g1
294 ldx [%g1 + %lo(PAGE_OFFSET)], %g1
296 sethi %hi(PAGE_SIZE), %o4
297 1: subcc %o4, (1 << 5), %o4
298 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
302 retl /* I-cache flush never needed on Cheetah, see callers. */
304 #endif /* DCACHE_ALIASING_POSSIBLE */
306 /* Hypervisor specific versions, patched at boot time. */
307 __hypervisor_tlb_tl0_error:
310 call hypervisor_tlbop_error
315 __hypervisor_flush_tlb_mm: /* 19 insns */
316 mov %o0, %o2 /* ARG2: mmu context */
317 mov 0, %o0 /* ARG0: CPU lists unimplemented */
318 mov 0, %o1 /* ARG1: CPU lists unimplemented */
319 mov HV_MMU_ALL, %o3 /* ARG3: flags */
320 mov HV_FAST_MMU_DEMAP_CTX, %o5
323 mov HV_FAST_MMU_DEMAP_CTX, %o1
326 1: sethi %hi(__hypervisor_tlb_tl0_error), %o5
327 jmpl %o5 + %lo(__hypervisor_tlb_tl0_error), %g0
336 __hypervisor_flush_tlb_page: /* 22 insns */
337 /* %o0 = context, %o1 = vaddr */
339 mov %o1, %o0 /* ARG0: vaddr + IMMU-bit */
340 mov %g2, %o1 /* ARG1: mmu context */
341 mov HV_MMU_ALL, %o2 /* ARG2: flags */
342 srlx %o0, PAGE_SHIFT, %o0
343 sllx %o0, PAGE_SHIFT, %o0
344 ta HV_MMU_UNMAP_ADDR_TRAP
346 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
349 1: sethi %hi(__hypervisor_tlb_tl0_error), %o2
350 jmpl %o2 + %lo(__hypervisor_tlb_tl0_error), %g0
361 __hypervisor_flush_tlb_pending: /* 27 insns */
362 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
366 1: sub %g1, (1 << 3), %g1
367 ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */
368 mov %g3, %o1 /* ARG1: mmu context */
369 mov HV_MMU_ALL, %o2 /* ARG2: flags */
370 srlx %o0, PAGE_SHIFT, %o0
371 sllx %o0, PAGE_SHIFT, %o0
372 ta HV_MMU_UNMAP_ADDR_TRAP
374 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
379 1: sethi %hi(__hypervisor_tlb_tl0_error), %o2
380 jmpl %o2 + %lo(__hypervisor_tlb_tl0_error), %g0
391 __hypervisor_flush_tlb_kernel_range: /* 19 insns */
392 /* %o0=start, %o1=end */
395 sethi %hi(PAGE_SIZE), %g3
399 1: add %g1, %g2, %o0 /* ARG0: virtual address */
400 mov 0, %o1 /* ARG1: mmu context */
401 mov HV_MMU_ALL, %o2 /* ARG2: flags */
402 ta HV_MMU_UNMAP_ADDR_TRAP
404 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
409 3: sethi %hi(__hypervisor_tlb_tl0_error), %o2
410 jmpl %o2 + %lo(__hypervisor_tlb_tl0_error), %g0
413 #ifdef DCACHE_ALIASING_POSSIBLE
414 /* XXX Niagara and friends have an 8K cache, so no aliasing is
415 * XXX possible, but nothing explicit in the Hypervisor API
416 * XXX guarantees this.
418 __hypervisor_flush_dcache_page: /* 2 insns */
434 .globl cheetah_patch_cachetlbops
435 cheetah_patch_cachetlbops:
438 sethi %hi(__flush_tlb_mm), %o0
439 or %o0, %lo(__flush_tlb_mm), %o0
440 sethi %hi(__cheetah_flush_tlb_mm), %o1
441 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
445 sethi %hi(__flush_tlb_page), %o0
446 or %o0, %lo(__flush_tlb_page), %o0
447 sethi %hi(__cheetah_flush_tlb_page), %o1
448 or %o1, %lo(__cheetah_flush_tlb_page), %o1
452 sethi %hi(__flush_tlb_pending), %o0
453 or %o0, %lo(__flush_tlb_pending), %o0
454 sethi %hi(__cheetah_flush_tlb_pending), %o1
455 or %o1, %lo(__cheetah_flush_tlb_pending), %o1
459 #ifdef DCACHE_ALIASING_POSSIBLE
460 sethi %hi(__flush_dcache_page), %o0
461 or %o0, %lo(__flush_dcache_page), %o0
462 sethi %hi(__cheetah_flush_dcache_page), %o1
463 or %o1, %lo(__cheetah_flush_dcache_page), %o1
466 #endif /* DCACHE_ALIASING_POSSIBLE */
472 /* These are all called by the slaves of a cross call, at
473 * trap level 1, with interrupts fully disabled.
476 * %g5 mm->context (all tlb flushes)
477 * %g1 address arg 1 (tlb page and range flushes)
478 * %g7 address arg 2 (tlb range flush only)
486 .globl xcall_flush_tlb_mm
487 xcall_flush_tlb_mm: /* 21 insns */
488 mov PRIMARY_CONTEXT, %g2
489 ldxa [%g2] ASI_DMMU, %g3
490 srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
491 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
492 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
493 stxa %g5, [%g2] ASI_DMMU
495 stxa %g0, [%g4] ASI_DMMU_DEMAP
496 stxa %g0, [%g4] ASI_IMMU_DEMAP
497 stxa %g3, [%g2] ASI_DMMU
510 .globl xcall_flush_tlb_page
511 xcall_flush_tlb_page: /* 17 insns */
512 /* %g5=context, %g1=vaddr */
513 mov PRIMARY_CONTEXT, %g4
514 ldxa [%g4] ASI_DMMU, %g2
515 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
516 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
518 mov PRIMARY_CONTEXT, %g4
519 stxa %g5, [%g4] ASI_DMMU
523 stxa %g0, [%g5] ASI_IMMU_DEMAP
524 2: stxa %g0, [%g5] ASI_DMMU_DEMAP
526 stxa %g2, [%g4] ASI_DMMU
531 .globl xcall_flush_tlb_kernel_range
532 xcall_flush_tlb_kernel_range: /* 25 insns */
533 sethi %hi(PAGE_SIZE - 1), %g2
534 or %g2, %lo(PAGE_SIZE - 1), %g2
540 or %g1, 0x20, %g1 ! Nucleus
541 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
542 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
559 /* This runs in a very controlled environment, so we do
560 * not need to worry about BH races etc.
562 .globl xcall_sync_tick
565 661: rdpr %pstate, %g2
566 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
567 .section .sun4v_2insn_patch, "ax"
574 wrpr %g0, PIL_NORMAL_MAX, %pil
577 109: or %g7, %lo(109b), %g7
578 #ifdef CONFIG_TRACE_IRQFLAGS
579 call trace_hardirqs_off
582 call smp_synchronize_tick_client
585 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
587 .globl xcall_fetch_glob_regs
588 xcall_fetch_glob_regs:
589 sethi %hi(global_cpu_snapshot), %g1
590 or %g1, %lo(global_cpu_snapshot), %g1
595 stx %g7, [%g1 + GR_SNAP_TSTATE]
597 stx %g7, [%g1 + GR_SNAP_TPC]
599 stx %g7, [%g1 + GR_SNAP_TNPC]
600 stx %o7, [%g1 + GR_SNAP_O7]
601 stx %i7, [%g1 + GR_SNAP_I7]
602 /* Don't try this at home kids... */
608 stx %g7, [%g1 + GR_SNAP_RPC]
609 sethi %hi(trap_block), %g7
610 or %g7, %lo(trap_block), %g7
611 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
613 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
614 stx %g3, [%g1 + GR_SNAP_THREAD]
617 .globl xcall_fetch_glob_pmu
618 xcall_fetch_glob_pmu:
619 sethi %hi(global_cpu_snapshot), %g1
620 or %g1, %lo(global_cpu_snapshot), %g1
625 stx %g7, [%g1 + (4 * 8)]
627 stx %g7, [%g1 + (0 * 8)]
630 .globl xcall_fetch_glob_pmu_n4
631 xcall_fetch_glob_pmu_n4:
632 sethi %hi(global_cpu_snapshot), %g1
633 or %g1, %lo(global_cpu_snapshot), %g1
638 ldxa [%g0] ASI_PIC, %g7
639 stx %g7, [%g1 + (4 * 8)]
641 ldxa [%g3] ASI_PIC, %g7
642 stx %g7, [%g1 + (5 * 8)]
644 ldxa [%g3] ASI_PIC, %g7
645 stx %g7, [%g1 + (6 * 8)]
647 ldxa [%g3] ASI_PIC, %g7
648 stx %g7, [%g1 + (7 * 8)]
654 mov HV_FAST_VT_GET_PERFREG, %o5
657 stx %o1, [%g1 + (3 * 8)]
658 mov HV_FAST_VT_GET_PERFREG, %o5
661 stx %o1, [%g1 + (2 * 8)]
662 mov HV_FAST_VT_GET_PERFREG, %o5
665 stx %o1, [%g1 + (1 * 8)]
666 mov HV_FAST_VT_GET_PERFREG, %o5
669 stx %o1, [%g1 + (0 * 8)]
677 #ifdef DCACHE_ALIASING_POSSIBLE
679 .globl xcall_flush_dcache_page_cheetah
680 xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
681 sethi %hi(PAGE_SIZE), %g3
682 1: subcc %g3, (1 << 5), %g3
683 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
689 #endif /* DCACHE_ALIASING_POSSIBLE */
691 .globl xcall_flush_dcache_page_spitfire
692 xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
693 %g7 == kernel page virtual address
694 %g5 == (page->mapping != NULL) */
695 #ifdef DCACHE_ALIASING_POSSIBLE
696 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
697 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
698 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
699 1: ldxa [%g3] ASI_DCACHE_TAG, %g2
707 stxa %g0, [%g3] ASI_DCACHE_TAG
711 sub %g3, (1 << 5), %g3
714 #endif /* DCACHE_ALIASING_POSSIBLE */
715 sethi %hi(PAGE_SIZE), %g3
718 subcc %g3, (1 << 5), %g3
720 add %g7, (1 << 5), %g7
729 __hypervisor_tlb_xcall_error:
735 call hypervisor_tlbop_error_xcall
739 .globl __hypervisor_xcall_flush_tlb_mm
740 __hypervisor_xcall_flush_tlb_mm: /* 21 insns */
741 /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
747 clr %o0 /* ARG0: CPU lists unimplemented */
748 clr %o1 /* ARG1: CPU lists unimplemented */
749 mov %g5, %o2 /* ARG2: mmu context */
750 mov HV_MMU_ALL, %o3 /* ARG3: flags */
751 mov HV_FAST_MMU_DEMAP_CTX, %o5
753 mov HV_FAST_MMU_DEMAP_CTX, %g6
754 brnz,pn %o0, __hypervisor_tlb_xcall_error
764 .globl __hypervisor_xcall_flush_tlb_page
765 __hypervisor_xcall_flush_tlb_page: /* 17 insns */
766 /* %g5=ctx, %g1=vaddr */
770 mov %g1, %o0 /* ARG0: virtual address */
771 mov %g5, %o1 /* ARG1: mmu context */
772 mov HV_MMU_ALL, %o2 /* ARG2: flags */
773 srlx %o0, PAGE_SHIFT, %o0
774 sllx %o0, PAGE_SHIFT, %o0
775 ta HV_MMU_UNMAP_ADDR_TRAP
776 mov HV_MMU_UNMAP_ADDR_TRAP, %g6
777 brnz,a,pn %o0, __hypervisor_tlb_xcall_error
785 .globl __hypervisor_xcall_flush_tlb_kernel_range
786 __hypervisor_xcall_flush_tlb_kernel_range: /* 25 insns */
787 /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
788 sethi %hi(PAGE_SIZE - 1), %g2
789 or %g2, %lo(PAGE_SIZE - 1), %g2
798 1: add %g1, %g3, %o0 /* ARG0: virtual address */
799 mov 0, %o1 /* ARG1: mmu context */
800 mov HV_MMU_ALL, %o2 /* ARG2: flags */
801 ta HV_MMU_UNMAP_ADDR_TRAP
802 mov HV_MMU_UNMAP_ADDR_TRAP, %g6
803 brnz,pn %o0, __hypervisor_tlb_xcall_error
805 sethi %hi(PAGE_SIZE), %o2
814 /* These just get rescheduled to PIL vectors. */
815 .globl xcall_call_function
817 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
820 .globl xcall_call_function_single
821 xcall_call_function_single:
822 wr %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint
825 .globl xcall_receive_signal
826 xcall_receive_signal:
827 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
832 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
835 .globl xcall_new_mmu_context_version
836 xcall_new_mmu_context_version:
837 wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint
841 .globl xcall_kgdb_capture
843 wr %g0, (1 << PIL_KGDB_CAPTURE), %set_softint
847 #endif /* CONFIG_SMP */
850 .globl hypervisor_patch_cachetlbops
851 hypervisor_patch_cachetlbops:
854 sethi %hi(__flush_tlb_mm), %o0
855 or %o0, %lo(__flush_tlb_mm), %o0
856 sethi %hi(__hypervisor_flush_tlb_mm), %o1
857 or %o1, %lo(__hypervisor_flush_tlb_mm), %o1
861 sethi %hi(__flush_tlb_page), %o0
862 or %o0, %lo(__flush_tlb_page), %o0
863 sethi %hi(__hypervisor_flush_tlb_page), %o1
864 or %o1, %lo(__hypervisor_flush_tlb_page), %o1
868 sethi %hi(__flush_tlb_pending), %o0
869 or %o0, %lo(__flush_tlb_pending), %o0
870 sethi %hi(__hypervisor_flush_tlb_pending), %o1
871 or %o1, %lo(__hypervisor_flush_tlb_pending), %o1
875 sethi %hi(__flush_tlb_kernel_range), %o0
876 or %o0, %lo(__flush_tlb_kernel_range), %o0
877 sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1
878 or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1
882 #ifdef DCACHE_ALIASING_POSSIBLE
883 sethi %hi(__flush_dcache_page), %o0
884 or %o0, %lo(__flush_dcache_page), %o0
885 sethi %hi(__hypervisor_flush_dcache_page), %o1
886 or %o1, %lo(__hypervisor_flush_dcache_page), %o1
889 #endif /* DCACHE_ALIASING_POSSIBLE */
892 sethi %hi(xcall_flush_tlb_mm), %o0
893 or %o0, %lo(xcall_flush_tlb_mm), %o0
894 sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1
895 or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1
899 sethi %hi(xcall_flush_tlb_page), %o0
900 or %o0, %lo(xcall_flush_tlb_page), %o0
901 sethi %hi(__hypervisor_xcall_flush_tlb_page), %o1
902 or %o1, %lo(__hypervisor_xcall_flush_tlb_page), %o1
906 sethi %hi(xcall_flush_tlb_kernel_range), %o0
907 or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
908 sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1
909 or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1
912 #endif /* CONFIG_SMP */