arch/x86/include/asm/barrier.h

   1 #ifndef _ASM_X86_BARRIER_H
   2 #define _ASM_X86_BARRIER_H
   3
   4 #include <asm/alternative.h>
   5 #include <asm/nops.h>
   6
   7 /*
   8  * Force strict CPU ordering.
   9  * And yes, this is required on UP too when we're talking
  10  * to devices.
  11  */
  12
  13 #ifdef CONFIG_X86_32
  14 /*
  15  * Some non-Intel clones support out of order store. wmb() ceases to be a
  16  * nop for these.
  17  */
  18 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
  19 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
  20 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
  21 #else
  22 #define mb()    asm volatile("mfence":::"memory")
  23 #define rmb()   asm volatile("lfence":::"memory")
  24 #define wmb()   asm volatile("sfence" ::: "memory")
  25 #endif
  26
  27 #ifdef CONFIG_X86_PPRO_FENCE
  28 #define dma_rmb()       rmb()
  29 #else
  30 #define dma_rmb()       barrier()
  31 #endif
  32 #define dma_wmb()       barrier()
  33
  34 #define __smp_mb()      mb()
  35 #define __smp_rmb()     dma_rmb()
  36 #define __smp_wmb()     barrier()
  37 #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
  38
  39 #if defined(CONFIG_X86_PPRO_FENCE)
  40
  41 /*
  42  * For this option x86 doesn't have a strong TSO memory
  43  * model and we should fall back to full barriers.
  44  */
  45
  46 #define __smp_store_release(p, v)                                       \
  47 do {                                                                    \
  48         compiletime_assert_atomic_type(*p);                             \
  49         __smp_mb();                                                     \
  50         WRITE_ONCE(*p, v);                                              \
  51 } while (0)
  52
  53 #define __smp_load_acquire(p)                                           \
  54 ({                                                                      \
  55         typeof(*p) ___p1 = READ_ONCE(*p);                               \
  56         compiletime_assert_atomic_type(*p);                             \
  57         __smp_mb();                                                     \
  58         ___p1;                                                          \
  59 })
  60
  61 #else /* regular x86 TSO memory ordering */
  62
  63 #define __smp_store_release(p, v)                                       \
  64 do {                                                                    \
  65         compiletime_assert_atomic_type(*p);                             \
  66         barrier();                                                      \
  67         WRITE_ONCE(*p, v);                                              \
  68 } while (0)
  69
  70 #define __smp_load_acquire(p)                                           \
  71 ({                                                                      \
  72         typeof(*p) ___p1 = READ_ONCE(*p);                               \
  73         compiletime_assert_atomic_type(*p);                             \
  74         barrier();                                                      \
  75         ___p1;                                                          \
  76 })
  77
  78 #endif
  79
  80 /* Atomic operations are already serializing on x86 */
  81 #define __smp_mb__before_atomic()       barrier()
  82 #define __smp_mb__after_atomic()        barrier()
  83
  84 #include <asm-generic/barrier.h>
  85
  86 #endif /* _ASM_X86_BARRIER_H */