2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
44 #include <asm/kvm_page_track.h>
47 * When setting this variable to true it enables Two-Dimensional-Paging
48 * where the hardware walks 2 page tables:
49 * 1. the guest-virtual to guest-physical
50 * 2. while doing 1. it walks guest-physical to host-physical
51 * If the hardware supports that we don't need to do shadow paging.
53 bool tdp_enabled = false;
57 AUDIT_POST_PAGE_FAULT,
68 module_param(dbg, bool, 0644);
70 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
71 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72 #define MMU_WARN_ON(x) WARN_ON(x)
74 #define pgprintk(x...) do { } while (0)
75 #define rmap_printk(x...) do { } while (0)
76 #define MMU_WARN_ON(x) do { } while (0)
79 #define PTE_PREFETCH_NUM 8
81 #define PT_FIRST_AVAIL_BITS_SHIFT 10
82 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
84 #define PT64_LEVEL_BITS 9
86 #define PT64_LEVEL_SHIFT(level) \
87 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
89 #define PT64_INDEX(address, level)\
90 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
93 #define PT32_LEVEL_BITS 10
95 #define PT32_LEVEL_SHIFT(level) \
96 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
98 #define PT32_LVL_OFFSET_MASK(level) \
99 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
100 * PT32_LEVEL_BITS))) - 1))
102 #define PT32_INDEX(address, level)\
103 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
106 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
107 #define PT64_DIR_BASE_ADDR_MASK \
108 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
109 #define PT64_LVL_ADDR_MASK(level) \
110 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
111 * PT64_LEVEL_BITS))) - 1))
112 #define PT64_LVL_OFFSET_MASK(level) \
113 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT64_LEVEL_BITS))) - 1))
116 #define PT32_BASE_ADDR_MASK PAGE_MASK
117 #define PT32_DIR_BASE_ADDR_MASK \
118 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
119 #define PT32_LVL_ADDR_MASK(level) \
120 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
121 * PT32_LEVEL_BITS))) - 1))
123 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
124 | shadow_x_mask | shadow_nx_mask)
126 #define ACC_EXEC_MASK 1
127 #define ACC_WRITE_MASK PT_WRITABLE_MASK
128 #define ACC_USER_MASK PT_USER_MASK
129 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
131 #include <trace/events/kvm.h>
133 #define CREATE_TRACE_POINTS
134 #include "mmutrace.h"
136 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
137 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
139 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
141 /* make pte_list_desc fit well in cache line */
142 #define PTE_LIST_EXT 3
144 struct pte_list_desc {
145 u64 *sptes[PTE_LIST_EXT];
146 struct pte_list_desc *more;
149 struct kvm_shadow_walk_iterator {
157 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
158 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
162 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)) && \
165 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
166 __shadow_walk_next(&(_walker), spte))
168 static struct kmem_cache *pte_list_desc_cache;
169 static struct kmem_cache *mmu_page_header_cache;
170 static struct percpu_counter kvm_total_used_mmu_pages;
172 static u64 __read_mostly shadow_nx_mask;
173 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
174 static u64 __read_mostly shadow_user_mask;
175 static u64 __read_mostly shadow_accessed_mask;
176 static u64 __read_mostly shadow_dirty_mask;
177 static u64 __read_mostly shadow_mmio_mask;
179 static void mmu_spte_set(u64 *sptep, u64 spte);
180 static void mmu_free_roots(struct kvm_vcpu *vcpu);
182 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
184 shadow_mmio_mask = mmio_mask;
186 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
189 * the low bit of the generation number is always presumed to be zero.
190 * This disables mmio caching during memslot updates. The concept is
191 * similar to a seqcount but instead of retrying the access we just punt
192 * and ignore the cache.
194 * spte bits 3-11 are used as bits 1-9 of the generation number,
195 * the bits 52-61 are used as bits 10-19 of the generation number.
197 #define MMIO_SPTE_GEN_LOW_SHIFT 2
198 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
200 #define MMIO_GEN_SHIFT 20
201 #define MMIO_GEN_LOW_SHIFT 10
202 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
203 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
205 static u64 generation_mmio_spte_mask(unsigned int gen)
209 WARN_ON(gen & ~MMIO_GEN_MASK);
211 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
212 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
216 static unsigned int get_mmio_spte_generation(u64 spte)
220 spte &= ~shadow_mmio_mask;
222 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
223 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
227 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
229 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
232 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
235 unsigned int gen = kvm_current_mmio_generation(vcpu);
236 u64 mask = generation_mmio_spte_mask(gen);
238 access &= ACC_WRITE_MASK | ACC_USER_MASK;
239 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
241 trace_mark_mmio_spte(sptep, gfn, access, gen);
242 mmu_spte_set(sptep, mask);
245 static bool is_mmio_spte(u64 spte)
247 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
250 static gfn_t get_mmio_spte_gfn(u64 spte)
252 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
253 return (spte & ~mask) >> PAGE_SHIFT;
256 static unsigned get_mmio_spte_access(u64 spte)
258 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
259 return (spte & ~mask) & ~PAGE_MASK;
262 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
263 kvm_pfn_t pfn, unsigned access)
265 if (unlikely(is_noslot_pfn(pfn))) {
266 mark_mmio_spte(vcpu, sptep, gfn, access);
273 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
275 unsigned int kvm_gen, spte_gen;
277 kvm_gen = kvm_current_mmio_generation(vcpu);
278 spte_gen = get_mmio_spte_generation(spte);
280 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
281 return likely(kvm_gen == spte_gen);
284 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
285 u64 dirty_mask, u64 nx_mask, u64 x_mask)
287 shadow_user_mask = user_mask;
288 shadow_accessed_mask = accessed_mask;
289 shadow_dirty_mask = dirty_mask;
290 shadow_nx_mask = nx_mask;
291 shadow_x_mask = x_mask;
293 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
295 static int is_cpuid_PSE36(void)
300 static int is_nx(struct kvm_vcpu *vcpu)
302 return vcpu->arch.efer & EFER_NX;
305 static int is_shadow_present_pte(u64 pte)
307 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
310 static int is_large_pte(u64 pte)
312 return pte & PT_PAGE_SIZE_MASK;
315 static int is_last_spte(u64 pte, int level)
317 if (level == PT_PAGE_TABLE_LEVEL)
319 if (is_large_pte(pte))
324 static kvm_pfn_t spte_to_pfn(u64 pte)
326 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
329 static gfn_t pse36_gfn_delta(u32 gpte)
331 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
333 return (gpte & PT32_DIR_PSE36_MASK) << shift;
337 static void __set_spte(u64 *sptep, u64 spte)
342 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
347 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
349 return xchg(sptep, spte);
352 static u64 __get_spte_lockless(u64 *sptep)
354 return ACCESS_ONCE(*sptep);
365 static void count_spte_clear(u64 *sptep, u64 spte)
367 struct kvm_mmu_page *sp = page_header(__pa(sptep));
369 if (is_shadow_present_pte(spte))
372 /* Ensure the spte is completely set before we increase the count */
374 sp->clear_spte_count++;
377 static void __set_spte(u64 *sptep, u64 spte)
379 union split_spte *ssptep, sspte;
381 ssptep = (union split_spte *)sptep;
382 sspte = (union split_spte)spte;
384 ssptep->spte_high = sspte.spte_high;
387 * If we map the spte from nonpresent to present, We should store
388 * the high bits firstly, then set present bit, so cpu can not
389 * fetch this spte while we are setting the spte.
393 ssptep->spte_low = sspte.spte_low;
396 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
398 union split_spte *ssptep, sspte;
400 ssptep = (union split_spte *)sptep;
401 sspte = (union split_spte)spte;
403 ssptep->spte_low = sspte.spte_low;
406 * If we map the spte from present to nonpresent, we should clear
407 * present bit firstly to avoid vcpu fetch the old high bits.
411 ssptep->spte_high = sspte.spte_high;
412 count_spte_clear(sptep, spte);
415 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
417 union split_spte *ssptep, sspte, orig;
419 ssptep = (union split_spte *)sptep;
420 sspte = (union split_spte)spte;
422 /* xchg acts as a barrier before the setting of the high bits */
423 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
424 orig.spte_high = ssptep->spte_high;
425 ssptep->spte_high = sspte.spte_high;
426 count_spte_clear(sptep, spte);
432 * The idea using the light way get the spte on x86_32 guest is from
433 * gup_get_pte(arch/x86/mm/gup.c).
435 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
436 * coalesces them and we are running out of the MMU lock. Therefore
437 * we need to protect against in-progress updates of the spte.
439 * Reading the spte while an update is in progress may get the old value
440 * for the high part of the spte. The race is fine for a present->non-present
441 * change (because the high part of the spte is ignored for non-present spte),
442 * but for a present->present change we must reread the spte.
444 * All such changes are done in two steps (present->non-present and
445 * non-present->present), hence it is enough to count the number of
446 * present->non-present updates: if it changed while reading the spte,
447 * we might have hit the race. This is done using clear_spte_count.
449 static u64 __get_spte_lockless(u64 *sptep)
451 struct kvm_mmu_page *sp = page_header(__pa(sptep));
452 union split_spte spte, *orig = (union split_spte *)sptep;
456 count = sp->clear_spte_count;
459 spte.spte_low = orig->spte_low;
462 spte.spte_high = orig->spte_high;
465 if (unlikely(spte.spte_low != orig->spte_low ||
466 count != sp->clear_spte_count))
473 static bool spte_is_locklessly_modifiable(u64 spte)
475 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
476 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
479 static bool spte_has_volatile_bits(u64 spte)
482 * Always atomicly update spte if it can be updated
483 * out of mmu-lock, it can ensure dirty bit is not lost,
484 * also, it can help us to get a stable is_writable_pte()
485 * to ensure tlb flush is not missed.
487 if (spte_is_locklessly_modifiable(spte))
490 if (!shadow_accessed_mask)
493 if (!is_shadow_present_pte(spte))
496 if ((spte & shadow_accessed_mask) &&
497 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
503 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
505 return (old_spte & bit_mask) && !(new_spte & bit_mask);
508 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
510 return (old_spte & bit_mask) != (new_spte & bit_mask);
513 /* Rules for using mmu_spte_set:
514 * Set the sptep from nonpresent to present.
515 * Note: the sptep being assigned *must* be either not present
516 * or in a state where the hardware will not attempt to update
519 static void mmu_spte_set(u64 *sptep, u64 new_spte)
521 WARN_ON(is_shadow_present_pte(*sptep));
522 __set_spte(sptep, new_spte);
525 /* Rules for using mmu_spte_update:
526 * Update the state bits, it means the mapped pfn is not changged.
528 * Whenever we overwrite a writable spte with a read-only one we
529 * should flush remote TLBs. Otherwise rmap_write_protect
530 * will find a read-only spte, even though the writable spte
531 * might be cached on a CPU's TLB, the return value indicates this
534 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
536 u64 old_spte = *sptep;
539 WARN_ON(!is_shadow_present_pte(new_spte));
541 if (!is_shadow_present_pte(old_spte)) {
542 mmu_spte_set(sptep, new_spte);
546 if (!spte_has_volatile_bits(old_spte))
547 __update_clear_spte_fast(sptep, new_spte);
549 old_spte = __update_clear_spte_slow(sptep, new_spte);
552 * For the spte updated out of mmu-lock is safe, since
553 * we always atomicly update it, see the comments in
554 * spte_has_volatile_bits().
556 if (spte_is_locklessly_modifiable(old_spte) &&
557 !is_writable_pte(new_spte))
560 if (!shadow_accessed_mask)
564 * Flush TLB when accessed/dirty bits are changed in the page tables,
565 * to guarantee consistency between TLB and page tables.
567 if (spte_is_bit_changed(old_spte, new_spte,
568 shadow_accessed_mask | shadow_dirty_mask))
571 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
572 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
573 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
574 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
580 * Rules for using mmu_spte_clear_track_bits:
581 * It sets the sptep from present to nonpresent, and track the
582 * state bits, it is used to clear the last level sptep.
584 static int mmu_spte_clear_track_bits(u64 *sptep)
587 u64 old_spte = *sptep;
589 if (!spte_has_volatile_bits(old_spte))
590 __update_clear_spte_fast(sptep, 0ull);
592 old_spte = __update_clear_spte_slow(sptep, 0ull);
594 if (!is_shadow_present_pte(old_spte))
597 pfn = spte_to_pfn(old_spte);
600 * KVM does not hold the refcount of the page used by
601 * kvm mmu, before reclaiming the page, we should
602 * unmap it from mmu first.
604 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
606 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
607 kvm_set_pfn_accessed(pfn);
608 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
609 kvm_set_pfn_dirty(pfn);
614 * Rules for using mmu_spte_clear_no_track:
615 * Directly clear spte without caring the state bits of sptep,
616 * it is used to set the upper level spte.
618 static void mmu_spte_clear_no_track(u64 *sptep)
620 __update_clear_spte_fast(sptep, 0ull);
623 static u64 mmu_spte_get_lockless(u64 *sptep)
625 return __get_spte_lockless(sptep);
628 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
631 * Prevent page table teardown by making any free-er wait during
632 * kvm_flush_remote_tlbs() IPI to all active vcpus.
635 vcpu->mode = READING_SHADOW_PAGE_TABLES;
637 * Make sure a following spte read is not reordered ahead of the write
643 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
646 * Make sure the write to vcpu->mode is not reordered in front of
647 * reads to sptes. If it does, kvm_commit_zap_page() can see us
648 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
651 vcpu->mode = OUTSIDE_GUEST_MODE;
655 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
656 struct kmem_cache *base_cache, int min)
660 if (cache->nobjs >= min)
662 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
663 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
666 cache->objects[cache->nobjs++] = obj;
671 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
676 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
677 struct kmem_cache *cache)
680 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
683 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
688 if (cache->nobjs >= min)
690 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
691 page = (void *)__get_free_page(GFP_KERNEL);
694 cache->objects[cache->nobjs++] = page;
699 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
702 free_page((unsigned long)mc->objects[--mc->nobjs]);
705 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
709 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
710 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
713 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
716 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
717 mmu_page_header_cache, 4);
722 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
724 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
725 pte_list_desc_cache);
726 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
727 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
728 mmu_page_header_cache);
731 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
736 p = mc->objects[--mc->nobjs];
740 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
742 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
745 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
747 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
750 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
752 if (!sp->role.direct)
753 return sp->gfns[index];
755 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
758 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
761 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
763 sp->gfns[index] = gfn;
767 * Return the pointer to the large page information for a given gfn,
768 * handling slots that are not large page aligned.
770 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
771 struct kvm_memory_slot *slot,
776 idx = gfn_to_index(gfn, slot->base_gfn, level);
777 return &slot->arch.lpage_info[level - 2][idx];
780 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
781 gfn_t gfn, int count)
783 struct kvm_lpage_info *linfo;
786 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
787 linfo = lpage_info_slot(gfn, slot, i);
788 linfo->disallow_lpage += count;
789 WARN_ON(linfo->disallow_lpage < 0);
793 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
795 update_gfn_disallow_lpage_count(slot, gfn, 1);
798 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
800 update_gfn_disallow_lpage_count(slot, gfn, -1);
803 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
805 struct kvm_memslots *slots;
806 struct kvm_memory_slot *slot;
809 kvm->arch.indirect_shadow_pages++;
811 slots = kvm_memslots_for_spte_role(kvm, sp->role);
812 slot = __gfn_to_memslot(slots, gfn);
814 /* the non-leaf shadow pages are keeping readonly. */
815 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
816 return kvm_slot_page_track_add_page(kvm, slot, gfn,
817 KVM_PAGE_TRACK_WRITE);
819 kvm_mmu_gfn_disallow_lpage(slot, gfn);
822 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
824 struct kvm_memslots *slots;
825 struct kvm_memory_slot *slot;
828 kvm->arch.indirect_shadow_pages--;
830 slots = kvm_memslots_for_spte_role(kvm, sp->role);
831 slot = __gfn_to_memslot(slots, gfn);
832 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
833 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
834 KVM_PAGE_TRACK_WRITE);
836 kvm_mmu_gfn_allow_lpage(slot, gfn);
839 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
840 struct kvm_memory_slot *slot)
842 struct kvm_lpage_info *linfo;
845 linfo = lpage_info_slot(gfn, slot, level);
846 return !!linfo->disallow_lpage;
852 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
855 struct kvm_memory_slot *slot;
857 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
858 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
861 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
863 unsigned long page_size;
866 page_size = kvm_host_page_size(kvm, gfn);
868 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
869 if (page_size >= KVM_HPAGE_SIZE(i))
878 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
881 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
883 if (no_dirty_log && slot->dirty_bitmap)
889 static struct kvm_memory_slot *
890 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
893 struct kvm_memory_slot *slot;
895 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
896 if (!memslot_valid_for_gpte(slot, no_dirty_log))
902 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
903 bool *force_pt_level)
905 int host_level, level, max_level;
906 struct kvm_memory_slot *slot;
908 if (unlikely(*force_pt_level))
909 return PT_PAGE_TABLE_LEVEL;
911 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
912 *force_pt_level = !memslot_valid_for_gpte(slot, true);
913 if (unlikely(*force_pt_level))
914 return PT_PAGE_TABLE_LEVEL;
916 host_level = host_mapping_level(vcpu->kvm, large_gfn);
918 if (host_level == PT_PAGE_TABLE_LEVEL)
921 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
923 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
924 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
931 * About rmap_head encoding:
933 * If the bit zero of rmap_head->val is clear, then it points to the only spte
934 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
935 * pte_list_desc containing more mappings.
939 * Returns the number of pointers in the rmap chain, not counting the new one.
941 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
942 struct kvm_rmap_head *rmap_head)
944 struct pte_list_desc *desc;
947 if (!rmap_head->val) {
948 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
949 rmap_head->val = (unsigned long)spte;
950 } else if (!(rmap_head->val & 1)) {
951 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
952 desc = mmu_alloc_pte_list_desc(vcpu);
953 desc->sptes[0] = (u64 *)rmap_head->val;
954 desc->sptes[1] = spte;
955 rmap_head->val = (unsigned long)desc | 1;
958 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
959 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
960 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
962 count += PTE_LIST_EXT;
964 if (desc->sptes[PTE_LIST_EXT-1]) {
965 desc->more = mmu_alloc_pte_list_desc(vcpu);
968 for (i = 0; desc->sptes[i]; ++i)
970 desc->sptes[i] = spte;
976 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
977 struct pte_list_desc *desc, int i,
978 struct pte_list_desc *prev_desc)
982 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
984 desc->sptes[i] = desc->sptes[j];
985 desc->sptes[j] = NULL;
988 if (!prev_desc && !desc->more)
989 rmap_head->val = (unsigned long)desc->sptes[0];
992 prev_desc->more = desc->more;
994 rmap_head->val = (unsigned long)desc->more | 1;
995 mmu_free_pte_list_desc(desc);
998 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1000 struct pte_list_desc *desc;
1001 struct pte_list_desc *prev_desc;
1004 if (!rmap_head->val) {
1005 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1007 } else if (!(rmap_head->val & 1)) {
1008 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1009 if ((u64 *)rmap_head->val != spte) {
1010 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1015 rmap_printk("pte_list_remove: %p many->many\n", spte);
1016 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1019 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1020 if (desc->sptes[i] == spte) {
1021 pte_list_desc_remove_entry(rmap_head,
1022 desc, i, prev_desc);
1029 pr_err("pte_list_remove: %p many->many\n", spte);
1034 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1035 struct kvm_memory_slot *slot)
1039 idx = gfn_to_index(gfn, slot->base_gfn, level);
1040 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1043 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1044 struct kvm_mmu_page *sp)
1046 struct kvm_memslots *slots;
1047 struct kvm_memory_slot *slot;
1049 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1050 slot = __gfn_to_memslot(slots, gfn);
1051 return __gfn_to_rmap(gfn, sp->role.level, slot);
1054 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1056 struct kvm_mmu_memory_cache *cache;
1058 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1059 return mmu_memory_cache_free_objects(cache);
1062 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1064 struct kvm_mmu_page *sp;
1065 struct kvm_rmap_head *rmap_head;
1067 sp = page_header(__pa(spte));
1068 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1069 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1070 return pte_list_add(vcpu, spte, rmap_head);
1073 static void rmap_remove(struct kvm *kvm, u64 *spte)
1075 struct kvm_mmu_page *sp;
1077 struct kvm_rmap_head *rmap_head;
1079 sp = page_header(__pa(spte));
1080 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1081 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1082 pte_list_remove(spte, rmap_head);
1086 * Used by the following functions to iterate through the sptes linked by a
1087 * rmap. All fields are private and not assumed to be used outside.
1089 struct rmap_iterator {
1090 /* private fields */
1091 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1092 int pos; /* index of the sptep */
1096 * Iteration must be started by this function. This should also be used after
1097 * removing/dropping sptes from the rmap link because in such cases the
1098 * information in the itererator may not be valid.
1100 * Returns sptep if found, NULL otherwise.
1102 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1103 struct rmap_iterator *iter)
1107 if (!rmap_head->val)
1110 if (!(rmap_head->val & 1)) {
1112 sptep = (u64 *)rmap_head->val;
1116 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1118 sptep = iter->desc->sptes[iter->pos];
1120 BUG_ON(!is_shadow_present_pte(*sptep));
1125 * Must be used with a valid iterator: e.g. after rmap_get_first().
1127 * Returns sptep if found, NULL otherwise.
1129 static u64 *rmap_get_next(struct rmap_iterator *iter)
1134 if (iter->pos < PTE_LIST_EXT - 1) {
1136 sptep = iter->desc->sptes[iter->pos];
1141 iter->desc = iter->desc->more;
1145 /* desc->sptes[0] cannot be NULL */
1146 sptep = iter->desc->sptes[iter->pos];
1153 BUG_ON(!is_shadow_present_pte(*sptep));
1157 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1158 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1159 _spte_; _spte_ = rmap_get_next(_iter_))
1161 static void drop_spte(struct kvm *kvm, u64 *sptep)
1163 if (mmu_spte_clear_track_bits(sptep))
1164 rmap_remove(kvm, sptep);
1168 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1170 if (is_large_pte(*sptep)) {
1171 WARN_ON(page_header(__pa(sptep))->role.level ==
1172 PT_PAGE_TABLE_LEVEL);
1173 drop_spte(kvm, sptep);
1181 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1183 if (__drop_large_spte(vcpu->kvm, sptep))
1184 kvm_flush_remote_tlbs(vcpu->kvm);
1188 * Write-protect on the specified @sptep, @pt_protect indicates whether
1189 * spte write-protection is caused by protecting shadow page table.
1191 * Note: write protection is difference between dirty logging and spte
1193 * - for dirty logging, the spte can be set to writable at anytime if
1194 * its dirty bitmap is properly set.
1195 * - for spte protection, the spte can be writable only after unsync-ing
1198 * Return true if tlb need be flushed.
1200 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1204 if (!is_writable_pte(spte) &&
1205 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1208 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1211 spte &= ~SPTE_MMU_WRITEABLE;
1212 spte = spte & ~PT_WRITABLE_MASK;
1214 return mmu_spte_update(sptep, spte);
1217 static bool __rmap_write_protect(struct kvm *kvm,
1218 struct kvm_rmap_head *rmap_head,
1222 struct rmap_iterator iter;
1225 for_each_rmap_spte(rmap_head, &iter, sptep)
1226 flush |= spte_write_protect(kvm, sptep, pt_protect);
1231 static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep)
1235 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1237 spte &= ~shadow_dirty_mask;
1239 return mmu_spte_update(sptep, spte);
1242 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1245 struct rmap_iterator iter;
1248 for_each_rmap_spte(rmap_head, &iter, sptep)
1249 flush |= spte_clear_dirty(kvm, sptep);
1254 static bool spte_set_dirty(struct kvm *kvm, u64 *sptep)
1258 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1260 spte |= shadow_dirty_mask;
1262 return mmu_spte_update(sptep, spte);
1265 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1268 struct rmap_iterator iter;
1271 for_each_rmap_spte(rmap_head, &iter, sptep)
1272 flush |= spte_set_dirty(kvm, sptep);
1278 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1279 * @kvm: kvm instance
1280 * @slot: slot to protect
1281 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1282 * @mask: indicates which pages we should protect
1284 * Used when we do not need to care about huge page mappings: e.g. during dirty
1285 * logging we do not have any such mappings.
1287 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1288 struct kvm_memory_slot *slot,
1289 gfn_t gfn_offset, unsigned long mask)
1291 struct kvm_rmap_head *rmap_head;
1294 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1295 PT_PAGE_TABLE_LEVEL, slot);
1296 __rmap_write_protect(kvm, rmap_head, false);
1298 /* clear the first set bit */
1304 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1305 * @kvm: kvm instance
1306 * @slot: slot to clear D-bit
1307 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1308 * @mask: indicates which pages we should clear D-bit
1310 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1312 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1313 struct kvm_memory_slot *slot,
1314 gfn_t gfn_offset, unsigned long mask)
1316 struct kvm_rmap_head *rmap_head;
1319 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1320 PT_PAGE_TABLE_LEVEL, slot);
1321 __rmap_clear_dirty(kvm, rmap_head);
1323 /* clear the first set bit */
1327 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1330 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1333 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1334 * enable dirty logging for them.
1336 * Used when we do not need to care about huge page mappings: e.g. during dirty
1337 * logging we do not have any such mappings.
1339 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1340 struct kvm_memory_slot *slot,
1341 gfn_t gfn_offset, unsigned long mask)
1343 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1344 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1347 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1350 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1351 struct kvm_memory_slot *slot, u64 gfn)
1353 struct kvm_rmap_head *rmap_head;
1355 bool write_protected = false;
1357 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1358 rmap_head = __gfn_to_rmap(gfn, i, slot);
1359 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1362 return write_protected;
1365 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1367 struct kvm_memory_slot *slot;
1369 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1370 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1373 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1376 struct rmap_iterator iter;
1379 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1380 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1382 drop_spte(kvm, sptep);
1389 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1390 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1393 return kvm_zap_rmapp(kvm, rmap_head);
1396 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1397 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1401 struct rmap_iterator iter;
1404 pte_t *ptep = (pte_t *)data;
1407 WARN_ON(pte_huge(*ptep));
1408 new_pfn = pte_pfn(*ptep);
1411 for_each_rmap_spte(rmap_head, &iter, sptep) {
1412 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1413 sptep, *sptep, gfn, level);
1417 if (pte_write(*ptep)) {
1418 drop_spte(kvm, sptep);
1421 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1422 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1424 new_spte &= ~PT_WRITABLE_MASK;
1425 new_spte &= ~SPTE_HOST_WRITEABLE;
1426 new_spte &= ~shadow_accessed_mask;
1428 mmu_spte_clear_track_bits(sptep);
1429 mmu_spte_set(sptep, new_spte);
1434 kvm_flush_remote_tlbs(kvm);
1439 struct slot_rmap_walk_iterator {
1441 struct kvm_memory_slot *slot;
1447 /* output fields. */
1449 struct kvm_rmap_head *rmap;
1452 /* private field. */
1453 struct kvm_rmap_head *end_rmap;
1457 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1459 iterator->level = level;
1460 iterator->gfn = iterator->start_gfn;
1461 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1462 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1467 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1468 struct kvm_memory_slot *slot, int start_level,
1469 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1471 iterator->slot = slot;
1472 iterator->start_level = start_level;
1473 iterator->end_level = end_level;
1474 iterator->start_gfn = start_gfn;
1475 iterator->end_gfn = end_gfn;
1477 rmap_walk_init_level(iterator, iterator->start_level);
1480 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1482 return !!iterator->rmap;
1485 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1487 if (++iterator->rmap <= iterator->end_rmap) {
1488 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1492 if (++iterator->level > iterator->end_level) {
1493 iterator->rmap = NULL;
1497 rmap_walk_init_level(iterator, iterator->level);
1500 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1501 _start_gfn, _end_gfn, _iter_) \
1502 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1503 _end_level_, _start_gfn, _end_gfn); \
1504 slot_rmap_walk_okay(_iter_); \
1505 slot_rmap_walk_next(_iter_))
1507 static int kvm_handle_hva_range(struct kvm *kvm,
1508 unsigned long start,
1511 int (*handler)(struct kvm *kvm,
1512 struct kvm_rmap_head *rmap_head,
1513 struct kvm_memory_slot *slot,
1516 unsigned long data))
1518 struct kvm_memslots *slots;
1519 struct kvm_memory_slot *memslot;
1520 struct slot_rmap_walk_iterator iterator;
1524 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1525 slots = __kvm_memslots(kvm, i);
1526 kvm_for_each_memslot(memslot, slots) {
1527 unsigned long hva_start, hva_end;
1528 gfn_t gfn_start, gfn_end;
1530 hva_start = max(start, memslot->userspace_addr);
1531 hva_end = min(end, memslot->userspace_addr +
1532 (memslot->npages << PAGE_SHIFT));
1533 if (hva_start >= hva_end)
1536 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1537 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1539 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1540 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1542 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1543 PT_MAX_HUGEPAGE_LEVEL,
1544 gfn_start, gfn_end - 1,
1546 ret |= handler(kvm, iterator.rmap, memslot,
1547 iterator.gfn, iterator.level, data);
1554 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1556 int (*handler)(struct kvm *kvm,
1557 struct kvm_rmap_head *rmap_head,
1558 struct kvm_memory_slot *slot,
1559 gfn_t gfn, int level,
1560 unsigned long data))
1562 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1565 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1567 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1570 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1572 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1575 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1577 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1580 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1581 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1585 struct rmap_iterator uninitialized_var(iter);
1588 BUG_ON(!shadow_accessed_mask);
1590 for_each_rmap_spte(rmap_head, &iter, sptep) {
1591 if (*sptep & shadow_accessed_mask) {
1593 clear_bit((ffs(shadow_accessed_mask) - 1),
1594 (unsigned long *)sptep);
1598 trace_kvm_age_page(gfn, level, slot, young);
1602 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1603 struct kvm_memory_slot *slot, gfn_t gfn,
1604 int level, unsigned long data)
1607 struct rmap_iterator iter;
1611 * If there's no access bit in the secondary pte set by the
1612 * hardware it's up to gup-fast/gup to set the access bit in
1613 * the primary pte or in the page structure.
1615 if (!shadow_accessed_mask)
1618 for_each_rmap_spte(rmap_head, &iter, sptep) {
1619 if (*sptep & shadow_accessed_mask) {
1628 #define RMAP_RECYCLE_THRESHOLD 1000
1630 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1632 struct kvm_rmap_head *rmap_head;
1633 struct kvm_mmu_page *sp;
1635 sp = page_header(__pa(spte));
1637 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1639 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1640 kvm_flush_remote_tlbs(vcpu->kvm);
1643 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1646 * In case of absence of EPT Access and Dirty Bits supports,
1647 * emulate the accessed bit for EPT, by checking if this page has
1648 * an EPT mapping, and clearing it if it does. On the next access,
1649 * a new EPT mapping will be established.
1650 * This has some overhead, but not as much as the cost of swapping
1651 * out actively used pages or breaking up actively used hugepages.
1653 if (!shadow_accessed_mask) {
1655 * We are holding the kvm->mmu_lock, and we are blowing up
1656 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1657 * This is correct as long as we don't decouple the mmu_lock
1658 * protected regions (like invalidate_range_start|end does).
1660 kvm->mmu_notifier_seq++;
1661 return kvm_handle_hva_range(kvm, start, end, 0,
1665 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1668 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1670 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1674 static int is_empty_shadow_page(u64 *spt)
1679 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1680 if (is_shadow_present_pte(*pos)) {
1681 printk(KERN_ERR "%s: %p %llx\n", __func__,
1690 * This value is the sum of all of the kvm instances's
1691 * kvm->arch.n_used_mmu_pages values. We need a global,
1692 * aggregate version in order to make the slab shrinker
1695 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1697 kvm->arch.n_used_mmu_pages += nr;
1698 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1701 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1703 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1704 hlist_del(&sp->hash_link);
1705 list_del(&sp->link);
1706 free_page((unsigned long)sp->spt);
1707 if (!sp->role.direct)
1708 free_page((unsigned long)sp->gfns);
1709 kmem_cache_free(mmu_page_header_cache, sp);
1712 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1714 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1717 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1718 struct kvm_mmu_page *sp, u64 *parent_pte)
1723 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1726 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1729 pte_list_remove(parent_pte, &sp->parent_ptes);
1732 static void drop_parent_pte(struct kvm_mmu_page *sp,
1735 mmu_page_remove_parent_pte(sp, parent_pte);
1736 mmu_spte_clear_no_track(parent_pte);
1739 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1741 struct kvm_mmu_page *sp;
1743 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1744 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1746 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1747 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1750 * The active_mmu_pages list is the FIFO list, do not move the
1751 * page until it is zapped. kvm_zap_obsolete_pages depends on
1752 * this feature. See the comments in kvm_zap_obsolete_pages().
1754 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1755 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1759 static void mark_unsync(u64 *spte);
1760 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1763 struct rmap_iterator iter;
1765 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1770 static void mark_unsync(u64 *spte)
1772 struct kvm_mmu_page *sp;
1775 sp = page_header(__pa(spte));
1776 index = spte - sp->spt;
1777 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1779 if (sp->unsync_children++)
1781 kvm_mmu_mark_parents_unsync(sp);
1784 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1785 struct kvm_mmu_page *sp)
1790 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1794 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1795 struct kvm_mmu_page *sp, u64 *spte,
1801 #define KVM_PAGE_ARRAY_NR 16
1803 struct kvm_mmu_pages {
1804 struct mmu_page_and_offset {
1805 struct kvm_mmu_page *sp;
1807 } page[KVM_PAGE_ARRAY_NR];
1811 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1817 for (i=0; i < pvec->nr; i++)
1818 if (pvec->page[i].sp == sp)
1821 pvec->page[pvec->nr].sp = sp;
1822 pvec->page[pvec->nr].idx = idx;
1824 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1827 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1829 --sp->unsync_children;
1830 WARN_ON((int)sp->unsync_children < 0);
1831 __clear_bit(idx, sp->unsync_child_bitmap);
1834 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1835 struct kvm_mmu_pages *pvec)
1837 int i, ret, nr_unsync_leaf = 0;
1839 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1840 struct kvm_mmu_page *child;
1841 u64 ent = sp->spt[i];
1843 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1844 clear_unsync_child_bit(sp, i);
1848 child = page_header(ent & PT64_BASE_ADDR_MASK);
1850 if (child->unsync_children) {
1851 if (mmu_pages_add(pvec, child, i))
1854 ret = __mmu_unsync_walk(child, pvec);
1856 clear_unsync_child_bit(sp, i);
1858 } else if (ret > 0) {
1859 nr_unsync_leaf += ret;
1862 } else if (child->unsync) {
1864 if (mmu_pages_add(pvec, child, i))
1867 clear_unsync_child_bit(sp, i);
1870 return nr_unsync_leaf;
1873 #define INVALID_INDEX (-1)
1875 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1876 struct kvm_mmu_pages *pvec)
1879 if (!sp->unsync_children)
1882 mmu_pages_add(pvec, sp, INVALID_INDEX);
1883 return __mmu_unsync_walk(sp, pvec);
1886 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1888 WARN_ON(!sp->unsync);
1889 trace_kvm_mmu_sync_page(sp);
1891 --kvm->stat.mmu_unsync;
1894 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1895 struct list_head *invalid_list);
1896 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1897 struct list_head *invalid_list);
1900 * NOTE: we should pay more attention on the zapped-obsolete page
1901 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1902 * since it has been deleted from active_mmu_pages but still can be found
1905 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1906 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1907 * all the obsolete pages.
1909 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1910 hlist_for_each_entry(_sp, \
1911 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1912 if ((_sp)->gfn != (_gfn)) {} else
1914 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1915 for_each_gfn_sp(_kvm, _sp, _gfn) \
1916 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1918 /* @sp->gfn should be write-protected at the call site */
1919 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1920 struct list_head *invalid_list, bool clear_unsync)
1922 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1923 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1928 kvm_unlink_unsync_page(vcpu->kvm, sp);
1930 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1931 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1938 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1939 struct list_head *invalid_list,
1940 bool remote_flush, bool local_flush)
1942 if (!list_empty(invalid_list)) {
1943 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
1948 kvm_flush_remote_tlbs(vcpu->kvm);
1949 else if (local_flush)
1950 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1953 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1954 struct kvm_mmu_page *sp)
1956 LIST_HEAD(invalid_list);
1959 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1960 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, !ret);
1965 #ifdef CONFIG_KVM_MMU_AUDIT
1966 #include "mmu_audit.c"
1968 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1969 static void mmu_audit_disable(void) { }
1972 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1973 struct list_head *invalid_list)
1975 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1978 /* @gfn should be write-protected at the call site */
1979 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1981 struct kvm_mmu_page *s;
1982 LIST_HEAD(invalid_list);
1985 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1989 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1990 kvm_unlink_unsync_page(vcpu->kvm, s);
1991 if (!__kvm_sync_page(vcpu, s, &invalid_list, false))
1995 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1998 struct mmu_page_path {
1999 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
2000 unsigned int idx[PT64_ROOT_LEVEL];
2003 #define for_each_sp(pvec, sp, parents, i) \
2004 for (i = mmu_pages_first(&pvec, &parents); \
2005 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2006 i = mmu_pages_next(&pvec, &parents, i))
2008 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2009 struct mmu_page_path *parents,
2014 for (n = i+1; n < pvec->nr; n++) {
2015 struct kvm_mmu_page *sp = pvec->page[n].sp;
2016 unsigned idx = pvec->page[n].idx;
2017 int level = sp->role.level;
2019 parents->idx[level-1] = idx;
2020 if (level == PT_PAGE_TABLE_LEVEL)
2023 parents->parent[level-2] = sp;
2029 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2030 struct mmu_page_path *parents)
2032 struct kvm_mmu_page *sp;
2038 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2040 sp = pvec->page[0].sp;
2041 level = sp->role.level;
2042 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2044 parents->parent[level-2] = sp;
2046 /* Also set up a sentinel. Further entries in pvec are all
2047 * children of sp, so this element is never overwritten.
2049 parents->parent[level-1] = NULL;
2050 return mmu_pages_next(pvec, parents, 0);
2053 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2055 struct kvm_mmu_page *sp;
2056 unsigned int level = 0;
2059 unsigned int idx = parents->idx[level];
2060 sp = parents->parent[level];
2064 WARN_ON(idx == INVALID_INDEX);
2065 clear_unsync_child_bit(sp, idx);
2067 } while (!sp->unsync_children);
2070 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2071 struct kvm_mmu_page *parent)
2074 struct kvm_mmu_page *sp;
2075 struct mmu_page_path parents;
2076 struct kvm_mmu_pages pages;
2077 LIST_HEAD(invalid_list);
2079 while (mmu_unsync_walk(parent, &pages)) {
2080 bool protected = false;
2083 for_each_sp(pages, sp, parents, i)
2084 protected |= rmap_write_protect(vcpu, sp->gfn);
2087 kvm_flush_remote_tlbs(vcpu->kvm);
2089 for_each_sp(pages, sp, parents, i) {
2090 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2093 mmu_pages_clear_parents(&parents);
2095 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2096 cond_resched_lock(&vcpu->kvm->mmu_lock);
2100 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2102 atomic_set(&sp->write_flooding_count, 0);
2105 static void clear_sp_write_flooding_count(u64 *spte)
2107 struct kvm_mmu_page *sp = page_header(__pa(spte));
2109 __clear_sp_write_flooding_count(sp);
2112 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2114 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2117 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2124 union kvm_mmu_page_role role;
2126 struct kvm_mmu_page *sp;
2127 bool need_sync = false;
2129 role = vcpu->arch.mmu.base_role;
2131 role.direct = direct;
2134 role.access = access;
2135 if (!vcpu->arch.mmu.direct_map
2136 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2137 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2138 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2139 role.quadrant = quadrant;
2141 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
2142 if (is_obsolete_sp(vcpu->kvm, sp))
2145 if (!need_sync && sp->unsync)
2148 if (sp->role.word != role.word)
2151 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
2154 if (sp->unsync_children)
2155 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2157 __clear_sp_write_flooding_count(sp);
2158 trace_kvm_mmu_get_page(sp, false);
2162 ++vcpu->kvm->stat.mmu_cache_miss;
2164 sp = kvm_mmu_alloc_page(vcpu, direct);
2168 hlist_add_head(&sp->hash_link,
2169 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2172 * we should do write protection before syncing pages
2173 * otherwise the content of the synced shadow page may
2174 * be inconsistent with guest page table.
2176 account_shadowed(vcpu->kvm, sp);
2177 if (level == PT_PAGE_TABLE_LEVEL &&
2178 rmap_write_protect(vcpu, gfn))
2179 kvm_flush_remote_tlbs(vcpu->kvm);
2181 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2182 kvm_sync_pages(vcpu, gfn);
2184 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2185 clear_page(sp->spt);
2186 trace_kvm_mmu_get_page(sp, true);
2190 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2191 struct kvm_vcpu *vcpu, u64 addr)
2193 iterator->addr = addr;
2194 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2195 iterator->level = vcpu->arch.mmu.shadow_root_level;
2197 if (iterator->level == PT64_ROOT_LEVEL &&
2198 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2199 !vcpu->arch.mmu.direct_map)
2202 if (iterator->level == PT32E_ROOT_LEVEL) {
2203 iterator->shadow_addr
2204 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2205 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2207 if (!iterator->shadow_addr)
2208 iterator->level = 0;
2212 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2214 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2217 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2218 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2222 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2225 if (is_last_spte(spte, iterator->level)) {
2226 iterator->level = 0;
2230 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2234 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2236 return __shadow_walk_next(iterator, *iterator->sptep);
2239 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2240 struct kvm_mmu_page *sp)
2244 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2245 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2247 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2248 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2250 mmu_spte_set(sptep, spte);
2252 mmu_page_add_parent_pte(vcpu, sp, sptep);
2254 if (sp->unsync_children || sp->unsync)
2258 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2259 unsigned direct_access)
2261 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2262 struct kvm_mmu_page *child;
2265 * For the direct sp, if the guest pte's dirty bit
2266 * changed form clean to dirty, it will corrupt the
2267 * sp's access: allow writable in the read-only sp,
2268 * so we should update the spte at this point to get
2269 * a new sp with the correct access.
2271 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2272 if (child->role.access == direct_access)
2275 drop_parent_pte(child, sptep);
2276 kvm_flush_remote_tlbs(vcpu->kvm);
2280 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2284 struct kvm_mmu_page *child;
2287 if (is_shadow_present_pte(pte)) {
2288 if (is_last_spte(pte, sp->role.level)) {
2289 drop_spte(kvm, spte);
2290 if (is_large_pte(pte))
2293 child = page_header(pte & PT64_BASE_ADDR_MASK);
2294 drop_parent_pte(child, spte);
2299 if (is_mmio_spte(pte))
2300 mmu_spte_clear_no_track(spte);
2305 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2306 struct kvm_mmu_page *sp)
2310 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2311 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2314 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2317 struct rmap_iterator iter;
2319 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2320 drop_parent_pte(sp, sptep);
2323 static int mmu_zap_unsync_children(struct kvm *kvm,
2324 struct kvm_mmu_page *parent,
2325 struct list_head *invalid_list)
2328 struct mmu_page_path parents;
2329 struct kvm_mmu_pages pages;
2331 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2334 while (mmu_unsync_walk(parent, &pages)) {
2335 struct kvm_mmu_page *sp;
2337 for_each_sp(pages, sp, parents, i) {
2338 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2339 mmu_pages_clear_parents(&parents);
2347 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2348 struct list_head *invalid_list)
2352 trace_kvm_mmu_prepare_zap_page(sp);
2353 ++kvm->stat.mmu_shadow_zapped;
2354 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2355 kvm_mmu_page_unlink_children(kvm, sp);
2356 kvm_mmu_unlink_parents(kvm, sp);
2358 if (!sp->role.invalid && !sp->role.direct)
2359 unaccount_shadowed(kvm, sp);
2362 kvm_unlink_unsync_page(kvm, sp);
2363 if (!sp->root_count) {
2366 list_move(&sp->link, invalid_list);
2367 kvm_mod_used_mmu_pages(kvm, -1);
2369 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2372 * The obsolete pages can not be used on any vcpus.
2373 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2375 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2376 kvm_reload_remote_mmus(kvm);
2379 sp->role.invalid = 1;
2383 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2384 struct list_head *invalid_list)
2386 struct kvm_mmu_page *sp, *nsp;
2388 if (list_empty(invalid_list))
2392 * wmb: make sure everyone sees our modifications to the page tables
2393 * rmb: make sure we see changes to vcpu->mode
2398 * Wait for all vcpus to exit guest mode and/or lockless shadow
2401 kvm_flush_remote_tlbs(kvm);
2403 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2404 WARN_ON(!sp->role.invalid || sp->root_count);
2405 kvm_mmu_free_page(sp);
2409 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2410 struct list_head *invalid_list)
2412 struct kvm_mmu_page *sp;
2414 if (list_empty(&kvm->arch.active_mmu_pages))
2417 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2418 struct kvm_mmu_page, link);
2419 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2425 * Changing the number of mmu pages allocated to the vm
2426 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2428 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2430 LIST_HEAD(invalid_list);
2432 spin_lock(&kvm->mmu_lock);
2434 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2435 /* Need to free some mmu pages to achieve the goal. */
2436 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2437 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2440 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2441 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2444 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2446 spin_unlock(&kvm->mmu_lock);
2449 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2451 struct kvm_mmu_page *sp;
2452 LIST_HEAD(invalid_list);
2455 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2457 spin_lock(&kvm->mmu_lock);
2458 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2459 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2462 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2464 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2465 spin_unlock(&kvm->mmu_lock);
2469 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2471 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2473 trace_kvm_mmu_unsync_page(sp);
2474 ++vcpu->kvm->stat.mmu_unsync;
2477 kvm_mmu_mark_parents_unsync(sp);
2480 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2483 struct kvm_mmu_page *sp;
2485 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2488 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2495 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2496 kvm_unsync_page(vcpu, sp);
2502 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2505 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2510 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2511 unsigned pte_access, int level,
2512 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2513 bool can_unsync, bool host_writable)
2518 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2521 spte = PT_PRESENT_MASK;
2523 spte |= shadow_accessed_mask;
2525 if (pte_access & ACC_EXEC_MASK)
2526 spte |= shadow_x_mask;
2528 spte |= shadow_nx_mask;
2530 if (pte_access & ACC_USER_MASK)
2531 spte |= shadow_user_mask;
2533 if (level > PT_PAGE_TABLE_LEVEL)
2534 spte |= PT_PAGE_SIZE_MASK;
2536 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2537 kvm_is_mmio_pfn(pfn));
2540 spte |= SPTE_HOST_WRITEABLE;
2542 pte_access &= ~ACC_WRITE_MASK;
2544 spte |= (u64)pfn << PAGE_SHIFT;
2546 if (pte_access & ACC_WRITE_MASK) {
2549 * Other vcpu creates new sp in the window between
2550 * mapping_level() and acquiring mmu-lock. We can
2551 * allow guest to retry the access, the mapping can
2552 * be fixed if guest refault.
2554 if (level > PT_PAGE_TABLE_LEVEL &&
2555 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2558 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2561 * Optimization: for pte sync, if spte was writable the hash
2562 * lookup is unnecessary (and expensive). Write protection
2563 * is responsibility of mmu_get_page / kvm_sync_page.
2564 * Same reasoning can be applied to dirty page accounting.
2566 if (!can_unsync && is_writable_pte(*sptep))
2569 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2570 pgprintk("%s: found shadow page for %llx, marking ro\n",
2573 pte_access &= ~ACC_WRITE_MASK;
2574 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2578 if (pte_access & ACC_WRITE_MASK) {
2579 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2580 spte |= shadow_dirty_mask;
2584 if (mmu_spte_update(sptep, spte))
2585 kvm_flush_remote_tlbs(vcpu->kvm);
2590 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2591 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2592 bool speculative, bool host_writable)
2594 int was_rmapped = 0;
2596 bool emulate = false;
2598 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2599 *sptep, write_fault, gfn);
2601 if (is_shadow_present_pte(*sptep)) {
2603 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2604 * the parent of the now unreachable PTE.
2606 if (level > PT_PAGE_TABLE_LEVEL &&
2607 !is_large_pte(*sptep)) {
2608 struct kvm_mmu_page *child;
2611 child = page_header(pte & PT64_BASE_ADDR_MASK);
2612 drop_parent_pte(child, sptep);
2613 kvm_flush_remote_tlbs(vcpu->kvm);
2614 } else if (pfn != spte_to_pfn(*sptep)) {
2615 pgprintk("hfn old %llx new %llx\n",
2616 spte_to_pfn(*sptep), pfn);
2617 drop_spte(vcpu->kvm, sptep);
2618 kvm_flush_remote_tlbs(vcpu->kvm);
2623 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2624 true, host_writable)) {
2627 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2630 if (unlikely(is_mmio_spte(*sptep)))
2633 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2634 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2635 is_large_pte(*sptep)? "2MB" : "4kB",
2636 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2638 if (!was_rmapped && is_large_pte(*sptep))
2639 ++vcpu->kvm->stat.lpages;
2641 if (is_shadow_present_pte(*sptep)) {
2643 rmap_count = rmap_add(vcpu, sptep, gfn);
2644 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2645 rmap_recycle(vcpu, sptep, gfn);
2649 kvm_release_pfn_clean(pfn);
2654 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2657 struct kvm_memory_slot *slot;
2659 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2661 return KVM_PFN_ERR_FAULT;
2663 return gfn_to_pfn_memslot_atomic(slot, gfn);
2666 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2667 struct kvm_mmu_page *sp,
2668 u64 *start, u64 *end)
2670 struct page *pages[PTE_PREFETCH_NUM];
2671 struct kvm_memory_slot *slot;
2672 unsigned access = sp->role.access;
2676 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2677 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2681 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2685 for (i = 0; i < ret; i++, gfn++, start++)
2686 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2687 page_to_pfn(pages[i]), true, true);
2692 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2693 struct kvm_mmu_page *sp, u64 *sptep)
2695 u64 *spte, *start = NULL;
2698 WARN_ON(!sp->role.direct);
2700 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2703 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2704 if (is_shadow_present_pte(*spte) || spte == sptep) {
2707 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2715 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2717 struct kvm_mmu_page *sp;
2720 * Since it's no accessed bit on EPT, it's no way to
2721 * distinguish between actually accessed translations
2722 * and prefetched, so disable pte prefetch if EPT is
2725 if (!shadow_accessed_mask)
2728 sp = page_header(__pa(sptep));
2729 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2732 __direct_pte_prefetch(vcpu, sp, sptep);
2735 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2736 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2738 struct kvm_shadow_walk_iterator iterator;
2739 struct kvm_mmu_page *sp;
2743 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2746 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2747 if (iterator.level == level) {
2748 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2749 write, level, gfn, pfn, prefault,
2751 direct_pte_prefetch(vcpu, iterator.sptep);
2752 ++vcpu->stat.pf_fixed;
2756 drop_large_spte(vcpu, iterator.sptep);
2757 if (!is_shadow_present_pte(*iterator.sptep)) {
2758 u64 base_addr = iterator.addr;
2760 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2761 pseudo_gfn = base_addr >> PAGE_SHIFT;
2762 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2763 iterator.level - 1, 1, ACC_ALL);
2765 link_shadow_page(vcpu, iterator.sptep, sp);
2771 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2775 info.si_signo = SIGBUS;
2777 info.si_code = BUS_MCEERR_AR;
2778 info.si_addr = (void __user *)address;
2779 info.si_addr_lsb = PAGE_SHIFT;
2781 send_sig_info(SIGBUS, &info, tsk);
2784 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2787 * Do not cache the mmio info caused by writing the readonly gfn
2788 * into the spte otherwise read access on readonly gfn also can
2789 * caused mmio page fault and treat it as mmio access.
2790 * Return 1 to tell kvm to emulate it.
2792 if (pfn == KVM_PFN_ERR_RO_FAULT)
2795 if (pfn == KVM_PFN_ERR_HWPOISON) {
2796 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2803 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2804 gfn_t *gfnp, kvm_pfn_t *pfnp,
2807 kvm_pfn_t pfn = *pfnp;
2809 int level = *levelp;
2812 * Check if it's a transparent hugepage. If this would be an
2813 * hugetlbfs page, level wouldn't be set to
2814 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2817 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2818 level == PT_PAGE_TABLE_LEVEL &&
2819 PageTransCompound(pfn_to_page(pfn)) &&
2820 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2823 * mmu_notifier_retry was successful and we hold the
2824 * mmu_lock here, so the pmd can't become splitting
2825 * from under us, and in turn
2826 * __split_huge_page_refcount() can't run from under
2827 * us and we can safely transfer the refcount from
2828 * PG_tail to PG_head as we switch the pfn to tail to
2831 *levelp = level = PT_DIRECTORY_LEVEL;
2832 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2833 VM_BUG_ON((gfn & mask) != (pfn & mask));
2837 kvm_release_pfn_clean(pfn);
2845 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2846 kvm_pfn_t pfn, unsigned access, int *ret_val)
2848 /* The pfn is invalid, report the error! */
2849 if (unlikely(is_error_pfn(pfn))) {
2850 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2854 if (unlikely(is_noslot_pfn(pfn)))
2855 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2860 static bool page_fault_can_be_fast(u32 error_code)
2863 * Do not fix the mmio spte with invalid generation number which
2864 * need to be updated by slow page fault path.
2866 if (unlikely(error_code & PFERR_RSVD_MASK))
2870 * #PF can be fast only if the shadow page table is present and it
2871 * is caused by write-protect, that means we just need change the
2872 * W bit of the spte which can be done out of mmu-lock.
2874 if (!(error_code & PFERR_PRESENT_MASK) ||
2875 !(error_code & PFERR_WRITE_MASK))
2882 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2883 u64 *sptep, u64 spte)
2887 WARN_ON(!sp->role.direct);
2890 * The gfn of direct spte is stable since it is calculated
2893 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2896 * Theoretically we could also set dirty bit (and flush TLB) here in
2897 * order to eliminate unnecessary PML logging. See comments in
2898 * set_spte. But fast_page_fault is very unlikely to happen with PML
2899 * enabled, so we do not do this. This might result in the same GPA
2900 * to be logged in PML buffer again when the write really happens, and
2901 * eventually to be called by mark_page_dirty twice. But it's also no
2902 * harm. This also avoids the TLB flush needed after setting dirty bit
2903 * so non-PML cases won't be impacted.
2905 * Compare with set_spte where instead shadow_dirty_mask is set.
2907 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2908 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2915 * - true: let the vcpu to access on the same address again.
2916 * - false: let the real page fault path to fix it.
2918 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2921 struct kvm_shadow_walk_iterator iterator;
2922 struct kvm_mmu_page *sp;
2926 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2929 if (!page_fault_can_be_fast(error_code))
2932 walk_shadow_page_lockless_begin(vcpu);
2933 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2934 if (!is_shadow_present_pte(spte) || iterator.level < level)
2938 * If the mapping has been changed, let the vcpu fault on the
2939 * same address again.
2941 if (!is_shadow_present_pte(spte)) {
2946 sp = page_header(__pa(iterator.sptep));
2947 if (!is_last_spte(spte, sp->role.level))
2951 * Check if it is a spurious fault caused by TLB lazily flushed.
2953 * Need not check the access of upper level table entries since
2954 * they are always ACC_ALL.
2956 if (is_writable_pte(spte)) {
2962 * Currently, to simplify the code, only the spte write-protected
2963 * by dirty-log can be fast fixed.
2965 if (!spte_is_locklessly_modifiable(spte))
2969 * Do not fix write-permission on the large spte since we only dirty
2970 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2971 * that means other pages are missed if its slot is dirty-logged.
2973 * Instead, we let the slow page fault path create a normal spte to
2976 * See the comments in kvm_arch_commit_memory_region().
2978 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2982 * Currently, fast page fault only works for direct mapping since
2983 * the gfn is not stable for indirect shadow page.
2984 * See Documentation/virtual/kvm/locking.txt to get more detail.
2986 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2988 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2990 walk_shadow_page_lockless_end(vcpu);
2995 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2996 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
2997 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2999 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3000 gfn_t gfn, bool prefault)
3004 bool force_pt_level = false;
3006 unsigned long mmu_seq;
3007 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3009 level = mapping_level(vcpu, gfn, &force_pt_level);
3010 if (likely(!force_pt_level)) {
3012 * This path builds a PAE pagetable - so we can map
3013 * 2mb pages at maximum. Therefore check if the level
3014 * is larger than that.
3016 if (level > PT_DIRECTORY_LEVEL)
3017 level = PT_DIRECTORY_LEVEL;
3019 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3022 if (fast_page_fault(vcpu, v, level, error_code))
3025 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3028 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3031 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3034 spin_lock(&vcpu->kvm->mmu_lock);
3035 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3037 make_mmu_pages_available(vcpu);
3038 if (likely(!force_pt_level))
3039 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3040 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3041 spin_unlock(&vcpu->kvm->mmu_lock);
3046 spin_unlock(&vcpu->kvm->mmu_lock);
3047 kvm_release_pfn_clean(pfn);
3052 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3055 struct kvm_mmu_page *sp;
3056 LIST_HEAD(invalid_list);
3058 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3061 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3062 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3063 vcpu->arch.mmu.direct_map)) {
3064 hpa_t root = vcpu->arch.mmu.root_hpa;
3066 spin_lock(&vcpu->kvm->mmu_lock);
3067 sp = page_header(root);
3069 if (!sp->root_count && sp->role.invalid) {
3070 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3071 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3073 spin_unlock(&vcpu->kvm->mmu_lock);
3074 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3078 spin_lock(&vcpu->kvm->mmu_lock);
3079 for (i = 0; i < 4; ++i) {
3080 hpa_t root = vcpu->arch.mmu.pae_root[i];
3083 root &= PT64_BASE_ADDR_MASK;
3084 sp = page_header(root);
3086 if (!sp->root_count && sp->role.invalid)
3087 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3090 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3092 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3093 spin_unlock(&vcpu->kvm->mmu_lock);
3094 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3097 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3101 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3102 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3109 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3111 struct kvm_mmu_page *sp;
3114 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3115 spin_lock(&vcpu->kvm->mmu_lock);
3116 make_mmu_pages_available(vcpu);
3117 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3119 spin_unlock(&vcpu->kvm->mmu_lock);
3120 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3121 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3122 for (i = 0; i < 4; ++i) {
3123 hpa_t root = vcpu->arch.mmu.pae_root[i];
3125 MMU_WARN_ON(VALID_PAGE(root));
3126 spin_lock(&vcpu->kvm->mmu_lock);
3127 make_mmu_pages_available(vcpu);
3128 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3129 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3130 root = __pa(sp->spt);
3132 spin_unlock(&vcpu->kvm->mmu_lock);
3133 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3135 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3142 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3144 struct kvm_mmu_page *sp;
3149 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3151 if (mmu_check_root(vcpu, root_gfn))
3155 * Do we shadow a long mode page table? If so we need to
3156 * write-protect the guests page table root.
3158 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3159 hpa_t root = vcpu->arch.mmu.root_hpa;
3161 MMU_WARN_ON(VALID_PAGE(root));
3163 spin_lock(&vcpu->kvm->mmu_lock);
3164 make_mmu_pages_available(vcpu);
3165 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3167 root = __pa(sp->spt);
3169 spin_unlock(&vcpu->kvm->mmu_lock);
3170 vcpu->arch.mmu.root_hpa = root;
3175 * We shadow a 32 bit page table. This may be a legacy 2-level
3176 * or a PAE 3-level page table. In either case we need to be aware that
3177 * the shadow page table may be a PAE or a long mode page table.
3179 pm_mask = PT_PRESENT_MASK;
3180 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3181 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3183 for (i = 0; i < 4; ++i) {
3184 hpa_t root = vcpu->arch.mmu.pae_root[i];
3186 MMU_WARN_ON(VALID_PAGE(root));
3187 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3188 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3189 if (!is_present_gpte(pdptr)) {
3190 vcpu->arch.mmu.pae_root[i] = 0;
3193 root_gfn = pdptr >> PAGE_SHIFT;
3194 if (mmu_check_root(vcpu, root_gfn))
3197 spin_lock(&vcpu->kvm->mmu_lock);
3198 make_mmu_pages_available(vcpu);
3199 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3201 root = __pa(sp->spt);
3203 spin_unlock(&vcpu->kvm->mmu_lock);
3205 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3207 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3210 * If we shadow a 32 bit page table with a long mode page
3211 * table we enter this path.
3213 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3214 if (vcpu->arch.mmu.lm_root == NULL) {
3216 * The additional page necessary for this is only
3217 * allocated on demand.
3222 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3223 if (lm_root == NULL)
3226 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3228 vcpu->arch.mmu.lm_root = lm_root;
3231 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3237 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3239 if (vcpu->arch.mmu.direct_map)
3240 return mmu_alloc_direct_roots(vcpu);
3242 return mmu_alloc_shadow_roots(vcpu);
3245 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3248 struct kvm_mmu_page *sp;
3250 if (vcpu->arch.mmu.direct_map)
3253 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3256 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3257 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3258 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3259 hpa_t root = vcpu->arch.mmu.root_hpa;
3260 sp = page_header(root);
3261 mmu_sync_children(vcpu, sp);
3262 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3265 for (i = 0; i < 4; ++i) {
3266 hpa_t root = vcpu->arch.mmu.pae_root[i];
3268 if (root && VALID_PAGE(root)) {
3269 root &= PT64_BASE_ADDR_MASK;
3270 sp = page_header(root);
3271 mmu_sync_children(vcpu, sp);
3274 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3277 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3279 spin_lock(&vcpu->kvm->mmu_lock);
3280 mmu_sync_roots(vcpu);
3281 spin_unlock(&vcpu->kvm->mmu_lock);
3283 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3285 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3286 u32 access, struct x86_exception *exception)
3289 exception->error_code = 0;
3293 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3295 struct x86_exception *exception)
3298 exception->error_code = 0;
3299 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3303 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3305 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3307 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3308 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3311 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3313 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3316 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3318 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3321 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3324 return vcpu_match_mmio_gpa(vcpu, addr);
3326 return vcpu_match_mmio_gva(vcpu, addr);
3329 /* return true if reserved bit is detected on spte. */
3331 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3333 struct kvm_shadow_walk_iterator iterator;
3334 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3336 bool reserved = false;
3338 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3341 walk_shadow_page_lockless_begin(vcpu);
3343 for (shadow_walk_init(&iterator, vcpu, addr),
3344 leaf = root = iterator.level;
3345 shadow_walk_okay(&iterator);
3346 __shadow_walk_next(&iterator, spte)) {
3347 spte = mmu_spte_get_lockless(iterator.sptep);
3349 sptes[leaf - 1] = spte;
3352 if (!is_shadow_present_pte(spte))
3355 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3359 walk_shadow_page_lockless_end(vcpu);
3362 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3364 while (root > leaf) {
3365 pr_err("------ spte 0x%llx level %d.\n",
3366 sptes[root - 1], root);
3375 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3380 if (mmio_info_in_cache(vcpu, addr, direct))
3381 return RET_MMIO_PF_EMULATE;
3383 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3384 if (WARN_ON(reserved))
3385 return RET_MMIO_PF_BUG;
3387 if (is_mmio_spte(spte)) {
3388 gfn_t gfn = get_mmio_spte_gfn(spte);
3389 unsigned access = get_mmio_spte_access(spte);
3391 if (!check_mmio_spte(vcpu, spte))
3392 return RET_MMIO_PF_INVALID;
3397 trace_handle_mmio_page_fault(addr, gfn, access);
3398 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3399 return RET_MMIO_PF_EMULATE;
3403 * If the page table is zapped by other cpus, let CPU fault again on
3406 return RET_MMIO_PF_RETRY;
3408 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3410 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3411 u32 error_code, gfn_t gfn)
3413 if (unlikely(error_code & PFERR_RSVD_MASK))
3416 if (!(error_code & PFERR_PRESENT_MASK) ||
3417 !(error_code & PFERR_WRITE_MASK))
3421 * guest is writing the page which is write tracked which can
3422 * not be fixed by page fault handler.
3424 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3430 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3432 struct kvm_shadow_walk_iterator iterator;
3435 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3438 walk_shadow_page_lockless_begin(vcpu);
3439 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3440 clear_sp_write_flooding_count(iterator.sptep);
3441 if (!is_shadow_present_pte(spte))
3444 walk_shadow_page_lockless_end(vcpu);
3447 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3448 u32 error_code, bool prefault)
3450 gfn_t gfn = gva >> PAGE_SHIFT;
3453 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3455 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3458 r = mmu_topup_memory_caches(vcpu);
3462 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3465 return nonpaging_map(vcpu, gva & PAGE_MASK,
3466 error_code, gfn, prefault);
3469 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3471 struct kvm_arch_async_pf arch;
3473 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3475 arch.direct_map = vcpu->arch.mmu.direct_map;
3476 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3478 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3481 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3483 if (unlikely(!lapic_in_kernel(vcpu) ||
3484 kvm_event_needs_reinjection(vcpu)))
3487 return kvm_x86_ops->interrupt_allowed(vcpu);
3490 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3491 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3493 struct kvm_memory_slot *slot;
3496 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3498 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3500 return false; /* *pfn has correct page already */
3502 if (!prefault && can_do_async_pf(vcpu)) {
3503 trace_kvm_try_async_get_page(gva, gfn);
3504 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3505 trace_kvm_async_pf_doublefault(gva, gfn);
3506 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3508 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3512 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3517 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3519 int page_num = KVM_PAGES_PER_HPAGE(level);
3521 gfn &= ~(page_num - 1);
3523 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3526 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3532 bool force_pt_level;
3533 gfn_t gfn = gpa >> PAGE_SHIFT;
3534 unsigned long mmu_seq;
3535 int write = error_code & PFERR_WRITE_MASK;
3538 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3540 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3543 r = mmu_topup_memory_caches(vcpu);
3547 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3548 PT_DIRECTORY_LEVEL);
3549 level = mapping_level(vcpu, gfn, &force_pt_level);
3550 if (likely(!force_pt_level)) {
3551 if (level > PT_DIRECTORY_LEVEL &&
3552 !check_hugepage_cache_consistency(vcpu, gfn, level))
3553 level = PT_DIRECTORY_LEVEL;
3554 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3557 if (fast_page_fault(vcpu, gpa, level, error_code))
3560 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3563 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3566 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3569 spin_lock(&vcpu->kvm->mmu_lock);
3570 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3572 make_mmu_pages_available(vcpu);
3573 if (likely(!force_pt_level))
3574 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3575 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3576 spin_unlock(&vcpu->kvm->mmu_lock);
3581 spin_unlock(&vcpu->kvm->mmu_lock);
3582 kvm_release_pfn_clean(pfn);
3586 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3587 struct kvm_mmu *context)
3589 context->page_fault = nonpaging_page_fault;
3590 context->gva_to_gpa = nonpaging_gva_to_gpa;
3591 context->sync_page = nonpaging_sync_page;
3592 context->invlpg = nonpaging_invlpg;
3593 context->update_pte = nonpaging_update_pte;
3594 context->root_level = 0;
3595 context->shadow_root_level = PT32E_ROOT_LEVEL;
3596 context->root_hpa = INVALID_PAGE;
3597 context->direct_map = true;
3598 context->nx = false;
3601 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3603 mmu_free_roots(vcpu);
3606 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3608 return kvm_read_cr3(vcpu);
3611 static void inject_page_fault(struct kvm_vcpu *vcpu,
3612 struct x86_exception *fault)
3614 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3617 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3618 unsigned access, int *nr_present)
3620 if (unlikely(is_mmio_spte(*sptep))) {
3621 if (gfn != get_mmio_spte_gfn(*sptep)) {
3622 mmu_spte_clear_no_track(sptep);
3627 mark_mmio_spte(vcpu, sptep, gfn, access);
3634 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3639 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3640 return mmu->last_pte_bitmap & (1 << index);
3643 #define PTTYPE_EPT 18 /* arbitrary */
3644 #define PTTYPE PTTYPE_EPT
3645 #include "paging_tmpl.h"
3649 #include "paging_tmpl.h"
3653 #include "paging_tmpl.h"
3657 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3658 struct rsvd_bits_validate *rsvd_check,
3659 int maxphyaddr, int level, bool nx, bool gbpages,
3662 u64 exb_bit_rsvd = 0;
3663 u64 gbpages_bit_rsvd = 0;
3664 u64 nonleaf_bit8_rsvd = 0;
3666 rsvd_check->bad_mt_xwr = 0;
3669 exb_bit_rsvd = rsvd_bits(63, 63);
3671 gbpages_bit_rsvd = rsvd_bits(7, 7);
3674 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3675 * leaf entries) on AMD CPUs only.
3678 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3681 case PT32_ROOT_LEVEL:
3682 /* no rsvd bits for 2 level 4K page table entries */
3683 rsvd_check->rsvd_bits_mask[0][1] = 0;
3684 rsvd_check->rsvd_bits_mask[0][0] = 0;
3685 rsvd_check->rsvd_bits_mask[1][0] =
3686 rsvd_check->rsvd_bits_mask[0][0];
3689 rsvd_check->rsvd_bits_mask[1][1] = 0;
3693 if (is_cpuid_PSE36())
3694 /* 36bits PSE 4MB page */
3695 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3697 /* 32 bits PSE 4MB page */
3698 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3700 case PT32E_ROOT_LEVEL:
3701 rsvd_check->rsvd_bits_mask[0][2] =
3702 rsvd_bits(maxphyaddr, 63) |
3703 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3704 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3705 rsvd_bits(maxphyaddr, 62); /* PDE */
3706 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3707 rsvd_bits(maxphyaddr, 62); /* PTE */
3708 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3709 rsvd_bits(maxphyaddr, 62) |
3710 rsvd_bits(13, 20); /* large page */
3711 rsvd_check->rsvd_bits_mask[1][0] =
3712 rsvd_check->rsvd_bits_mask[0][0];
3714 case PT64_ROOT_LEVEL:
3715 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3716 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3717 rsvd_bits(maxphyaddr, 51);
3718 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3719 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3720 rsvd_bits(maxphyaddr, 51);
3721 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3722 rsvd_bits(maxphyaddr, 51);
3723 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3724 rsvd_bits(maxphyaddr, 51);
3725 rsvd_check->rsvd_bits_mask[1][3] =
3726 rsvd_check->rsvd_bits_mask[0][3];
3727 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3728 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3730 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3731 rsvd_bits(maxphyaddr, 51) |
3732 rsvd_bits(13, 20); /* large page */
3733 rsvd_check->rsvd_bits_mask[1][0] =
3734 rsvd_check->rsvd_bits_mask[0][0];
3739 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3740 struct kvm_mmu *context)
3742 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3743 cpuid_maxphyaddr(vcpu), context->root_level,
3744 context->nx, guest_cpuid_has_gbpages(vcpu),
3745 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3749 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3750 int maxphyaddr, bool execonly)
3754 rsvd_check->rsvd_bits_mask[0][3] =
3755 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3756 rsvd_check->rsvd_bits_mask[0][2] =
3757 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3758 rsvd_check->rsvd_bits_mask[0][1] =
3759 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3760 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3763 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3764 rsvd_check->rsvd_bits_mask[1][2] =
3765 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3766 rsvd_check->rsvd_bits_mask[1][1] =
3767 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3768 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3770 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3771 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3772 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3773 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3774 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3776 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3777 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3779 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3782 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3783 struct kvm_mmu *context, bool execonly)
3785 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3786 cpuid_maxphyaddr(vcpu), execonly);
3790 * the page table on host is the shadow page table for the page
3791 * table in guest or amd nested guest, its mmu features completely
3792 * follow the features in guest.
3795 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3798 * Passing "true" to the last argument is okay; it adds a check
3799 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3801 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3802 boot_cpu_data.x86_phys_bits,
3803 context->shadow_root_level, context->nx,
3804 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3807 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3809 static inline bool boot_cpu_is_amd(void)
3811 WARN_ON_ONCE(!tdp_enabled);
3812 return shadow_x_mask == 0;
3816 * the direct page table on host, use as much mmu features as
3817 * possible, however, kvm currently does not do execution-protection.
3820 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3821 struct kvm_mmu *context)
3823 if (boot_cpu_is_amd())
3824 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3825 boot_cpu_data.x86_phys_bits,
3826 context->shadow_root_level, false,
3827 cpu_has_gbpages, true, true);
3829 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3830 boot_cpu_data.x86_phys_bits,
3836 * as the comments in reset_shadow_zero_bits_mask() except it
3837 * is the shadow page table for intel nested guest.
3840 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3841 struct kvm_mmu *context, bool execonly)
3843 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3844 boot_cpu_data.x86_phys_bits, execonly);
3847 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3848 struct kvm_mmu *mmu, bool ept)
3850 unsigned bit, byte, pfec;
3852 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3854 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3855 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3856 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3859 wf = pfec & PFERR_WRITE_MASK;
3860 uf = pfec & PFERR_USER_MASK;
3861 ff = pfec & PFERR_FETCH_MASK;
3863 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3864 * subject to SMAP restrictions, and cleared otherwise. The
3865 * bit is only meaningful if the SMAP bit is set in CR4.
3867 smapf = !(pfec & PFERR_RSVD_MASK);
3868 for (bit = 0; bit < 8; ++bit) {
3869 x = bit & ACC_EXEC_MASK;
3870 w = bit & ACC_WRITE_MASK;
3871 u = bit & ACC_USER_MASK;
3874 /* Not really needed: !nx will cause pte.nx to fault */
3876 /* Allow supervisor writes if !cr0.wp */
3877 w |= !is_write_protection(vcpu) && !uf;
3878 /* Disallow supervisor fetches of user code if cr4.smep */
3879 x &= !(cr4_smep && u && !uf);
3882 * SMAP:kernel-mode data accesses from user-mode
3883 * mappings should fault. A fault is considered
3884 * as a SMAP violation if all of the following
3885 * conditions are ture:
3886 * - X86_CR4_SMAP is set in CR4
3887 * - An user page is accessed
3888 * - Page fault in kernel mode
3889 * - if CPL = 3 or X86_EFLAGS_AC is clear
3891 * Here, we cover the first three conditions.
3892 * The fourth is computed dynamically in
3893 * permission_fault() and is in smapf.
3895 * Also, SMAP does not affect instruction
3896 * fetches, add the !ff check here to make it
3899 smap = cr4_smap && u && !uf && !ff;
3901 /* Not really needed: no U/S accesses on ept */
3904 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3906 map |= fault << bit;
3908 mmu->permissions[byte] = map;
3912 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3915 unsigned level, root_level = mmu->root_level;
3916 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3918 if (root_level == PT32E_ROOT_LEVEL)
3920 /* PT_PAGE_TABLE_LEVEL always terminates */
3921 map = 1 | (1 << ps_set_index);
3922 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3923 if (level <= PT_PDPE_LEVEL
3924 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3925 map |= 1 << (ps_set_index | (level - 1));
3927 mmu->last_pte_bitmap = map;
3930 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3931 struct kvm_mmu *context,
3934 context->nx = is_nx(vcpu);
3935 context->root_level = level;
3937 reset_rsvds_bits_mask(vcpu, context);
3938 update_permission_bitmask(vcpu, context, false);
3939 update_last_pte_bitmap(vcpu, context);
3941 MMU_WARN_ON(!is_pae(vcpu));
3942 context->page_fault = paging64_page_fault;
3943 context->gva_to_gpa = paging64_gva_to_gpa;
3944 context->sync_page = paging64_sync_page;
3945 context->invlpg = paging64_invlpg;
3946 context->update_pte = paging64_update_pte;
3947 context->shadow_root_level = level;
3948 context->root_hpa = INVALID_PAGE;
3949 context->direct_map = false;
3952 static void paging64_init_context(struct kvm_vcpu *vcpu,
3953 struct kvm_mmu *context)
3955 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3958 static void paging32_init_context(struct kvm_vcpu *vcpu,
3959 struct kvm_mmu *context)
3961 context->nx = false;
3962 context->root_level = PT32_ROOT_LEVEL;
3964 reset_rsvds_bits_mask(vcpu, context);
3965 update_permission_bitmask(vcpu, context, false);
3966 update_last_pte_bitmap(vcpu, context);
3968 context->page_fault = paging32_page_fault;
3969 context->gva_to_gpa = paging32_gva_to_gpa;
3970 context->sync_page = paging32_sync_page;
3971 context->invlpg = paging32_invlpg;
3972 context->update_pte = paging32_update_pte;
3973 context->shadow_root_level = PT32E_ROOT_LEVEL;
3974 context->root_hpa = INVALID_PAGE;
3975 context->direct_map = false;
3978 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3979 struct kvm_mmu *context)
3981 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3984 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3986 struct kvm_mmu *context = &vcpu->arch.mmu;
3988 context->base_role.word = 0;
3989 context->base_role.smm = is_smm(vcpu);
3990 context->page_fault = tdp_page_fault;
3991 context->sync_page = nonpaging_sync_page;
3992 context->invlpg = nonpaging_invlpg;
3993 context->update_pte = nonpaging_update_pte;
3994 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3995 context->root_hpa = INVALID_PAGE;
3996 context->direct_map = true;
3997 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3998 context->get_cr3 = get_cr3;
3999 context->get_pdptr = kvm_pdptr_read;
4000 context->inject_page_fault = kvm_inject_page_fault;
4002 if (!is_paging(vcpu)) {
4003 context->nx = false;
4004 context->gva_to_gpa = nonpaging_gva_to_gpa;
4005 context->root_level = 0;
4006 } else if (is_long_mode(vcpu)) {
4007 context->nx = is_nx(vcpu);
4008 context->root_level = PT64_ROOT_LEVEL;
4009 reset_rsvds_bits_mask(vcpu, context);
4010 context->gva_to_gpa = paging64_gva_to_gpa;
4011 } else if (is_pae(vcpu)) {
4012 context->nx = is_nx(vcpu);
4013 context->root_level = PT32E_ROOT_LEVEL;
4014 reset_rsvds_bits_mask(vcpu, context);
4015 context->gva_to_gpa = paging64_gva_to_gpa;
4017 context->nx = false;
4018 context->root_level = PT32_ROOT_LEVEL;
4019 reset_rsvds_bits_mask(vcpu, context);
4020 context->gva_to_gpa = paging32_gva_to_gpa;
4023 update_permission_bitmask(vcpu, context, false);
4024 update_last_pte_bitmap(vcpu, context);
4025 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4028 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4030 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4031 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4032 struct kvm_mmu *context = &vcpu->arch.mmu;
4034 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4036 if (!is_paging(vcpu))
4037 nonpaging_init_context(vcpu, context);
4038 else if (is_long_mode(vcpu))
4039 paging64_init_context(vcpu, context);
4040 else if (is_pae(vcpu))
4041 paging32E_init_context(vcpu, context);
4043 paging32_init_context(vcpu, context);
4045 context->base_role.nxe = is_nx(vcpu);
4046 context->base_role.cr4_pae = !!is_pae(vcpu);
4047 context->base_role.cr0_wp = is_write_protection(vcpu);
4048 context->base_role.smep_andnot_wp
4049 = smep && !is_write_protection(vcpu);
4050 context->base_role.smap_andnot_wp
4051 = smap && !is_write_protection(vcpu);
4052 context->base_role.smm = is_smm(vcpu);
4053 reset_shadow_zero_bits_mask(vcpu, context);
4055 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4057 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4059 struct kvm_mmu *context = &vcpu->arch.mmu;
4061 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4063 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4066 context->page_fault = ept_page_fault;
4067 context->gva_to_gpa = ept_gva_to_gpa;
4068 context->sync_page = ept_sync_page;
4069 context->invlpg = ept_invlpg;
4070 context->update_pte = ept_update_pte;
4071 context->root_level = context->shadow_root_level;
4072 context->root_hpa = INVALID_PAGE;
4073 context->direct_map = false;
4075 update_permission_bitmask(vcpu, context, true);
4076 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4077 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4079 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4081 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4083 struct kvm_mmu *context = &vcpu->arch.mmu;
4085 kvm_init_shadow_mmu(vcpu);
4086 context->set_cr3 = kvm_x86_ops->set_cr3;
4087 context->get_cr3 = get_cr3;
4088 context->get_pdptr = kvm_pdptr_read;
4089 context->inject_page_fault = kvm_inject_page_fault;
4092 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4094 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4096 g_context->get_cr3 = get_cr3;
4097 g_context->get_pdptr = kvm_pdptr_read;
4098 g_context->inject_page_fault = kvm_inject_page_fault;
4101 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4102 * L1's nested page tables (e.g. EPT12). The nested translation
4103 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4104 * L2's page tables as the first level of translation and L1's
4105 * nested page tables as the second level of translation. Basically
4106 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4108 if (!is_paging(vcpu)) {
4109 g_context->nx = false;
4110 g_context->root_level = 0;
4111 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4112 } else if (is_long_mode(vcpu)) {
4113 g_context->nx = is_nx(vcpu);
4114 g_context->root_level = PT64_ROOT_LEVEL;
4115 reset_rsvds_bits_mask(vcpu, g_context);
4116 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4117 } else if (is_pae(vcpu)) {
4118 g_context->nx = is_nx(vcpu);
4119 g_context->root_level = PT32E_ROOT_LEVEL;
4120 reset_rsvds_bits_mask(vcpu, g_context);
4121 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4123 g_context->nx = false;
4124 g_context->root_level = PT32_ROOT_LEVEL;
4125 reset_rsvds_bits_mask(vcpu, g_context);
4126 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4129 update_permission_bitmask(vcpu, g_context, false);
4130 update_last_pte_bitmap(vcpu, g_context);
4133 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4135 if (mmu_is_nested(vcpu))
4136 init_kvm_nested_mmu(vcpu);
4137 else if (tdp_enabled)
4138 init_kvm_tdp_mmu(vcpu);
4140 init_kvm_softmmu(vcpu);
4143 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4145 kvm_mmu_unload(vcpu);
4148 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4150 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4154 r = mmu_topup_memory_caches(vcpu);
4157 r = mmu_alloc_roots(vcpu);
4158 kvm_mmu_sync_roots(vcpu);
4161 /* set_cr3() should ensure TLB has been flushed */
4162 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4166 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4168 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4170 mmu_free_roots(vcpu);
4171 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4173 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4175 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4176 struct kvm_mmu_page *sp, u64 *spte,
4179 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4180 ++vcpu->kvm->stat.mmu_pde_zapped;
4184 ++vcpu->kvm->stat.mmu_pte_updated;
4185 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4188 static bool need_remote_flush(u64 old, u64 new)
4190 if (!is_shadow_present_pte(old))
4192 if (!is_shadow_present_pte(new))
4194 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4196 old ^= shadow_nx_mask;
4197 new ^= shadow_nx_mask;
4198 return (old & ~new & PT64_PERM_MASK) != 0;
4201 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4202 const u8 *new, int *bytes)
4208 * Assume that the pte write on a page table of the same type
4209 * as the current vcpu paging mode since we update the sptes only
4210 * when they have the same mode.
4212 if (is_pae(vcpu) && *bytes == 4) {
4213 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4216 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4219 new = (const u8 *)&gentry;
4224 gentry = *(const u32 *)new;
4227 gentry = *(const u64 *)new;
4238 * If we're seeing too many writes to a page, it may no longer be a page table,
4239 * or we may be forking, in which case it is better to unmap the page.
4241 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4244 * Skip write-flooding detected for the sp whose level is 1, because
4245 * it can become unsync, then the guest page is not write-protected.
4247 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4250 atomic_inc(&sp->write_flooding_count);
4251 return atomic_read(&sp->write_flooding_count) >= 3;
4255 * Misaligned accesses are too much trouble to fix up; also, they usually
4256 * indicate a page is not used as a page table.
4258 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4261 unsigned offset, pte_size, misaligned;
4263 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4264 gpa, bytes, sp->role.word);
4266 offset = offset_in_page(gpa);
4267 pte_size = sp->role.cr4_pae ? 8 : 4;
4270 * Sometimes, the OS only writes the last one bytes to update status
4271 * bits, for example, in linux, andb instruction is used in clear_bit().
4273 if (!(offset & (pte_size - 1)) && bytes == 1)
4276 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4277 misaligned |= bytes < 4;
4282 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4284 unsigned page_offset, quadrant;
4288 page_offset = offset_in_page(gpa);
4289 level = sp->role.level;
4291 if (!sp->role.cr4_pae) {
4292 page_offset <<= 1; /* 32->64 */
4294 * A 32-bit pde maps 4MB while the shadow pdes map
4295 * only 2MB. So we need to double the offset again
4296 * and zap two pdes instead of one.
4298 if (level == PT32_ROOT_LEVEL) {
4299 page_offset &= ~7; /* kill rounding error */
4303 quadrant = page_offset >> PAGE_SHIFT;
4304 page_offset &= ~PAGE_MASK;
4305 if (quadrant != sp->role.quadrant)
4309 spte = &sp->spt[page_offset / sizeof(*spte)];
4313 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4314 const u8 *new, int bytes)
4316 gfn_t gfn = gpa >> PAGE_SHIFT;
4317 struct kvm_mmu_page *sp;
4318 LIST_HEAD(invalid_list);
4319 u64 entry, gentry, *spte;
4321 bool remote_flush, local_flush;
4322 union kvm_mmu_page_role mask = { };
4327 mask.smep_andnot_wp = 1;
4328 mask.smap_andnot_wp = 1;
4332 * If we don't have indirect shadow pages, it means no page is
4333 * write-protected, so we can exit simply.
4335 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4338 remote_flush = local_flush = false;
4340 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4342 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4345 * No need to care whether allocation memory is successful
4346 * or not since pte prefetch is skiped if it does not have
4347 * enough objects in the cache.
4349 mmu_topup_memory_caches(vcpu);
4351 spin_lock(&vcpu->kvm->mmu_lock);
4352 ++vcpu->kvm->stat.mmu_pte_write;
4353 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4355 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4356 if (detect_write_misaligned(sp, gpa, bytes) ||
4357 detect_write_flooding(sp)) {
4358 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4359 ++vcpu->kvm->stat.mmu_flooded;
4363 spte = get_written_sptes(sp, gpa, &npte);
4370 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4372 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4373 & mask.word) && rmap_can_add(vcpu))
4374 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4375 if (need_remote_flush(entry, *spte))
4376 remote_flush = true;
4380 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4381 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4382 spin_unlock(&vcpu->kvm->mmu_lock);
4385 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4390 if (vcpu->arch.mmu.direct_map)
4393 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4395 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4399 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4401 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4403 LIST_HEAD(invalid_list);
4405 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4408 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4409 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4412 ++vcpu->kvm->stat.mmu_recycled;
4414 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4417 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4418 void *insn, int insn_len)
4420 int r, emulation_type = EMULTYPE_RETRY;
4421 enum emulation_result er;
4422 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4424 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4425 r = handle_mmio_page_fault(vcpu, cr2, direct);
4426 if (r == RET_MMIO_PF_EMULATE) {
4430 if (r == RET_MMIO_PF_RETRY)
4436 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4442 if (mmio_info_in_cache(vcpu, cr2, direct))
4445 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4450 case EMULATE_USER_EXIT:
4451 ++vcpu->stat.mmio_exits;
4459 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4461 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4463 vcpu->arch.mmu.invlpg(vcpu, gva);
4464 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4465 ++vcpu->stat.invlpg;
4467 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4469 void kvm_enable_tdp(void)
4473 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4475 void kvm_disable_tdp(void)
4477 tdp_enabled = false;
4479 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4481 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4483 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4484 if (vcpu->arch.mmu.lm_root != NULL)
4485 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4488 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4494 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4495 * Therefore we need to allocate shadow page tables in the first
4496 * 4GB of memory, which happens to fit the DMA32 zone.
4498 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4502 vcpu->arch.mmu.pae_root = page_address(page);
4503 for (i = 0; i < 4; ++i)
4504 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4509 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4511 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4512 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4513 vcpu->arch.mmu.translate_gpa = translate_gpa;
4514 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4516 return alloc_mmu_pages(vcpu);
4519 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4521 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4526 void kvm_mmu_init_vm(struct kvm *kvm)
4528 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4530 node->track_write = kvm_mmu_pte_write;
4531 kvm_page_track_register_notifier(kvm, node);
4534 void kvm_mmu_uninit_vm(struct kvm *kvm)
4536 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4538 kvm_page_track_unregister_notifier(kvm, node);
4541 /* The return value indicates if tlb flush on all vcpus is needed. */
4542 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4544 /* The caller should hold mmu-lock before calling this function. */
4546 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4547 slot_level_handler fn, int start_level, int end_level,
4548 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4550 struct slot_rmap_walk_iterator iterator;
4553 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4554 end_gfn, &iterator) {
4556 flush |= fn(kvm, iterator.rmap);
4558 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4559 if (flush && lock_flush_tlb) {
4560 kvm_flush_remote_tlbs(kvm);
4563 cond_resched_lock(&kvm->mmu_lock);
4567 if (flush && lock_flush_tlb) {
4568 kvm_flush_remote_tlbs(kvm);
4576 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4577 slot_level_handler fn, int start_level, int end_level,
4578 bool lock_flush_tlb)
4580 return slot_handle_level_range(kvm, memslot, fn, start_level,
4581 end_level, memslot->base_gfn,
4582 memslot->base_gfn + memslot->npages - 1,
4587 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4588 slot_level_handler fn, bool lock_flush_tlb)
4590 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4591 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4595 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4596 slot_level_handler fn, bool lock_flush_tlb)
4598 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4599 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4603 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4604 slot_level_handler fn, bool lock_flush_tlb)
4606 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4607 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4610 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4612 struct kvm_memslots *slots;
4613 struct kvm_memory_slot *memslot;
4616 spin_lock(&kvm->mmu_lock);
4617 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4618 slots = __kvm_memslots(kvm, i);
4619 kvm_for_each_memslot(memslot, slots) {
4622 start = max(gfn_start, memslot->base_gfn);
4623 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4627 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4628 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4629 start, end - 1, true);
4633 spin_unlock(&kvm->mmu_lock);
4636 static bool slot_rmap_write_protect(struct kvm *kvm,
4637 struct kvm_rmap_head *rmap_head)
4639 return __rmap_write_protect(kvm, rmap_head, false);
4642 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4643 struct kvm_memory_slot *memslot)
4647 spin_lock(&kvm->mmu_lock);
4648 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4650 spin_unlock(&kvm->mmu_lock);
4653 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4654 * which do tlb flush out of mmu-lock should be serialized by
4655 * kvm->slots_lock otherwise tlb flush would be missed.
4657 lockdep_assert_held(&kvm->slots_lock);
4660 * We can flush all the TLBs out of the mmu lock without TLB
4661 * corruption since we just change the spte from writable to
4662 * readonly so that we only need to care the case of changing
4663 * spte from present to present (changing the spte from present
4664 * to nonpresent will flush all the TLBs immediately), in other
4665 * words, the only case we care is mmu_spte_update() where we
4666 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4667 * instead of PT_WRITABLE_MASK, that means it does not depend
4668 * on PT_WRITABLE_MASK anymore.
4671 kvm_flush_remote_tlbs(kvm);
4674 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4675 struct kvm_rmap_head *rmap_head)
4678 struct rmap_iterator iter;
4679 int need_tlb_flush = 0;
4681 struct kvm_mmu_page *sp;
4684 for_each_rmap_spte(rmap_head, &iter, sptep) {
4685 sp = page_header(__pa(sptep));
4686 pfn = spte_to_pfn(*sptep);
4689 * We cannot do huge page mapping for indirect shadow pages,
4690 * which are found on the last rmap (level = 1) when not using
4691 * tdp; such shadow pages are synced with the page table in
4692 * the guest, and the guest page table is using 4K page size
4693 * mapping if the indirect sp has level = 1.
4695 if (sp->role.direct &&
4696 !kvm_is_reserved_pfn(pfn) &&
4697 PageTransCompound(pfn_to_page(pfn))) {
4698 drop_spte(kvm, sptep);
4704 return need_tlb_flush;
4707 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4708 const struct kvm_memory_slot *memslot)
4710 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4711 spin_lock(&kvm->mmu_lock);
4712 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4713 kvm_mmu_zap_collapsible_spte, true);
4714 spin_unlock(&kvm->mmu_lock);
4717 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4718 struct kvm_memory_slot *memslot)
4722 spin_lock(&kvm->mmu_lock);
4723 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4724 spin_unlock(&kvm->mmu_lock);
4726 lockdep_assert_held(&kvm->slots_lock);
4729 * It's also safe to flush TLBs out of mmu lock here as currently this
4730 * function is only used for dirty logging, in which case flushing TLB
4731 * out of mmu lock also guarantees no dirty pages will be lost in
4735 kvm_flush_remote_tlbs(kvm);
4737 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4739 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4740 struct kvm_memory_slot *memslot)
4744 spin_lock(&kvm->mmu_lock);
4745 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4747 spin_unlock(&kvm->mmu_lock);
4749 /* see kvm_mmu_slot_remove_write_access */
4750 lockdep_assert_held(&kvm->slots_lock);
4753 kvm_flush_remote_tlbs(kvm);
4755 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4757 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4758 struct kvm_memory_slot *memslot)
4762 spin_lock(&kvm->mmu_lock);
4763 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4764 spin_unlock(&kvm->mmu_lock);
4766 lockdep_assert_held(&kvm->slots_lock);
4768 /* see kvm_mmu_slot_leaf_clear_dirty */
4770 kvm_flush_remote_tlbs(kvm);
4772 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4774 #define BATCH_ZAP_PAGES 10
4775 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4777 struct kvm_mmu_page *sp, *node;
4781 list_for_each_entry_safe_reverse(sp, node,
4782 &kvm->arch.active_mmu_pages, link) {
4786 * No obsolete page exists before new created page since
4787 * active_mmu_pages is the FIFO list.
4789 if (!is_obsolete_sp(kvm, sp))
4793 * Since we are reversely walking the list and the invalid
4794 * list will be moved to the head, skip the invalid page
4795 * can help us to avoid the infinity list walking.
4797 if (sp->role.invalid)
4801 * Need not flush tlb since we only zap the sp with invalid
4802 * generation number.
4804 if (batch >= BATCH_ZAP_PAGES &&
4805 cond_resched_lock(&kvm->mmu_lock)) {
4810 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4811 &kvm->arch.zapped_obsolete_pages);
4819 * Should flush tlb before free page tables since lockless-walking
4820 * may use the pages.
4822 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4826 * Fast invalidate all shadow pages and use lock-break technique
4827 * to zap obsolete pages.
4829 * It's required when memslot is being deleted or VM is being
4830 * destroyed, in these cases, we should ensure that KVM MMU does
4831 * not use any resource of the being-deleted slot or all slots
4832 * after calling the function.
4834 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4836 spin_lock(&kvm->mmu_lock);
4837 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4838 kvm->arch.mmu_valid_gen++;
4841 * Notify all vcpus to reload its shadow page table
4842 * and flush TLB. Then all vcpus will switch to new
4843 * shadow page table with the new mmu_valid_gen.
4845 * Note: we should do this under the protection of
4846 * mmu-lock, otherwise, vcpu would purge shadow page
4847 * but miss tlb flush.
4849 kvm_reload_remote_mmus(kvm);
4851 kvm_zap_obsolete_pages(kvm);
4852 spin_unlock(&kvm->mmu_lock);
4855 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4857 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4860 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4863 * The very rare case: if the generation-number is round,
4864 * zap all shadow pages.
4866 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4867 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4868 kvm_mmu_invalidate_zap_all_pages(kvm);
4872 static unsigned long
4873 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4876 int nr_to_scan = sc->nr_to_scan;
4877 unsigned long freed = 0;
4879 spin_lock(&kvm_lock);
4881 list_for_each_entry(kvm, &vm_list, vm_list) {
4883 LIST_HEAD(invalid_list);
4886 * Never scan more than sc->nr_to_scan VM instances.
4887 * Will not hit this condition practically since we do not try
4888 * to shrink more than one VM and it is very unlikely to see
4889 * !n_used_mmu_pages so many times.
4894 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4895 * here. We may skip a VM instance errorneosly, but we do not
4896 * want to shrink a VM that only started to populate its MMU
4899 if (!kvm->arch.n_used_mmu_pages &&
4900 !kvm_has_zapped_obsolete_pages(kvm))
4903 idx = srcu_read_lock(&kvm->srcu);
4904 spin_lock(&kvm->mmu_lock);
4906 if (kvm_has_zapped_obsolete_pages(kvm)) {
4907 kvm_mmu_commit_zap_page(kvm,
4908 &kvm->arch.zapped_obsolete_pages);
4912 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4914 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4917 spin_unlock(&kvm->mmu_lock);
4918 srcu_read_unlock(&kvm->srcu, idx);
4921 * unfair on small ones
4922 * per-vm shrinkers cry out
4923 * sadness comes quickly
4925 list_move_tail(&kvm->vm_list, &vm_list);
4929 spin_unlock(&kvm_lock);
4933 static unsigned long
4934 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4936 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4939 static struct shrinker mmu_shrinker = {
4940 .count_objects = mmu_shrink_count,
4941 .scan_objects = mmu_shrink_scan,
4942 .seeks = DEFAULT_SEEKS * 10,
4945 static void mmu_destroy_caches(void)
4947 if (pte_list_desc_cache)
4948 kmem_cache_destroy(pte_list_desc_cache);
4949 if (mmu_page_header_cache)
4950 kmem_cache_destroy(mmu_page_header_cache);
4953 int kvm_mmu_module_init(void)
4955 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4956 sizeof(struct pte_list_desc),
4958 if (!pte_list_desc_cache)
4961 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4962 sizeof(struct kvm_mmu_page),
4964 if (!mmu_page_header_cache)
4967 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
4970 register_shrinker(&mmu_shrinker);
4975 mmu_destroy_caches();
4980 * Caculate mmu pages needed for kvm.
4982 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4984 unsigned int nr_mmu_pages;
4985 unsigned int nr_pages = 0;
4986 struct kvm_memslots *slots;
4987 struct kvm_memory_slot *memslot;
4990 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4991 slots = __kvm_memslots(kvm, i);
4993 kvm_for_each_memslot(memslot, slots)
4994 nr_pages += memslot->npages;
4997 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4998 nr_mmu_pages = max(nr_mmu_pages,
4999 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5001 return nr_mmu_pages;
5004 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5006 kvm_mmu_unload(vcpu);
5007 free_mmu_pages(vcpu);
5008 mmu_free_memory_caches(vcpu);
5011 void kvm_mmu_module_exit(void)
5013 mmu_destroy_caches();
5014 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5015 unregister_shrinker(&mmu_shrinker);
5016 mmu_audit_disable();