arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_xsaves_supported(void);
 867 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 868 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 869                             struct kvm_segment *var, int seg);
 870 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 871                             struct kvm_segment *var, int seg);
 872 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 873 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 874 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 875 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 876 static int alloc_identity_pagetable(struct kvm *kvm);
 877
 878 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 879 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 880 /*
 881  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 882  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 883  */
 884 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 885 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 886
 887 /*
 888  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 889  * can find which vCPU should be waken up.
 890  */
 891 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 892 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 893
 894 static unsigned long *vmx_io_bitmap_a;
 895 static unsigned long *vmx_io_bitmap_b;
 896 static unsigned long *vmx_msr_bitmap_legacy;
 897 static unsigned long *vmx_msr_bitmap_longmode;
 898 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 899 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 900 static unsigned long *vmx_msr_bitmap_nested;
 901 static unsigned long *vmx_vmread_bitmap;
 902 static unsigned long *vmx_vmwrite_bitmap;
 903
 904 static bool cpu_has_load_ia32_efer;
 905 static bool cpu_has_load_perf_global_ctrl;
 906
 907 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 908 static DEFINE_SPINLOCK(vmx_vpid_lock);
 909
 910 static struct vmcs_config {
 911         int size;
 912         int order;
 913         u32 revision_id;
 914         u32 pin_based_exec_ctrl;
 915         u32 cpu_based_exec_ctrl;
 916         u32 cpu_based_2nd_exec_ctrl;
 917         u32 vmexit_ctrl;
 918         u32 vmentry_ctrl;
 919 } vmcs_config;
 920
 921 static struct vmx_capability {
 922         u32 ept;
 923         u32 vpid;
 924 } vmx_capability;
 925
 926 #define VMX_SEGMENT_FIELD(seg)                                  \
 927         [VCPU_SREG_##seg] = {                                   \
 928                 .selector = GUEST_##seg##_SELECTOR,             \
 929                 .base = GUEST_##seg##_BASE,                     \
 930                 .limit = GUEST_##seg##_LIMIT,                   \
 931                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 932         }
 933
 934 static const struct kvm_vmx_segment_field {
 935         unsigned selector;
 936         unsigned base;
 937         unsigned limit;
 938         unsigned ar_bytes;
 939 } kvm_vmx_segment_fields[] = {
 940         VMX_SEGMENT_FIELD(CS),
 941         VMX_SEGMENT_FIELD(DS),
 942         VMX_SEGMENT_FIELD(ES),
 943         VMX_SEGMENT_FIELD(FS),
 944         VMX_SEGMENT_FIELD(GS),
 945         VMX_SEGMENT_FIELD(SS),
 946         VMX_SEGMENT_FIELD(TR),
 947         VMX_SEGMENT_FIELD(LDTR),
 948 };
 949
 950 static u64 host_efer;
 951
 952 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 953
 954 /*
 955  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 956  * away by decrementing the array size.
 957  */
 958 static const u32 vmx_msr_index[] = {
 959 #ifdef CONFIG_X86_64
 960         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 961 #endif
 962         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 963 };
 964
 965 static inline bool is_exception_n(u32 intr_info, u8 vector)
 966 {
 967         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 968                              INTR_INFO_VALID_MASK)) ==
 969                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 970 }
 971
 972 static inline bool is_debug(u32 intr_info)
 973 {
 974         return is_exception_n(intr_info, DB_VECTOR);
 975 }
 976
 977 static inline bool is_breakpoint(u32 intr_info)
 978 {
 979         return is_exception_n(intr_info, BP_VECTOR);
 980 }
 981
 982 static inline bool is_page_fault(u32 intr_info)
 983 {
 984         return is_exception_n(intr_info, PF_VECTOR);
 985 }
 986
 987 static inline bool is_no_device(u32 intr_info)
 988 {
 989         return is_exception_n(intr_info, NM_VECTOR);
 990 }
 991
 992 static inline bool is_invalid_opcode(u32 intr_info)
 993 {
 994         return is_exception_n(intr_info, UD_VECTOR);
 995 }
 996
 997 static inline bool is_external_interrupt(u32 intr_info)
 998 {
 999         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1000                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1001 }
1002
1003 static inline bool is_machine_check(u32 intr_info)
1004 {
1005         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1006                              INTR_INFO_VALID_MASK)) ==
1007                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1008 }
1009
1010 static inline bool cpu_has_vmx_msr_bitmap(void)
1011 {
1012         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1013 }
1014
1015 static inline bool cpu_has_vmx_tpr_shadow(void)
1016 {
1017         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1018 }
1019
1020 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1021 {
1022         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1023 }
1024
1025 static inline bool cpu_has_secondary_exec_ctrls(void)
1026 {
1027         return vmcs_config.cpu_based_exec_ctrl &
1028                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1029 }
1030
1031 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1032 {
1033         return vmcs_config.cpu_based_2nd_exec_ctrl &
1034                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1035 }
1036
1037 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1038 {
1039         return vmcs_config.cpu_based_2nd_exec_ctrl &
1040                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1041 }
1042
1043 static inline bool cpu_has_vmx_apic_register_virt(void)
1044 {
1045         return vmcs_config.cpu_based_2nd_exec_ctrl &
1046                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1047 }
1048
1049 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1050 {
1051         return vmcs_config.cpu_based_2nd_exec_ctrl &
1052                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1053 }
1054
1055 static inline bool cpu_has_vmx_posted_intr(void)
1056 {
1057         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1058                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1059 }
1060
1061 static inline bool cpu_has_vmx_apicv(void)
1062 {
1063         return cpu_has_vmx_apic_register_virt() &&
1064                 cpu_has_vmx_virtual_intr_delivery() &&
1065                 cpu_has_vmx_posted_intr();
1066 }
1067
1068 static inline bool cpu_has_vmx_flexpriority(void)
1069 {
1070         return cpu_has_vmx_tpr_shadow() &&
1071                 cpu_has_vmx_virtualize_apic_accesses();
1072 }
1073
1074 static inline bool cpu_has_vmx_ept_execute_only(void)
1075 {
1076         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1077 }
1078
1079 static inline bool cpu_has_vmx_ept_2m_page(void)
1080 {
1081         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1082 }
1083
1084 static inline bool cpu_has_vmx_ept_1g_page(void)
1085 {
1086         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1087 }
1088
1089 static inline bool cpu_has_vmx_ept_4levels(void)
1090 {
1091         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1092 }
1093
1094 static inline bool cpu_has_vmx_ept_ad_bits(void)
1095 {
1096         return vmx_capability.ept & VMX_EPT_AD_BIT;
1097 }
1098
1099 static inline bool cpu_has_vmx_invept_context(void)
1100 {
1101         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1102 }
1103
1104 static inline bool cpu_has_vmx_invept_global(void)
1105 {
1106         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1107 }
1108
1109 static inline bool cpu_has_vmx_invvpid_single(void)
1110 {
1111         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1112 }
1113
1114 static inline bool cpu_has_vmx_invvpid_global(void)
1115 {
1116         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1117 }
1118
1119 static inline bool cpu_has_vmx_ept(void)
1120 {
1121         return vmcs_config.cpu_based_2nd_exec_ctrl &
1122                 SECONDARY_EXEC_ENABLE_EPT;
1123 }
1124
1125 static inline bool cpu_has_vmx_unrestricted_guest(void)
1126 {
1127         return vmcs_config.cpu_based_2nd_exec_ctrl &
1128                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1129 }
1130
1131 static inline bool cpu_has_vmx_ple(void)
1132 {
1133         return vmcs_config.cpu_based_2nd_exec_ctrl &
1134                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1135 }
1136
1137 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1138 {
1139         return flexpriority_enabled && lapic_in_kernel(vcpu);
1140 }
1141
1142 static inline bool cpu_has_vmx_vpid(void)
1143 {
1144         return vmcs_config.cpu_based_2nd_exec_ctrl &
1145                 SECONDARY_EXEC_ENABLE_VPID;
1146 }
1147
1148 static inline bool cpu_has_vmx_rdtscp(void)
1149 {
1150         return vmcs_config.cpu_based_2nd_exec_ctrl &
1151                 SECONDARY_EXEC_RDTSCP;
1152 }
1153
1154 static inline bool cpu_has_vmx_invpcid(void)
1155 {
1156         return vmcs_config.cpu_based_2nd_exec_ctrl &
1157                 SECONDARY_EXEC_ENABLE_INVPCID;
1158 }
1159
1160 static inline bool cpu_has_virtual_nmis(void)
1161 {
1162         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1163 }
1164
1165 static inline bool cpu_has_vmx_wbinvd_exit(void)
1166 {
1167         return vmcs_config.cpu_based_2nd_exec_ctrl &
1168                 SECONDARY_EXEC_WBINVD_EXITING;
1169 }
1170
1171 static inline bool cpu_has_vmx_shadow_vmcs(void)
1172 {
1173         u64 vmx_msr;
1174         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1175         /* check if the cpu supports writing r/o exit information fields */
1176         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1177                 return false;
1178
1179         return vmcs_config.cpu_based_2nd_exec_ctrl &
1180                 SECONDARY_EXEC_SHADOW_VMCS;
1181 }
1182
1183 static inline bool cpu_has_vmx_pml(void)
1184 {
1185         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1186 }
1187
1188 static inline bool cpu_has_vmx_tsc_scaling(void)
1189 {
1190         return vmcs_config.cpu_based_2nd_exec_ctrl &
1191                 SECONDARY_EXEC_TSC_SCALING;
1192 }
1193
1194 static inline bool report_flexpriority(void)
1195 {
1196         return flexpriority_enabled;
1197 }
1198
1199 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1200 {
1201         return vmcs12->cpu_based_vm_exec_control & bit;
1202 }
1203
1204 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1205 {
1206         return (vmcs12->cpu_based_vm_exec_control &
1207                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1208                 (vmcs12->secondary_vm_exec_control & bit);
1209 }
1210
1211 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1212 {
1213         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1214 }
1215
1216 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1217 {
1218         return vmcs12->pin_based_vm_exec_control &
1219                 PIN_BASED_VMX_PREEMPTION_TIMER;
1220 }
1221
1222 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1223 {
1224         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1225 }
1226
1227 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1228 {
1229         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1230                 vmx_xsaves_supported();
1231 }
1232
1233 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1234 {
1235         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1236 }
1237
1238 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1239 {
1240         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1241 }
1242
1243 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1244 {
1245         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1246 }
1247
1248 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1249 {
1250         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1251 }
1252
1253 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1254 {
1255         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1256 }
1257
1258 static inline bool is_exception(u32 intr_info)
1259 {
1260         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1261                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1262 }
1263
1264 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1265                               u32 exit_intr_info,
1266                               unsigned long exit_qualification);
1267 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1268                         struct vmcs12 *vmcs12,
1269                         u32 reason, unsigned long qualification);
1270
1271 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1272 {
1273         int i;
1274
1275         for (i = 0; i < vmx->nmsrs; ++i)
1276                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1277                         return i;
1278         return -1;
1279 }
1280
1281 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1282 {
1283     struct {
1284         u64 vpid : 16;
1285         u64 rsvd : 48;
1286         u64 gva;
1287     } operand = { vpid, 0, gva };
1288
1289     asm volatile (__ex(ASM_VMX_INVVPID)
1290                   /* CF==1 or ZF==1 --> rc = -1 */
1291                   "; ja 1f ; ud2 ; 1:"
1292                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1293 }
1294
1295 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1296 {
1297         struct {
1298                 u64 eptp, gpa;
1299         } operand = {eptp, gpa};
1300
1301         asm volatile (__ex(ASM_VMX_INVEPT)
1302                         /* CF==1 or ZF==1 --> rc = -1 */
1303                         "; ja 1f ; ud2 ; 1:\n"
1304                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1305 }
1306
1307 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1308 {
1309         int i;
1310
1311         i = __find_msr_index(vmx, msr);
1312         if (i >= 0)
1313                 return &vmx->guest_msrs[i];
1314         return NULL;
1315 }
1316
1317 static void vmcs_clear(struct vmcs *vmcs)
1318 {
1319         u64 phys_addr = __pa(vmcs);
1320         u8 error;
1321
1322         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1323                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1324                       : "cc", "memory");
1325         if (error)
1326                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1327                        vmcs, phys_addr);
1328 }
1329
1330 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1331 {
1332         vmcs_clear(loaded_vmcs->vmcs);
1333         loaded_vmcs->cpu = -1;
1334         loaded_vmcs->launched = 0;
1335 }
1336
1337 static void vmcs_load(struct vmcs *vmcs)
1338 {
1339         u64 phys_addr = __pa(vmcs);
1340         u8 error;
1341
1342         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1343                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1344                         : "cc", "memory");
1345         if (error)
1346                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1347                        vmcs, phys_addr);
1348 }
1349
1350 #ifdef CONFIG_KEXEC_CORE
1351 /*
1352  * This bitmap is used to indicate whether the vmclear
1353  * operation is enabled on all cpus. All disabled by
1354  * default.
1355  */
1356 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1357
1358 static inline void crash_enable_local_vmclear(int cpu)
1359 {
1360         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1361 }
1362
1363 static inline void crash_disable_local_vmclear(int cpu)
1364 {
1365         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1366 }
1367
1368 static inline int crash_local_vmclear_enabled(int cpu)
1369 {
1370         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1371 }
1372
1373 static void crash_vmclear_local_loaded_vmcss(void)
1374 {
1375         int cpu = raw_smp_processor_id();
1376         struct loaded_vmcs *v;
1377
1378         if (!crash_local_vmclear_enabled(cpu))
1379                 return;
1380
1381         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1382                             loaded_vmcss_on_cpu_link)
1383                 vmcs_clear(v->vmcs);
1384 }
1385 #else
1386 static inline void crash_enable_local_vmclear(int cpu) { }
1387 static inline void crash_disable_local_vmclear(int cpu) { }
1388 #endif /* CONFIG_KEXEC_CORE */
1389
1390 static void __loaded_vmcs_clear(void *arg)
1391 {
1392         struct loaded_vmcs *loaded_vmcs = arg;
1393         int cpu = raw_smp_processor_id();
1394
1395         if (loaded_vmcs->cpu != cpu)
1396                 return; /* vcpu migration can race with cpu offline */
1397         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1398                 per_cpu(current_vmcs, cpu) = NULL;
1399         crash_disable_local_vmclear(cpu);
1400         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1401
1402         /*
1403          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1404          * is before setting loaded_vmcs->vcpu to -1 which is done in
1405          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1406          * then adds the vmcs into percpu list before it is deleted.
1407          */
1408         smp_wmb();
1409
1410         loaded_vmcs_init(loaded_vmcs);
1411         crash_enable_local_vmclear(cpu);
1412 }
1413
1414 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1415 {
1416         int cpu = loaded_vmcs->cpu;
1417
1418         if (cpu != -1)
1419                 smp_call_function_single(cpu,
1420                          __loaded_vmcs_clear, loaded_vmcs, 1);
1421 }
1422
1423 static inline void vpid_sync_vcpu_single(int vpid)
1424 {
1425         if (vpid == 0)
1426                 return;
1427
1428         if (cpu_has_vmx_invvpid_single())
1429                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1430 }
1431
1432 static inline void vpid_sync_vcpu_global(void)
1433 {
1434         if (cpu_has_vmx_invvpid_global())
1435                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1436 }
1437
1438 static inline void vpid_sync_context(int vpid)
1439 {
1440         if (cpu_has_vmx_invvpid_single())
1441                 vpid_sync_vcpu_single(vpid);
1442         else
1443                 vpid_sync_vcpu_global();
1444 }
1445
1446 static inline void ept_sync_global(void)
1447 {
1448         if (cpu_has_vmx_invept_global())
1449                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1450 }
1451
1452 static inline void ept_sync_context(u64 eptp)
1453 {
1454         if (enable_ept) {
1455                 if (cpu_has_vmx_invept_context())
1456                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1457                 else
1458                         ept_sync_global();
1459         }
1460 }
1461
1462 static __always_inline void vmcs_check16(unsigned long field)
1463 {
1464         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1465                          "16-bit accessor invalid for 64-bit field");
1466         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1467                          "16-bit accessor invalid for 64-bit high field");
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1469                          "16-bit accessor invalid for 32-bit high field");
1470         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1471                          "16-bit accessor invalid for natural width field");
1472 }
1473
1474 static __always_inline void vmcs_check32(unsigned long field)
1475 {
1476         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1477                          "32-bit accessor invalid for 16-bit field");
1478         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1479                          "32-bit accessor invalid for natural width field");
1480 }
1481
1482 static __always_inline void vmcs_check64(unsigned long field)
1483 {
1484         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1485                          "64-bit accessor invalid for 16-bit field");
1486         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1487                          "64-bit accessor invalid for 64-bit high field");
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1489                          "64-bit accessor invalid for 32-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1491                          "64-bit accessor invalid for natural width field");
1492 }
1493
1494 static __always_inline void vmcs_checkl(unsigned long field)
1495 {
1496         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1497                          "Natural width accessor invalid for 16-bit field");
1498         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1499                          "Natural width accessor invalid for 64-bit field");
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1501                          "Natural width accessor invalid for 64-bit high field");
1502         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1503                          "Natural width accessor invalid for 32-bit field");
1504 }
1505
1506 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1507 {
1508         unsigned long value;
1509
1510         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1511                       : "=a"(value) : "d"(field) : "cc");
1512         return value;
1513 }
1514
1515 static __always_inline u16 vmcs_read16(unsigned long field)
1516 {
1517         vmcs_check16(field);
1518         return __vmcs_readl(field);
1519 }
1520
1521 static __always_inline u32 vmcs_read32(unsigned long field)
1522 {
1523         vmcs_check32(field);
1524         return __vmcs_readl(field);
1525 }
1526
1527 static __always_inline u64 vmcs_read64(unsigned long field)
1528 {
1529         vmcs_check64(field);
1530 #ifdef CONFIG_X86_64
1531         return __vmcs_readl(field);
1532 #else
1533         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1534 #endif
1535 }
1536
1537 static __always_inline unsigned long vmcs_readl(unsigned long field)
1538 {
1539         vmcs_checkl(field);
1540         return __vmcs_readl(field);
1541 }
1542
1543 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1544 {
1545         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1546                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1547         dump_stack();
1548 }
1549
1550 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1551 {
1552         u8 error;
1553
1554         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1555                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1556         if (unlikely(error))
1557                 vmwrite_error(field, value);
1558 }
1559
1560 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1561 {
1562         vmcs_check16(field);
1563         __vmcs_writel(field, value);
1564 }
1565
1566 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1567 {
1568         vmcs_check32(field);
1569         __vmcs_writel(field, value);
1570 }
1571
1572 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1573 {
1574         vmcs_check64(field);
1575         __vmcs_writel(field, value);
1576 #ifndef CONFIG_X86_64
1577         asm volatile ("");
1578         __vmcs_writel(field+1, value >> 32);
1579 #endif
1580 }
1581
1582 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1583 {
1584         vmcs_checkl(field);
1585         __vmcs_writel(field, value);
1586 }
1587
1588 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1589 {
1590         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1591                          "vmcs_clear_bits does not support 64-bit fields");
1592         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1593 }
1594
1595 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1596 {
1597         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1598                          "vmcs_set_bits does not support 64-bit fields");
1599         __vmcs_writel(field, __vmcs_readl(field) | mask);
1600 }
1601
1602 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1603 {
1604         vmcs_write32(VM_ENTRY_CONTROLS, val);
1605         vmx->vm_entry_controls_shadow = val;
1606 }
1607
1608 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1609 {
1610         if (vmx->vm_entry_controls_shadow != val)
1611                 vm_entry_controls_init(vmx, val);
1612 }
1613
1614 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1615 {
1616         return vmx->vm_entry_controls_shadow;
1617 }
1618
1619
1620 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1621 {
1622         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1623 }
1624
1625 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1626 {
1627         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1628 }
1629
1630 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1631 {
1632         vmcs_write32(VM_EXIT_CONTROLS, val);
1633         vmx->vm_exit_controls_shadow = val;
1634 }
1635
1636 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1637 {
1638         if (vmx->vm_exit_controls_shadow != val)
1639                 vm_exit_controls_init(vmx, val);
1640 }
1641
1642 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1643 {
1644         return vmx->vm_exit_controls_shadow;
1645 }
1646
1647
1648 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1649 {
1650         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1651 }
1652
1653 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1654 {
1655         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1656 }
1657
1658 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1659 {
1660         vmx->segment_cache.bitmask = 0;
1661 }
1662
1663 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1664                                        unsigned field)
1665 {
1666         bool ret;
1667         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1668
1669         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1670                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1671                 vmx->segment_cache.bitmask = 0;
1672         }
1673         ret = vmx->segment_cache.bitmask & mask;
1674         vmx->segment_cache.bitmask |= mask;
1675         return ret;
1676 }
1677
1678 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1679 {
1680         u16 *p = &vmx->segment_cache.seg[seg].selector;
1681
1682         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1683                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1684         return *p;
1685 }
1686
1687 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1688 {
1689         ulong *p = &vmx->segment_cache.seg[seg].base;
1690
1691         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1692                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1693         return *p;
1694 }
1695
1696 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1697 {
1698         u32 *p = &vmx->segment_cache.seg[seg].limit;
1699
1700         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1701                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1702         return *p;
1703 }
1704
1705 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1706 {
1707         u32 *p = &vmx->segment_cache.seg[seg].ar;
1708
1709         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1710                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1711         return *p;
1712 }
1713
1714 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1715 {
1716         u32 eb;
1717
1718         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1719              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1720         if ((vcpu->guest_debug &
1721              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1722             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1723                 eb |= 1u << BP_VECTOR;
1724         if (to_vmx(vcpu)->rmode.vm86_active)
1725                 eb = ~0;
1726         if (enable_ept)
1727                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1728         if (vcpu->fpu_active)
1729                 eb &= ~(1u << NM_VECTOR);
1730
1731         /* When we are running a nested L2 guest and L1 specified for it a
1732          * certain exception bitmap, we must trap the same exceptions and pass
1733          * them to L1. When running L2, we will only handle the exceptions
1734          * specified above if L1 did not want them.
1735          */
1736         if (is_guest_mode(vcpu))
1737                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1738
1739         vmcs_write32(EXCEPTION_BITMAP, eb);
1740 }
1741
1742 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1743                 unsigned long entry, unsigned long exit)
1744 {
1745         vm_entry_controls_clearbit(vmx, entry);
1746         vm_exit_controls_clearbit(vmx, exit);
1747 }
1748
1749 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1750 {
1751         unsigned i;
1752         struct msr_autoload *m = &vmx->msr_autoload;
1753
1754         switch (msr) {
1755         case MSR_EFER:
1756                 if (cpu_has_load_ia32_efer) {
1757                         clear_atomic_switch_msr_special(vmx,
1758                                         VM_ENTRY_LOAD_IA32_EFER,
1759                                         VM_EXIT_LOAD_IA32_EFER);
1760                         return;
1761                 }
1762                 break;
1763         case MSR_CORE_PERF_GLOBAL_CTRL:
1764                 if (cpu_has_load_perf_global_ctrl) {
1765                         clear_atomic_switch_msr_special(vmx,
1766                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1767                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1768                         return;
1769                 }
1770                 break;
1771         }
1772
1773         for (i = 0; i < m->nr; ++i)
1774                 if (m->guest[i].index == msr)
1775                         break;
1776
1777         if (i == m->nr)
1778                 return;
1779         --m->nr;
1780         m->guest[i] = m->guest[m->nr];
1781         m->host[i] = m->host[m->nr];
1782         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1783         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1784 }
1785
1786 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1787                 unsigned long entry, unsigned long exit,
1788                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1789                 u64 guest_val, u64 host_val)
1790 {
1791         vmcs_write64(guest_val_vmcs, guest_val);
1792         vmcs_write64(host_val_vmcs, host_val);
1793         vm_entry_controls_setbit(vmx, entry);
1794         vm_exit_controls_setbit(vmx, exit);
1795 }
1796
1797 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1798                                   u64 guest_val, u64 host_val)
1799 {
1800         unsigned i;
1801         struct msr_autoload *m = &vmx->msr_autoload;
1802
1803         switch (msr) {
1804         case MSR_EFER:
1805                 if (cpu_has_load_ia32_efer) {
1806                         add_atomic_switch_msr_special(vmx,
1807                                         VM_ENTRY_LOAD_IA32_EFER,
1808                                         VM_EXIT_LOAD_IA32_EFER,
1809                                         GUEST_IA32_EFER,
1810                                         HOST_IA32_EFER,
1811                                         guest_val, host_val);
1812                         return;
1813                 }
1814                 break;
1815         case MSR_CORE_PERF_GLOBAL_CTRL:
1816                 if (cpu_has_load_perf_global_ctrl) {
1817                         add_atomic_switch_msr_special(vmx,
1818                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1819                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1820                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1821                                         HOST_IA32_PERF_GLOBAL_CTRL,
1822                                         guest_val, host_val);
1823                         return;
1824                 }
1825                 break;
1826         case MSR_IA32_PEBS_ENABLE:
1827                 /* PEBS needs a quiescent period after being disabled (to write
1828                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1829                  * provide that period, so a CPU could write host's record into
1830                  * guest's memory.
1831                  */
1832                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1833         }
1834
1835         for (i = 0; i < m->nr; ++i)
1836                 if (m->guest[i].index == msr)
1837                         break;
1838
1839         if (i == NR_AUTOLOAD_MSRS) {
1840                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1841                                 "Can't add msr %x\n", msr);
1842                 return;
1843         } else if (i == m->nr) {
1844                 ++m->nr;
1845                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1846                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1847         }
1848
1849         m->guest[i].index = msr;
1850         m->guest[i].value = guest_val;
1851         m->host[i].index = msr;
1852         m->host[i].value = host_val;
1853 }
1854
1855 static void reload_tss(void)
1856 {
1857         /*
1858          * VT restores TR but not its size.  Useless.
1859          */
1860         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1861         struct desc_struct *descs;
1862
1863         descs = (void *)gdt->address;
1864         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1865         load_TR_desc();
1866 }
1867
1868 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1869 {
1870         u64 guest_efer = vmx->vcpu.arch.efer;
1871         u64 ignore_bits = 0;
1872
1873         if (!enable_ept) {
1874                 /*
1875                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1876                  * host CPUID is more efficient than testing guest CPUID
1877                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1878                  */
1879                 if (boot_cpu_has(X86_FEATURE_SMEP))
1880                         guest_efer |= EFER_NX;
1881                 else if (!(guest_efer & EFER_NX))
1882                         ignore_bits |= EFER_NX;
1883         }
1884
1885         /*
1886          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1887          */
1888         ignore_bits |= EFER_SCE;
1889 #ifdef CONFIG_X86_64
1890         ignore_bits |= EFER_LMA | EFER_LME;
1891         /* SCE is meaningful only in long mode on Intel */
1892         if (guest_efer & EFER_LMA)
1893                 ignore_bits &= ~(u64)EFER_SCE;
1894 #endif
1895
1896         clear_atomic_switch_msr(vmx, MSR_EFER);
1897
1898         /*
1899          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1900          * On CPUs that support "load IA32_EFER", always switch EFER
1901          * atomically, since it's faster than switching it manually.
1902          */
1903         if (cpu_has_load_ia32_efer ||
1904             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1905                 if (!(guest_efer & EFER_LMA))
1906                         guest_efer &= ~EFER_LME;
1907                 if (guest_efer != host_efer)
1908                         add_atomic_switch_msr(vmx, MSR_EFER,
1909                                               guest_efer, host_efer);
1910                 return false;
1911         } else {
1912                 guest_efer &= ~ignore_bits;
1913                 guest_efer |= host_efer & ignore_bits;
1914
1915                 vmx->guest_msrs[efer_offset].data = guest_efer;
1916                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1917
1918                 return true;
1919         }
1920 }
1921
1922 static unsigned long segment_base(u16 selector)
1923 {
1924         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1925         struct desc_struct *d;
1926         unsigned long table_base;
1927         unsigned long v;
1928
1929         if (!(selector & ~3))
1930                 return 0;
1931
1932         table_base = gdt->address;
1933
1934         if (selector & 4) {           /* from ldt */
1935                 u16 ldt_selector = kvm_read_ldt();
1936
1937                 if (!(ldt_selector & ~3))
1938                         return 0;
1939
1940                 table_base = segment_base(ldt_selector);
1941         }
1942         d = (struct desc_struct *)(table_base + (selector & ~7));
1943         v = get_desc_base(d);
1944 #ifdef CONFIG_X86_64
1945        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1946                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1947 #endif
1948         return v;
1949 }
1950
1951 static inline unsigned long kvm_read_tr_base(void)
1952 {
1953         u16 tr;
1954         asm("str %0" : "=g"(tr));
1955         return segment_base(tr);
1956 }
1957
1958 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1959 {
1960         struct vcpu_vmx *vmx = to_vmx(vcpu);
1961         int i;
1962
1963         if (vmx->host_state.loaded)
1964                 return;
1965
1966         vmx->host_state.loaded = 1;
1967         /*
1968          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1969          * allow segment selectors with cpl > 0 or ti == 1.
1970          */
1971         vmx->host_state.ldt_sel = kvm_read_ldt();
1972         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1973         savesegment(fs, vmx->host_state.fs_sel);
1974         if (!(vmx->host_state.fs_sel & 7)) {
1975                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1976                 vmx->host_state.fs_reload_needed = 0;
1977         } else {
1978                 vmcs_write16(HOST_FS_SELECTOR, 0);
1979                 vmx->host_state.fs_reload_needed = 1;
1980         }
1981         savesegment(gs, vmx->host_state.gs_sel);
1982         if (!(vmx->host_state.gs_sel & 7))
1983                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1984         else {
1985                 vmcs_write16(HOST_GS_SELECTOR, 0);
1986                 vmx->host_state.gs_ldt_reload_needed = 1;
1987         }
1988
1989 #ifdef CONFIG_X86_64
1990         savesegment(ds, vmx->host_state.ds_sel);
1991         savesegment(es, vmx->host_state.es_sel);
1992 #endif
1993
1994 #ifdef CONFIG_X86_64
1995         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1996         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1997 #else
1998         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1999         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2000 #endif
2001
2002 #ifdef CONFIG_X86_64
2003         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2004         if (is_long_mode(&vmx->vcpu))
2005                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2006 #endif
2007         if (boot_cpu_has(X86_FEATURE_MPX))
2008                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2009         for (i = 0; i < vmx->save_nmsrs; ++i)
2010                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2011                                    vmx->guest_msrs[i].data,
2012                                    vmx->guest_msrs[i].mask);
2013 }
2014
2015 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2016 {
2017         if (!vmx->host_state.loaded)
2018                 return;
2019
2020         ++vmx->vcpu.stat.host_state_reload;
2021         vmx->host_state.loaded = 0;
2022 #ifdef CONFIG_X86_64
2023         if (is_long_mode(&vmx->vcpu))
2024                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2025 #endif
2026         if (vmx->host_state.gs_ldt_reload_needed) {
2027                 kvm_load_ldt(vmx->host_state.ldt_sel);
2028 #ifdef CONFIG_X86_64
2029                 load_gs_index(vmx->host_state.gs_sel);
2030 #else
2031                 loadsegment(gs, vmx->host_state.gs_sel);
2032 #endif
2033         }
2034         if (vmx->host_state.fs_reload_needed)
2035                 loadsegment(fs, vmx->host_state.fs_sel);
2036 #ifdef CONFIG_X86_64
2037         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2038                 loadsegment(ds, vmx->host_state.ds_sel);
2039                 loadsegment(es, vmx->host_state.es_sel);
2040         }
2041 #endif
2042         reload_tss();
2043 #ifdef CONFIG_X86_64
2044         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2045 #endif
2046         if (vmx->host_state.msr_host_bndcfgs)
2047                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2048         /*
2049          * If the FPU is not active (through the host task or
2050          * the guest vcpu), then restore the cr0.TS bit.
2051          */
2052         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2053                 stts();
2054         load_gdt(this_cpu_ptr(&host_gdt));
2055 }
2056
2057 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2058 {
2059         preempt_disable();
2060         __vmx_load_host_state(vmx);
2061         preempt_enable();
2062 }
2063
2064 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2065 {
2066         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2067         struct pi_desc old, new;
2068         unsigned int dest;
2069
2070         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2071                 !irq_remapping_cap(IRQ_POSTING_CAP))
2072                 return;
2073
2074         do {
2075                 old.control = new.control = pi_desc->control;
2076
2077                 /*
2078                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2079                  * are two possible cases:
2080                  * 1. After running 'pre_block', context switch
2081                  *    happened. For this case, 'sn' was set in
2082                  *    vmx_vcpu_put(), so we need to clear it here.
2083                  * 2. After running 'pre_block', we were blocked,
2084                  *    and woken up by some other guy. For this case,
2085                  *    we don't need to do anything, 'pi_post_block'
2086                  *    will do everything for us. However, we cannot
2087                  *    check whether it is case #1 or case #2 here
2088                  *    (maybe, not needed), so we also clear sn here,
2089                  *    I think it is not a big deal.
2090                  */
2091                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2092                         if (vcpu->cpu != cpu) {
2093                                 dest = cpu_physical_id(cpu);
2094
2095                                 if (x2apic_enabled())
2096                                         new.ndst = dest;
2097                                 else
2098                                         new.ndst = (dest << 8) & 0xFF00;
2099                         }
2100
2101                         /* set 'NV' to 'notification vector' */
2102                         new.nv = POSTED_INTR_VECTOR;
2103                 }
2104
2105                 /* Allow posting non-urgent interrupts */
2106                 new.sn = 0;
2107         } while (cmpxchg(&pi_desc->control, old.control,
2108                         new.control) != old.control);
2109 }
2110 /*
2111  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2112  * vcpu mutex is already taken.
2113  */
2114 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2115 {
2116         struct vcpu_vmx *vmx = to_vmx(vcpu);
2117         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2118
2119         if (!vmm_exclusive)
2120                 kvm_cpu_vmxon(phys_addr);
2121         else if (vmx->loaded_vmcs->cpu != cpu)
2122                 loaded_vmcs_clear(vmx->loaded_vmcs);
2123
2124         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2125                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2126                 vmcs_load(vmx->loaded_vmcs->vmcs);
2127         }
2128
2129         if (vmx->loaded_vmcs->cpu != cpu) {
2130                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2131                 unsigned long sysenter_esp;
2132
2133                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2134                 local_irq_disable();
2135                 crash_disable_local_vmclear(cpu);
2136
2137                 /*
2138                  * Read loaded_vmcs->cpu should be before fetching
2139                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2140                  * See the comments in __loaded_vmcs_clear().
2141                  */
2142                 smp_rmb();
2143
2144                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2145                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2146                 crash_enable_local_vmclear(cpu);
2147                 local_irq_enable();
2148
2149                 /*
2150                  * Linux uses per-cpu TSS and GDT, so set these when switching
2151                  * processors.
2152                  */
2153                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2154                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2155
2156                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2157                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2158
2159                 vmx->loaded_vmcs->cpu = cpu;
2160         }
2161
2162         /* Setup TSC multiplier */
2163         if (kvm_has_tsc_control &&
2164             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2165                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2166                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2167         }
2168
2169         vmx_vcpu_pi_load(vcpu, cpu);
2170 }
2171
2172 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2173 {
2174         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2175
2176         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2177                 !irq_remapping_cap(IRQ_POSTING_CAP))
2178                 return;
2179
2180         /* Set SN when the vCPU is preempted */
2181         if (vcpu->preempted)
2182                 pi_set_sn(pi_desc);
2183 }
2184
2185 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2186 {
2187         vmx_vcpu_pi_put(vcpu);
2188
2189         __vmx_load_host_state(to_vmx(vcpu));
2190         if (!vmm_exclusive) {
2191                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2192                 vcpu->cpu = -1;
2193                 kvm_cpu_vmxoff();
2194         }
2195 }
2196
2197 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2198 {
2199         ulong cr0;
2200
2201         if (vcpu->fpu_active)
2202                 return;
2203         vcpu->fpu_active = 1;
2204         cr0 = vmcs_readl(GUEST_CR0);
2205         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2206         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2207         vmcs_writel(GUEST_CR0, cr0);
2208         update_exception_bitmap(vcpu);
2209         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2210         if (is_guest_mode(vcpu))
2211                 vcpu->arch.cr0_guest_owned_bits &=
2212                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2213         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2214 }
2215
2216 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2217
2218 /*
2219  * Return the cr0 value that a nested guest would read. This is a combination
2220  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2221  * its hypervisor (cr0_read_shadow).
2222  */
2223 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2224 {
2225         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2226                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2227 }
2228 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2229 {
2230         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2231                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2232 }
2233
2234 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2235 {
2236         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2237          * set this *before* calling this function.
2238          */
2239         vmx_decache_cr0_guest_bits(vcpu);
2240         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2241         update_exception_bitmap(vcpu);
2242         vcpu->arch.cr0_guest_owned_bits = 0;
2243         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2244         if (is_guest_mode(vcpu)) {
2245                 /*
2246                  * L1's specified read shadow might not contain the TS bit,
2247                  * so now that we turned on shadowing of this bit, we need to
2248                  * set this bit of the shadow. Like in nested_vmx_run we need
2249                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2250                  * up-to-date here because we just decached cr0.TS (and we'll
2251                  * only update vmcs12->guest_cr0 on nested exit).
2252                  */
2253                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2254                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2255                         (vcpu->arch.cr0 & X86_CR0_TS);
2256                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2257         } else
2258                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2259 }
2260
2261 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2262 {
2263         unsigned long rflags, save_rflags;
2264
2265         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2266                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2267                 rflags = vmcs_readl(GUEST_RFLAGS);
2268                 if (to_vmx(vcpu)->rmode.vm86_active) {
2269                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2270                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2271                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2272                 }
2273                 to_vmx(vcpu)->rflags = rflags;
2274         }
2275         return to_vmx(vcpu)->rflags;
2276 }
2277
2278 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2279 {
2280         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2281         to_vmx(vcpu)->rflags = rflags;
2282         if (to_vmx(vcpu)->rmode.vm86_active) {
2283                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2284                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2285         }
2286         vmcs_writel(GUEST_RFLAGS, rflags);
2287 }
2288
2289 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2290 {
2291         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2292         int ret = 0;
2293
2294         if (interruptibility & GUEST_INTR_STATE_STI)
2295                 ret |= KVM_X86_SHADOW_INT_STI;
2296         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2297                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2298
2299         return ret;
2300 }
2301
2302 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2303 {
2304         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2305         u32 interruptibility = interruptibility_old;
2306
2307         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2308
2309         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2310                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2311         else if (mask & KVM_X86_SHADOW_INT_STI)
2312                 interruptibility |= GUEST_INTR_STATE_STI;
2313
2314         if ((interruptibility != interruptibility_old))
2315                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2316 }
2317
2318 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2319 {
2320         unsigned long rip;
2321
2322         rip = kvm_rip_read(vcpu);
2323         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2324         kvm_rip_write(vcpu, rip);
2325
2326         /* skipping an emulated instruction also counts */
2327         vmx_set_interrupt_shadow(vcpu, 0);
2328 }
2329
2330 /*
2331  * KVM wants to inject page-faults which it got to the guest. This function
2332  * checks whether in a nested guest, we need to inject them to L1 or L2.
2333  */
2334 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2335 {
2336         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2337
2338         if (!(vmcs12->exception_bitmap & (1u << nr)))
2339                 return 0;
2340
2341         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2342                           vmcs_read32(VM_EXIT_INTR_INFO),
2343                           vmcs_readl(EXIT_QUALIFICATION));
2344         return 1;
2345 }
2346
2347 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2348                                 bool has_error_code, u32 error_code,
2349                                 bool reinject)
2350 {
2351         struct vcpu_vmx *vmx = to_vmx(vcpu);
2352         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2353
2354         if (!reinject && is_guest_mode(vcpu) &&
2355             nested_vmx_check_exception(vcpu, nr))
2356                 return;
2357
2358         if (has_error_code) {
2359                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2360                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2361         }
2362
2363         if (vmx->rmode.vm86_active) {
2364                 int inc_eip = 0;
2365                 if (kvm_exception_is_soft(nr))
2366                         inc_eip = vcpu->arch.event_exit_inst_len;
2367                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2368                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2369                 return;
2370         }
2371
2372         if (kvm_exception_is_soft(nr)) {
2373                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2374                              vmx->vcpu.arch.event_exit_inst_len);
2375                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2376         } else
2377                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2378
2379         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2380 }
2381
2382 static bool vmx_rdtscp_supported(void)
2383 {
2384         return cpu_has_vmx_rdtscp();
2385 }
2386
2387 static bool vmx_invpcid_supported(void)
2388 {
2389         return cpu_has_vmx_invpcid() && enable_ept;
2390 }
2391
2392 /*
2393  * Swap MSR entry in host/guest MSR entry array.
2394  */
2395 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2396 {
2397         struct shared_msr_entry tmp;
2398
2399         tmp = vmx->guest_msrs[to];
2400         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2401         vmx->guest_msrs[from] = tmp;
2402 }
2403
2404 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2405 {
2406         unsigned long *msr_bitmap;
2407
2408         if (is_guest_mode(vcpu))
2409                 msr_bitmap = vmx_msr_bitmap_nested;
2410         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2411                 if (is_long_mode(vcpu))
2412                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2413                 else
2414                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2415         } else {
2416                 if (is_long_mode(vcpu))
2417                         msr_bitmap = vmx_msr_bitmap_longmode;
2418                 else
2419                         msr_bitmap = vmx_msr_bitmap_legacy;
2420         }
2421
2422         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2423 }
2424
2425 /*
2426  * Set up the vmcs to automatically save and restore system
2427  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2428  * mode, as fiddling with msrs is very expensive.
2429  */
2430 static void setup_msrs(struct vcpu_vmx *vmx)
2431 {
2432         int save_nmsrs, index;
2433
2434         save_nmsrs = 0;
2435 #ifdef CONFIG_X86_64
2436         if (is_long_mode(&vmx->vcpu)) {
2437                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2438                 if (index >= 0)
2439                         move_msr_up(vmx, index, save_nmsrs++);
2440                 index = __find_msr_index(vmx, MSR_LSTAR);
2441                 if (index >= 0)
2442                         move_msr_up(vmx, index, save_nmsrs++);
2443                 index = __find_msr_index(vmx, MSR_CSTAR);
2444                 if (index >= 0)
2445                         move_msr_up(vmx, index, save_nmsrs++);
2446                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2447                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2448                         move_msr_up(vmx, index, save_nmsrs++);
2449                 /*
2450                  * MSR_STAR is only needed on long mode guests, and only
2451                  * if efer.sce is enabled.
2452                  */
2453                 index = __find_msr_index(vmx, MSR_STAR);
2454                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2455                         move_msr_up(vmx, index, save_nmsrs++);
2456         }
2457 #endif
2458         index = __find_msr_index(vmx, MSR_EFER);
2459         if (index >= 0 && update_transition_efer(vmx, index))
2460                 move_msr_up(vmx, index, save_nmsrs++);
2461
2462         vmx->save_nmsrs = save_nmsrs;
2463
2464         if (cpu_has_vmx_msr_bitmap())
2465                 vmx_set_msr_bitmap(&vmx->vcpu);
2466 }
2467
2468 /*
2469  * reads and returns guest's timestamp counter "register"
2470  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2471  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2472  */
2473 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2474 {
2475         u64 host_tsc, tsc_offset;
2476
2477         host_tsc = rdtsc();
2478         tsc_offset = vmcs_read64(TSC_OFFSET);
2479         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2480 }
2481
2482 /*
2483  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2484  * counter, even if a nested guest (L2) is currently running.
2485  */
2486 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2487 {
2488         u64 tsc_offset;
2489
2490         tsc_offset = is_guest_mode(vcpu) ?
2491                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2492                 vmcs_read64(TSC_OFFSET);
2493         return host_tsc + tsc_offset;
2494 }
2495
2496 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2497 {
2498         return vmcs_read64(TSC_OFFSET);
2499 }
2500
2501 /*
2502  * writes 'offset' into guest's timestamp counter offset register
2503  */
2504 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2505 {
2506         if (is_guest_mode(vcpu)) {
2507                 /*
2508                  * We're here if L1 chose not to trap WRMSR to TSC. According
2509                  * to the spec, this should set L1's TSC; The offset that L1
2510                  * set for L2 remains unchanged, and still needs to be added
2511                  * to the newly set TSC to get L2's TSC.
2512                  */
2513                 struct vmcs12 *vmcs12;
2514                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2515                 /* recalculate vmcs02.TSC_OFFSET: */
2516                 vmcs12 = get_vmcs12(vcpu);
2517                 vmcs_write64(TSC_OFFSET, offset +
2518                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2519                          vmcs12->tsc_offset : 0));
2520         } else {
2521                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2522                                            vmcs_read64(TSC_OFFSET), offset);
2523                 vmcs_write64(TSC_OFFSET, offset);
2524         }
2525 }
2526
2527 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2528 {
2529         u64 offset = vmcs_read64(TSC_OFFSET);
2530
2531         vmcs_write64(TSC_OFFSET, offset + adjustment);
2532         if (is_guest_mode(vcpu)) {
2533                 /* Even when running L2, the adjustment needs to apply to L1 */
2534                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2535         } else
2536                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2537                                            offset + adjustment);
2538 }
2539
2540 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2541 {
2542         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2543         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2544 }
2545
2546 /*
2547  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2548  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2549  * all guests if the "nested" module option is off, and can also be disabled
2550  * for a single guest by disabling its VMX cpuid bit.
2551  */
2552 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2553 {
2554         return nested && guest_cpuid_has_vmx(vcpu);
2555 }
2556
2557 /*
2558  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2559  * returned for the various VMX controls MSRs when nested VMX is enabled.
2560  * The same values should also be used to verify that vmcs12 control fields are
2561  * valid during nested entry from L1 to L2.
2562  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2563  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2564  * bit in the high half is on if the corresponding bit in the control field
2565  * may be on. See also vmx_control_verify().
2566  */
2567 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2568 {
2569         /*
2570          * Note that as a general rule, the high half of the MSRs (bits in
2571          * the control fields which may be 1) should be initialized by the
2572          * intersection of the underlying hardware's MSR (i.e., features which
2573          * can be supported) and the list of features we want to expose -
2574          * because they are known to be properly supported in our code.
2575          * Also, usually, the low half of the MSRs (bits which must be 1) can
2576          * be set to 0, meaning that L1 may turn off any of these bits. The
2577          * reason is that if one of these bits is necessary, it will appear
2578          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2579          * fields of vmcs01 and vmcs02, will turn these bits off - and
2580          * nested_vmx_exit_handled() will not pass related exits to L1.
2581          * These rules have exceptions below.
2582          */
2583
2584         /* pin-based controls */
2585         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2586                 vmx->nested.nested_vmx_pinbased_ctls_low,
2587                 vmx->nested.nested_vmx_pinbased_ctls_high);
2588         vmx->nested.nested_vmx_pinbased_ctls_low |=
2589                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2590         vmx->nested.nested_vmx_pinbased_ctls_high &=
2591                 PIN_BASED_EXT_INTR_MASK |
2592                 PIN_BASED_NMI_EXITING |
2593                 PIN_BASED_VIRTUAL_NMIS;
2594         vmx->nested.nested_vmx_pinbased_ctls_high |=
2595                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2596                 PIN_BASED_VMX_PREEMPTION_TIMER;
2597         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2598                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2599                         PIN_BASED_POSTED_INTR;
2600
2601         /* exit controls */
2602         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2603                 vmx->nested.nested_vmx_exit_ctls_low,
2604                 vmx->nested.nested_vmx_exit_ctls_high);
2605         vmx->nested.nested_vmx_exit_ctls_low =
2606                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2607
2608         vmx->nested.nested_vmx_exit_ctls_high &=
2609 #ifdef CONFIG_X86_64
2610                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2611 #endif
2612                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2613         vmx->nested.nested_vmx_exit_ctls_high |=
2614                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2615                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2616                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2617
2618         if (kvm_mpx_supported())
2619                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2620
2621         /* We support free control of debug control saving. */
2622         vmx->nested.nested_vmx_true_exit_ctls_low =
2623                 vmx->nested.nested_vmx_exit_ctls_low &
2624                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2625
2626         /* entry controls */
2627         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2628                 vmx->nested.nested_vmx_entry_ctls_low,
2629                 vmx->nested.nested_vmx_entry_ctls_high);
2630         vmx->nested.nested_vmx_entry_ctls_low =
2631                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2632         vmx->nested.nested_vmx_entry_ctls_high &=
2633 #ifdef CONFIG_X86_64
2634                 VM_ENTRY_IA32E_MODE |
2635 #endif
2636                 VM_ENTRY_LOAD_IA32_PAT;
2637         vmx->nested.nested_vmx_entry_ctls_high |=
2638                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2639         if (kvm_mpx_supported())
2640                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2641
2642         /* We support free control of debug control loading. */
2643         vmx->nested.nested_vmx_true_entry_ctls_low =
2644                 vmx->nested.nested_vmx_entry_ctls_low &
2645                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2646
2647         /* cpu-based controls */
2648         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2649                 vmx->nested.nested_vmx_procbased_ctls_low,
2650                 vmx->nested.nested_vmx_procbased_ctls_high);
2651         vmx->nested.nested_vmx_procbased_ctls_low =
2652                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2653         vmx->nested.nested_vmx_procbased_ctls_high &=
2654                 CPU_BASED_VIRTUAL_INTR_PENDING |
2655                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2656                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2657                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2658                 CPU_BASED_CR3_STORE_EXITING |
2659 #ifdef CONFIG_X86_64
2660                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2661 #endif
2662                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2663                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2664                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2665                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2666                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2667         /*
2668          * We can allow some features even when not supported by the
2669          * hardware. For example, L1 can specify an MSR bitmap - and we
2670          * can use it to avoid exits to L1 - even when L0 runs L2
2671          * without MSR bitmaps.
2672          */
2673         vmx->nested.nested_vmx_procbased_ctls_high |=
2674                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2675                 CPU_BASED_USE_MSR_BITMAPS;
2676
2677         /* We support free control of CR3 access interception. */
2678         vmx->nested.nested_vmx_true_procbased_ctls_low =
2679                 vmx->nested.nested_vmx_procbased_ctls_low &
2680                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2681
2682         /* secondary cpu-based controls */
2683         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2684                 vmx->nested.nested_vmx_secondary_ctls_low,
2685                 vmx->nested.nested_vmx_secondary_ctls_high);
2686         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2687         vmx->nested.nested_vmx_secondary_ctls_high &=
2688                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2689                 SECONDARY_EXEC_RDTSCP |
2690                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2691                 SECONDARY_EXEC_ENABLE_VPID |
2692                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2693                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2694                 SECONDARY_EXEC_WBINVD_EXITING |
2695                 SECONDARY_EXEC_XSAVES |
2696                 SECONDARY_EXEC_PCOMMIT;
2697
2698         if (enable_ept) {
2699                 /* nested EPT: emulate EPT also to L1 */
2700                 vmx->nested.nested_vmx_secondary_ctls_high |=
2701                         SECONDARY_EXEC_ENABLE_EPT;
2702                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2703                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2704                          VMX_EPT_INVEPT_BIT;
2705                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2706                 /*
2707                  * For nested guests, we don't do anything specific
2708                  * for single context invalidation. Hence, only advertise
2709                  * support for global context invalidation.
2710                  */
2711                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2712         } else
2713                 vmx->nested.nested_vmx_ept_caps = 0;
2714
2715         if (enable_vpid)
2716                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2717                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2718         else
2719                 vmx->nested.nested_vmx_vpid_caps = 0;
2720
2721         if (enable_unrestricted_guest)
2722                 vmx->nested.nested_vmx_secondary_ctls_high |=
2723                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2724
2725         /* miscellaneous data */
2726         rdmsr(MSR_IA32_VMX_MISC,
2727                 vmx->nested.nested_vmx_misc_low,
2728                 vmx->nested.nested_vmx_misc_high);
2729         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2730         vmx->nested.nested_vmx_misc_low |=
2731                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2732                 VMX_MISC_ACTIVITY_HLT;
2733         vmx->nested.nested_vmx_misc_high = 0;
2734 }
2735
2736 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2737 {
2738         /*
2739          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2740          */
2741         return ((control & high) | low) == control;
2742 }
2743
2744 static inline u64 vmx_control_msr(u32 low, u32 high)
2745 {
2746         return low | ((u64)high << 32);
2747 }
2748
2749 /* Returns 0 on success, non-0 otherwise. */
2750 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2751 {
2752         struct vcpu_vmx *vmx = to_vmx(vcpu);
2753
2754         switch (msr_index) {
2755         case MSR_IA32_VMX_BASIC:
2756                 /*
2757                  * This MSR reports some information about VMX support. We
2758                  * should return information about the VMX we emulate for the
2759                  * guest, and the VMCS structure we give it - not about the
2760                  * VMX support of the underlying hardware.
2761                  */
2762                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2763                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2764                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2765                 break;
2766         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2767         case MSR_IA32_VMX_PINBASED_CTLS:
2768                 *pdata = vmx_control_msr(
2769                         vmx->nested.nested_vmx_pinbased_ctls_low,
2770                         vmx->nested.nested_vmx_pinbased_ctls_high);
2771                 break;
2772         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2773                 *pdata = vmx_control_msr(
2774                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2775                         vmx->nested.nested_vmx_procbased_ctls_high);
2776                 break;
2777         case MSR_IA32_VMX_PROCBASED_CTLS:
2778                 *pdata = vmx_control_msr(
2779                         vmx->nested.nested_vmx_procbased_ctls_low,
2780                         vmx->nested.nested_vmx_procbased_ctls_high);
2781                 break;
2782         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2783                 *pdata = vmx_control_msr(
2784                         vmx->nested.nested_vmx_true_exit_ctls_low,
2785                         vmx->nested.nested_vmx_exit_ctls_high);
2786                 break;
2787         case MSR_IA32_VMX_EXIT_CTLS:
2788                 *pdata = vmx_control_msr(
2789                         vmx->nested.nested_vmx_exit_ctls_low,
2790                         vmx->nested.nested_vmx_exit_ctls_high);
2791                 break;
2792         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2793                 *pdata = vmx_control_msr(
2794                         vmx->nested.nested_vmx_true_entry_ctls_low,
2795                         vmx->nested.nested_vmx_entry_ctls_high);
2796                 break;
2797         case MSR_IA32_VMX_ENTRY_CTLS:
2798                 *pdata = vmx_control_msr(
2799                         vmx->nested.nested_vmx_entry_ctls_low,
2800                         vmx->nested.nested_vmx_entry_ctls_high);
2801                 break;
2802         case MSR_IA32_VMX_MISC:
2803                 *pdata = vmx_control_msr(
2804                         vmx->nested.nested_vmx_misc_low,
2805                         vmx->nested.nested_vmx_misc_high);
2806                 break;
2807         /*
2808          * These MSRs specify bits which the guest must keep fixed (on or off)
2809          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2810          * We picked the standard core2 setting.
2811          */
2812 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2813 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2814         case MSR_IA32_VMX_CR0_FIXED0:
2815                 *pdata = VMXON_CR0_ALWAYSON;
2816                 break;
2817         case MSR_IA32_VMX_CR0_FIXED1:
2818                 *pdata = -1ULL;
2819                 break;
2820         case MSR_IA32_VMX_CR4_FIXED0:
2821                 *pdata = VMXON_CR4_ALWAYSON;
2822                 break;
2823         case MSR_IA32_VMX_CR4_FIXED1:
2824                 *pdata = -1ULL;
2825                 break;
2826         case MSR_IA32_VMX_VMCS_ENUM:
2827                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2828                 break;
2829         case MSR_IA32_VMX_PROCBASED_CTLS2:
2830                 *pdata = vmx_control_msr(
2831                         vmx->nested.nested_vmx_secondary_ctls_low,
2832                         vmx->nested.nested_vmx_secondary_ctls_high);
2833                 break;
2834         case MSR_IA32_VMX_EPT_VPID_CAP:
2835                 /* Currently, no nested vpid support */
2836                 *pdata = vmx->nested.nested_vmx_ept_caps |
2837                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2838                 break;
2839         default:
2840                 return 1;
2841         }
2842
2843         return 0;
2844 }
2845
2846 /*
2847  * Reads an msr value (of 'msr_index') into 'pdata'.
2848  * Returns 0 on success, non-0 otherwise.
2849  * Assumes vcpu_load() was already called.
2850  */
2851 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2852 {
2853         struct shared_msr_entry *msr;
2854
2855         switch (msr_info->index) {
2856 #ifdef CONFIG_X86_64
2857         case MSR_FS_BASE:
2858                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2859                 break;
2860         case MSR_GS_BASE:
2861                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2862                 break;
2863         case MSR_KERNEL_GS_BASE:
2864                 vmx_load_host_state(to_vmx(vcpu));
2865                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2866                 break;
2867 #endif
2868         case MSR_EFER:
2869                 return kvm_get_msr_common(vcpu, msr_info);
2870         case MSR_IA32_TSC:
2871                 msr_info->data = guest_read_tsc(vcpu);
2872                 break;
2873         case MSR_IA32_SYSENTER_CS:
2874                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2875                 break;
2876         case MSR_IA32_SYSENTER_EIP:
2877                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2878                 break;
2879         case MSR_IA32_SYSENTER_ESP:
2880                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2881                 break;
2882         case MSR_IA32_BNDCFGS:
2883                 if (!kvm_mpx_supported())
2884                         return 1;
2885                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2886                 break;
2887         case MSR_IA32_FEATURE_CONTROL:
2888                 if (!nested_vmx_allowed(vcpu))
2889                         return 1;
2890                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2891                 break;
2892         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2893                 if (!nested_vmx_allowed(vcpu))
2894                         return 1;
2895                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2896         case MSR_IA32_XSS:
2897                 if (!vmx_xsaves_supported())
2898                         return 1;
2899                 msr_info->data = vcpu->arch.ia32_xss;
2900                 break;
2901         case MSR_TSC_AUX:
2902                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2903                         return 1;
2904                 /* Otherwise falls through */
2905         default:
2906                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2907                 if (msr) {
2908                         msr_info->data = msr->data;
2909                         break;
2910                 }
2911                 return kvm_get_msr_common(vcpu, msr_info);
2912         }
2913
2914         return 0;
2915 }
2916
2917 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2918
2919 /*
2920  * Writes msr value into into the appropriate "register".
2921  * Returns 0 on success, non-0 otherwise.
2922  * Assumes vcpu_load() was already called.
2923  */
2924 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2925 {
2926         struct vcpu_vmx *vmx = to_vmx(vcpu);
2927         struct shared_msr_entry *msr;
2928         int ret = 0;
2929         u32 msr_index = msr_info->index;
2930         u64 data = msr_info->data;
2931
2932         switch (msr_index) {
2933         case MSR_EFER:
2934                 ret = kvm_set_msr_common(vcpu, msr_info);
2935                 break;
2936 #ifdef CONFIG_X86_64
2937         case MSR_FS_BASE:
2938                 vmx_segment_cache_clear(vmx);
2939                 vmcs_writel(GUEST_FS_BASE, data);
2940                 break;
2941         case MSR_GS_BASE:
2942                 vmx_segment_cache_clear(vmx);
2943                 vmcs_writel(GUEST_GS_BASE, data);
2944                 break;
2945         case MSR_KERNEL_GS_BASE:
2946                 vmx_load_host_state(vmx);
2947                 vmx->msr_guest_kernel_gs_base = data;
2948                 break;
2949 #endif
2950         case MSR_IA32_SYSENTER_CS:
2951                 vmcs_write32(GUEST_SYSENTER_CS, data);
2952                 break;
2953         case MSR_IA32_SYSENTER_EIP:
2954                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2955                 break;
2956         case MSR_IA32_SYSENTER_ESP:
2957                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2958                 break;
2959         case MSR_IA32_BNDCFGS:
2960                 if (!kvm_mpx_supported())
2961                         return 1;
2962                 vmcs_write64(GUEST_BNDCFGS, data);
2963                 break;
2964         case MSR_IA32_TSC:
2965                 kvm_write_tsc(vcpu, msr_info);
2966                 break;
2967         case MSR_IA32_CR_PAT:
2968                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2969                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2970                                 return 1;
2971                         vmcs_write64(GUEST_IA32_PAT, data);
2972                         vcpu->arch.pat = data;
2973                         break;
2974                 }
2975                 ret = kvm_set_msr_common(vcpu, msr_info);
2976                 break;
2977         case MSR_IA32_TSC_ADJUST:
2978                 ret = kvm_set_msr_common(vcpu, msr_info);
2979                 break;
2980         case MSR_IA32_FEATURE_CONTROL:
2981                 if (!nested_vmx_allowed(vcpu) ||
2982                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2983                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2984                         return 1;
2985                 vmx->nested.msr_ia32_feature_control = data;
2986                 if (msr_info->host_initiated && data == 0)
2987                         vmx_leave_nested(vcpu);
2988                 break;
2989         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2990                 return 1; /* they are read-only */
2991         case MSR_IA32_XSS:
2992                 if (!vmx_xsaves_supported())
2993                         return 1;
2994                 /*
2995                  * The only supported bit as of Skylake is bit 8, but
2996                  * it is not supported on KVM.
2997                  */
2998                 if (data != 0)
2999                         return 1;
3000                 vcpu->arch.ia32_xss = data;
3001                 if (vcpu->arch.ia32_xss != host_xss)
3002                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3003                                 vcpu->arch.ia32_xss, host_xss);
3004                 else
3005                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3006                 break;
3007         case MSR_TSC_AUX:
3008                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3009                         return 1;
3010                 /* Check reserved bit, higher 32 bits should be zero */
3011                 if ((data >> 32) != 0)
3012                         return 1;
3013                 /* Otherwise falls through */
3014         default:
3015                 msr = find_msr_entry(vmx, msr_index);
3016                 if (msr) {
3017                         u64 old_msr_data = msr->data;
3018                         msr->data = data;
3019                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3020                                 preempt_disable();
3021                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3022                                                          msr->mask);
3023                                 preempt_enable();
3024                                 if (ret)
3025                                         msr->data = old_msr_data;
3026                         }
3027                         break;
3028                 }
3029                 ret = kvm_set_msr_common(vcpu, msr_info);
3030         }
3031
3032         return ret;
3033 }
3034
3035 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3036 {
3037         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3038         switch (reg) {
3039         case VCPU_REGS_RSP:
3040                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3041                 break;
3042         case VCPU_REGS_RIP:
3043                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3044                 break;
3045         case VCPU_EXREG_PDPTR:
3046                 if (enable_ept)
3047                         ept_save_pdptrs(vcpu);
3048                 break;
3049         default:
3050                 break;
3051         }
3052 }
3053
3054 static __init int cpu_has_kvm_support(void)
3055 {
3056         return cpu_has_vmx();
3057 }
3058
3059 static __init int vmx_disabled_by_bios(void)
3060 {
3061         u64 msr;
3062
3063         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3064         if (msr & FEATURE_CONTROL_LOCKED) {
3065                 /* launched w/ TXT and VMX disabled */
3066                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3067                         && tboot_enabled())
3068                         return 1;
3069                 /* launched w/o TXT and VMX only enabled w/ TXT */
3070                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3071                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3072                         && !tboot_enabled()) {
3073                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3074                                 "activate TXT before enabling KVM\n");
3075                         return 1;
3076                 }
3077                 /* launched w/o TXT and VMX disabled */
3078                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3079                         && !tboot_enabled())
3080                         return 1;
3081         }
3082
3083         return 0;
3084 }
3085
3086 static void kvm_cpu_vmxon(u64 addr)
3087 {
3088         asm volatile (ASM_VMX_VMXON_RAX
3089                         : : "a"(&addr), "m"(addr)
3090                         : "memory", "cc");
3091 }
3092
3093 static int hardware_enable(void)
3094 {
3095         int cpu = raw_smp_processor_id();
3096         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3097         u64 old, test_bits;
3098
3099         if (cr4_read_shadow() & X86_CR4_VMXE)
3100                 return -EBUSY;
3101
3102         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3103         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3104         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3105
3106         /*
3107          * Now we can enable the vmclear operation in kdump
3108          * since the loaded_vmcss_on_cpu list on this cpu
3109          * has been initialized.
3110          *
3111          * Though the cpu is not in VMX operation now, there
3112          * is no problem to enable the vmclear operation
3113          * for the loaded_vmcss_on_cpu list is empty!
3114          */
3115         crash_enable_local_vmclear(cpu);
3116
3117         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3118
3119         test_bits = FEATURE_CONTROL_LOCKED;
3120         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3121         if (tboot_enabled())
3122                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3123
3124         if ((old & test_bits) != test_bits) {
3125                 /* enable and lock */
3126                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3127         }
3128         cr4_set_bits(X86_CR4_VMXE);
3129
3130         if (vmm_exclusive) {
3131                 kvm_cpu_vmxon(phys_addr);
3132                 ept_sync_global();
3133         }
3134
3135         native_store_gdt(this_cpu_ptr(&host_gdt));
3136
3137         return 0;
3138 }
3139
3140 static void vmclear_local_loaded_vmcss(void)
3141 {
3142         int cpu = raw_smp_processor_id();
3143         struct loaded_vmcs *v, *n;
3144
3145         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3146                                  loaded_vmcss_on_cpu_link)
3147                 __loaded_vmcs_clear(v);
3148 }
3149
3150
3151 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3152  * tricks.
3153  */
3154 static void kvm_cpu_vmxoff(void)
3155 {
3156         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3157 }
3158
3159 static void hardware_disable(void)
3160 {
3161         if (vmm_exclusive) {
3162                 vmclear_local_loaded_vmcss();
3163                 kvm_cpu_vmxoff();
3164         }
3165         cr4_clear_bits(X86_CR4_VMXE);
3166 }
3167
3168 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3169                                       u32 msr, u32 *result)
3170 {
3171         u32 vmx_msr_low, vmx_msr_high;
3172         u32 ctl = ctl_min | ctl_opt;
3173
3174         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3175
3176         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3177         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3178
3179         /* Ensure minimum (required) set of control bits are supported. */
3180         if (ctl_min & ~ctl)
3181                 return -EIO;
3182
3183         *result = ctl;
3184         return 0;
3185 }
3186
3187 static __init bool allow_1_setting(u32 msr, u32 ctl)
3188 {
3189         u32 vmx_msr_low, vmx_msr_high;
3190
3191         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3192         return vmx_msr_high & ctl;
3193 }
3194
3195 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3196 {
3197         u32 vmx_msr_low, vmx_msr_high;
3198         u32 min, opt, min2, opt2;
3199         u32 _pin_based_exec_control = 0;
3200         u32 _cpu_based_exec_control = 0;
3201         u32 _cpu_based_2nd_exec_control = 0;
3202         u32 _vmexit_control = 0;
3203         u32 _vmentry_control = 0;
3204
3205         min = CPU_BASED_HLT_EXITING |
3206 #ifdef CONFIG_X86_64
3207               CPU_BASED_CR8_LOAD_EXITING |
3208               CPU_BASED_CR8_STORE_EXITING |
3209 #endif
3210               CPU_BASED_CR3_LOAD_EXITING |
3211               CPU_BASED_CR3_STORE_EXITING |
3212               CPU_BASED_USE_IO_BITMAPS |
3213               CPU_BASED_MOV_DR_EXITING |
3214               CPU_BASED_USE_TSC_OFFSETING |
3215               CPU_BASED_MWAIT_EXITING |
3216               CPU_BASED_MONITOR_EXITING |
3217               CPU_BASED_INVLPG_EXITING |
3218               CPU_BASED_RDPMC_EXITING;
3219
3220         opt = CPU_BASED_TPR_SHADOW |
3221               CPU_BASED_USE_MSR_BITMAPS |
3222               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3223         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3224                                 &_cpu_based_exec_control) < 0)
3225                 return -EIO;
3226 #ifdef CONFIG_X86_64
3227         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3228                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3229                                            ~CPU_BASED_CR8_STORE_EXITING;
3230 #endif
3231         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3232                 min2 = 0;
3233                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3234                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3235                         SECONDARY_EXEC_WBINVD_EXITING |
3236                         SECONDARY_EXEC_ENABLE_VPID |
3237                         SECONDARY_EXEC_ENABLE_EPT |
3238                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3239                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3240                         SECONDARY_EXEC_RDTSCP |
3241                         SECONDARY_EXEC_ENABLE_INVPCID |
3242                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3243                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3244                         SECONDARY_EXEC_SHADOW_VMCS |
3245                         SECONDARY_EXEC_XSAVES |
3246                         SECONDARY_EXEC_ENABLE_PML |
3247                         SECONDARY_EXEC_PCOMMIT |
3248                         SECONDARY_EXEC_TSC_SCALING;
3249                 if (adjust_vmx_controls(min2, opt2,
3250                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3251                                         &_cpu_based_2nd_exec_control) < 0)
3252                         return -EIO;
3253         }
3254 #ifndef CONFIG_X86_64
3255         if (!(_cpu_based_2nd_exec_control &
3256                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3257                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3258 #endif
3259
3260         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3261                 _cpu_based_2nd_exec_control &= ~(
3262                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3263                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3264                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3265
3266         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3267                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3268                    enabled */
3269                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3270                                              CPU_BASED_CR3_STORE_EXITING |
3271                                              CPU_BASED_INVLPG_EXITING);
3272                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3273                       vmx_capability.ept, vmx_capability.vpid);
3274         }
3275
3276         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3277 #ifdef CONFIG_X86_64
3278         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3279 #endif
3280         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3281                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3282         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3283                                 &_vmexit_control) < 0)
3284                 return -EIO;
3285
3286         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3287         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3288         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3289                                 &_pin_based_exec_control) < 0)
3290                 return -EIO;
3291
3292         if (!(_cpu_based_2nd_exec_control &
3293                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3294                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3295                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3296
3297         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3298         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3299         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3300                                 &_vmentry_control) < 0)
3301                 return -EIO;
3302
3303         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3304
3305         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3306         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3307                 return -EIO;
3308
3309 #ifdef CONFIG_X86_64
3310         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3311         if (vmx_msr_high & (1u<<16))
3312                 return -EIO;
3313 #endif
3314
3315         /* Require Write-Back (WB) memory type for VMCS accesses. */
3316         if (((vmx_msr_high >> 18) & 15) != 6)
3317                 return -EIO;
3318
3319         vmcs_conf->size = vmx_msr_high & 0x1fff;
3320         vmcs_conf->order = get_order(vmcs_config.size);
3321         vmcs_conf->revision_id = vmx_msr_low;
3322
3323         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3324         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3325         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3326         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3327         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3328
3329         cpu_has_load_ia32_efer =
3330                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3331                                 VM_ENTRY_LOAD_IA32_EFER)
3332                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3333                                    VM_EXIT_LOAD_IA32_EFER);
3334
3335         cpu_has_load_perf_global_ctrl =
3336                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3337                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3338                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3339                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3340
3341         /*
3342          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3343          * but due to arrata below it can't be used. Workaround is to use
3344          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3345          *
3346          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3347          *
3348          * AAK155             (model 26)
3349          * AAP115             (model 30)
3350          * AAT100             (model 37)
3351          * BC86,AAY89,BD102   (model 44)
3352          * BA97               (model 46)
3353          *
3354          */
3355         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3356                 switch (boot_cpu_data.x86_model) {
3357                 case 26:
3358                 case 30:
3359                 case 37:
3360                 case 44:
3361                 case 46:
3362                         cpu_has_load_perf_global_ctrl = false;
3363                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3364                                         "does not work properly. Using workaround\n");
3365                         break;
3366                 default:
3367                         break;
3368                 }
3369         }
3370
3371         if (cpu_has_xsaves)
3372                 rdmsrl(MSR_IA32_XSS, host_xss);
3373
3374         return 0;
3375 }
3376
3377 static struct vmcs *alloc_vmcs_cpu(int cpu)
3378 {
3379         int node = cpu_to_node(cpu);
3380         struct page *pages;
3381         struct vmcs *vmcs;
3382
3383         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3384         if (!pages)
3385                 return NULL;
3386         vmcs = page_address(pages);
3387         memset(vmcs, 0, vmcs_config.size);
3388         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3389         return vmcs;
3390 }
3391
3392 static struct vmcs *alloc_vmcs(void)
3393 {
3394         return alloc_vmcs_cpu(raw_smp_processor_id());
3395 }
3396
3397 static void free_vmcs(struct vmcs *vmcs)
3398 {
3399         free_pages((unsigned long)vmcs, vmcs_config.order);
3400 }
3401
3402 /*
3403  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3404  */
3405 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3406 {
3407         if (!loaded_vmcs->vmcs)
3408                 return;
3409         loaded_vmcs_clear(loaded_vmcs);
3410         free_vmcs(loaded_vmcs->vmcs);
3411         loaded_vmcs->vmcs = NULL;
3412 }
3413
3414 static void free_kvm_area(void)
3415 {
3416         int cpu;
3417
3418         for_each_possible_cpu(cpu) {
3419                 free_vmcs(per_cpu(vmxarea, cpu));
3420                 per_cpu(vmxarea, cpu) = NULL;
3421         }
3422 }
3423
3424 static void init_vmcs_shadow_fields(void)
3425 {
3426         int i, j;
3427
3428         /* No checks for read only fields yet */
3429
3430         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3431                 switch (shadow_read_write_fields[i]) {
3432                 case GUEST_BNDCFGS:
3433                         if (!kvm_mpx_supported())
3434                                 continue;
3435                         break;
3436                 default:
3437                         break;
3438                 }
3439
3440                 if (j < i)
3441                         shadow_read_write_fields[j] =
3442                                 shadow_read_write_fields[i];
3443                 j++;
3444         }
3445         max_shadow_read_write_fields = j;
3446
3447         /* shadowed fields guest access without vmexit */
3448         for (i = 0; i < max_shadow_read_write_fields; i++) {
3449                 clear_bit(shadow_read_write_fields[i],
3450                           vmx_vmwrite_bitmap);
3451                 clear_bit(shadow_read_write_fields[i],
3452                           vmx_vmread_bitmap);
3453         }
3454         for (i = 0; i < max_shadow_read_only_fields; i++)
3455                 clear_bit(shadow_read_only_fields[i],
3456                           vmx_vmread_bitmap);
3457 }
3458
3459 static __init int alloc_kvm_area(void)
3460 {
3461         int cpu;
3462
3463         for_each_possible_cpu(cpu) {
3464                 struct vmcs *vmcs;
3465
3466                 vmcs = alloc_vmcs_cpu(cpu);
3467                 if (!vmcs) {
3468                         free_kvm_area();
3469                         return -ENOMEM;
3470                 }
3471
3472                 per_cpu(vmxarea, cpu) = vmcs;
3473         }
3474         return 0;
3475 }
3476
3477 static bool emulation_required(struct kvm_vcpu *vcpu)
3478 {
3479         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3480 }
3481
3482 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3483                 struct kvm_segment *save)
3484 {
3485         if (!emulate_invalid_guest_state) {
3486                 /*
3487                  * CS and SS RPL should be equal during guest entry according
3488                  * to VMX spec, but in reality it is not always so. Since vcpu
3489                  * is in the middle of the transition from real mode to
3490                  * protected mode it is safe to assume that RPL 0 is a good
3491                  * default value.
3492                  */
3493                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3494                         save->selector &= ~SEGMENT_RPL_MASK;
3495                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3496                 save->s = 1;
3497         }
3498         vmx_set_segment(vcpu, save, seg);
3499 }
3500
3501 static void enter_pmode(struct kvm_vcpu *vcpu)
3502 {
3503         unsigned long flags;
3504         struct vcpu_vmx *vmx = to_vmx(vcpu);
3505
3506         /*
3507          * Update real mode segment cache. It may be not up-to-date if sement
3508          * register was written while vcpu was in a guest mode.
3509          */
3510         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3511         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3512         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3513         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3514         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3515         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3516
3517         vmx->rmode.vm86_active = 0;
3518
3519         vmx_segment_cache_clear(vmx);
3520
3521         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3522
3523         flags = vmcs_readl(GUEST_RFLAGS);
3524         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3525         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3526         vmcs_writel(GUEST_RFLAGS, flags);
3527
3528         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3529                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3530
3531         update_exception_bitmap(vcpu);
3532
3533         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3534         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3535         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3536         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3537         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3538         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3539 }
3540
3541 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3542 {
3543         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3544         struct kvm_segment var = *save;
3545
3546         var.dpl = 0x3;
3547         if (seg == VCPU_SREG_CS)
3548                 var.type = 0x3;
3549
3550         if (!emulate_invalid_guest_state) {
3551                 var.selector = var.base >> 4;
3552                 var.base = var.base & 0xffff0;
3553                 var.limit = 0xffff;
3554                 var.g = 0;
3555                 var.db = 0;
3556                 var.present = 1;
3557                 var.s = 1;
3558                 var.l = 0;
3559                 var.unusable = 0;
3560                 var.type = 0x3;
3561                 var.avl = 0;
3562                 if (save->base & 0xf)
3563                         printk_once(KERN_WARNING "kvm: segment base is not "
3564                                         "paragraph aligned when entering "
3565                                         "protected mode (seg=%d)", seg);
3566         }
3567
3568         vmcs_write16(sf->selector, var.selector);
3569         vmcs_write32(sf->base, var.base);
3570         vmcs_write32(sf->limit, var.limit);
3571         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3572 }
3573
3574 static void enter_rmode(struct kvm_vcpu *vcpu)
3575 {
3576         unsigned long flags;
3577         struct vcpu_vmx *vmx = to_vmx(vcpu);
3578
3579         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3580         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3581         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3582         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3583         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3584         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3585         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3586
3587         vmx->rmode.vm86_active = 1;
3588
3589         /*
3590          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3591          * vcpu. Warn the user that an update is overdue.
3592          */
3593         if (!vcpu->kvm->arch.tss_addr)
3594                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3595                              "called before entering vcpu\n");
3596
3597         vmx_segment_cache_clear(vmx);
3598
3599         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3600         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3601         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3602
3603         flags = vmcs_readl(GUEST_RFLAGS);
3604         vmx->rmode.save_rflags = flags;
3605
3606         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3607
3608         vmcs_writel(GUEST_RFLAGS, flags);
3609         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3610         update_exception_bitmap(vcpu);
3611
3612         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3613         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3614         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3615         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3616         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3617         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3618
3619         kvm_mmu_reset_context(vcpu);
3620 }
3621
3622 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3623 {
3624         struct vcpu_vmx *vmx = to_vmx(vcpu);
3625         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3626
3627         if (!msr)
3628                 return;
3629
3630         /*
3631          * Force kernel_gs_base reloading before EFER changes, as control
3632          * of this msr depends on is_long_mode().
3633          */
3634         vmx_load_host_state(to_vmx(vcpu));
3635         vcpu->arch.efer = efer;
3636         if (efer & EFER_LMA) {
3637                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3638                 msr->data = efer;
3639         } else {
3640                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3641
3642                 msr->data = efer & ~EFER_LME;
3643         }
3644         setup_msrs(vmx);
3645 }
3646
3647 #ifdef CONFIG_X86_64
3648
3649 static void enter_lmode(struct kvm_vcpu *vcpu)
3650 {
3651         u32 guest_tr_ar;
3652
3653         vmx_segment_cache_clear(to_vmx(vcpu));
3654
3655         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3656         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3657                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3658                                      __func__);
3659                 vmcs_write32(GUEST_TR_AR_BYTES,
3660                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3661                              | VMX_AR_TYPE_BUSY_64_TSS);
3662         }
3663         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3664 }
3665
3666 static void exit_lmode(struct kvm_vcpu *vcpu)
3667 {
3668         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3669         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3670 }
3671
3672 #endif
3673
3674 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3675 {
3676         vpid_sync_context(vpid);
3677         if (enable_ept) {
3678                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3679                         return;
3680                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3681         }
3682 }
3683
3684 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3685 {
3686         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3687 }
3688
3689 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3690 {
3691         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3692
3693         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3694         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3695 }
3696
3697 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3698 {
3699         if (enable_ept && is_paging(vcpu))
3700                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3701         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3702 }
3703
3704 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3705 {
3706         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3707
3708         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3709         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3710 }
3711
3712 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3713 {
3714         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3715
3716         if (!test_bit(VCPU_EXREG_PDPTR,
3717                       (unsigned long *)&vcpu->arch.regs_dirty))
3718                 return;
3719
3720         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3721                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3722                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3723                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3724                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3725         }
3726 }
3727
3728 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3729 {
3730         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3731
3732         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3733                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3734                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3735                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3736                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3737         }
3738
3739         __set_bit(VCPU_EXREG_PDPTR,
3740                   (unsigned long *)&vcpu->arch.regs_avail);
3741         __set_bit(VCPU_EXREG_PDPTR,
3742                   (unsigned long *)&vcpu->arch.regs_dirty);
3743 }
3744
3745 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3746
3747 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3748                                         unsigned long cr0,
3749                                         struct kvm_vcpu *vcpu)
3750 {
3751         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3752                 vmx_decache_cr3(vcpu);
3753         if (!(cr0 & X86_CR0_PG)) {
3754                 /* From paging/starting to nonpaging */
3755                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3756                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3757                              (CPU_BASED_CR3_LOAD_EXITING |
3758                               CPU_BASED_CR3_STORE_EXITING));
3759                 vcpu->arch.cr0 = cr0;
3760                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3761         } else if (!is_paging(vcpu)) {
3762                 /* From nonpaging to paging */
3763                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3764                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3765                              ~(CPU_BASED_CR3_LOAD_EXITING |
3766                                CPU_BASED_CR3_STORE_EXITING));
3767                 vcpu->arch.cr0 = cr0;
3768                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3769         }
3770
3771         if (!(cr0 & X86_CR0_WP))
3772                 *hw_cr0 &= ~X86_CR0_WP;
3773 }
3774
3775 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3776 {
3777         struct vcpu_vmx *vmx = to_vmx(vcpu);
3778         unsigned long hw_cr0;
3779
3780         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3781         if (enable_unrestricted_guest)
3782                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3783         else {
3784                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3785
3786                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3787                         enter_pmode(vcpu);
3788
3789                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3790                         enter_rmode(vcpu);
3791         }
3792
3793 #ifdef CONFIG_X86_64
3794         if (vcpu->arch.efer & EFER_LME) {
3795                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3796                         enter_lmode(vcpu);
3797                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3798                         exit_lmode(vcpu);
3799         }
3800 #endif
3801
3802         if (enable_ept)
3803                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3804
3805         if (!vcpu->fpu_active)
3806                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3807
3808         vmcs_writel(CR0_READ_SHADOW, cr0);
3809         vmcs_writel(GUEST_CR0, hw_cr0);
3810         vcpu->arch.cr0 = cr0;
3811
3812         /* depends on vcpu->arch.cr0 to be set to a new value */
3813         vmx->emulation_required = emulation_required(vcpu);
3814 }
3815
3816 static u64 construct_eptp(unsigned long root_hpa)
3817 {
3818         u64 eptp;
3819
3820         /* TODO write the value reading from MSR */
3821         eptp = VMX_EPT_DEFAULT_MT |
3822                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3823         if (enable_ept_ad_bits)
3824                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3825         eptp |= (root_hpa & PAGE_MASK);
3826
3827         return eptp;
3828 }
3829
3830 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3831 {
3832         unsigned long guest_cr3;
3833         u64 eptp;
3834
3835         guest_cr3 = cr3;
3836         if (enable_ept) {
3837                 eptp = construct_eptp(cr3);
3838                 vmcs_write64(EPT_POINTER, eptp);
3839                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3840                         guest_cr3 = kvm_read_cr3(vcpu);
3841                 else
3842                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3843                 ept_load_pdptrs(vcpu);
3844         }
3845
3846         vmx_flush_tlb(vcpu);
3847         vmcs_writel(GUEST_CR3, guest_cr3);
3848 }
3849
3850 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3851 {
3852         /*
3853          * Pass through host's Machine Check Enable value to hw_cr4, which
3854          * is in force while we are in guest mode.  Do not let guests control
3855          * this bit, even if host CR4.MCE == 0.
3856          */
3857         unsigned long hw_cr4 =
3858                 (cr4_read_shadow() & X86_CR4_MCE) |
3859                 (cr4 & ~X86_CR4_MCE) |
3860                 (to_vmx(vcpu)->rmode.vm86_active ?
3861                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3862
3863         if (cr4 & X86_CR4_VMXE) {
3864                 /*
3865                  * To use VMXON (and later other VMX instructions), a guest
3866                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3867                  * So basically the check on whether to allow nested VMX
3868                  * is here.
3869                  */
3870                 if (!nested_vmx_allowed(vcpu))
3871                         return 1;
3872         }
3873         if (to_vmx(vcpu)->nested.vmxon &&
3874             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3875                 return 1;
3876
3877         vcpu->arch.cr4 = cr4;
3878         if (enable_ept) {
3879                 if (!is_paging(vcpu)) {
3880                         hw_cr4 &= ~X86_CR4_PAE;
3881                         hw_cr4 |= X86_CR4_PSE;
3882                 } else if (!(cr4 & X86_CR4_PAE)) {
3883                         hw_cr4 &= ~X86_CR4_PAE;
3884                 }
3885         }
3886
3887         if (!enable_unrestricted_guest && !is_paging(vcpu))
3888                 /*
3889                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3890                  * hardware.  However KVM always uses paging mode without
3891                  * unrestricted guest.
3892                  * To emulate this behavior, SMEP/SMAP needs to be manually
3893                  * disabled when guest switches to non-paging mode.
3894                  */
3895                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3896
3897         vmcs_writel(CR4_READ_SHADOW, cr4);
3898         vmcs_writel(GUEST_CR4, hw_cr4);
3899         return 0;
3900 }
3901
3902 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3903                             struct kvm_segment *var, int seg)
3904 {
3905         struct vcpu_vmx *vmx = to_vmx(vcpu);
3906         u32 ar;
3907
3908         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3909                 *var = vmx->rmode.segs[seg];
3910                 if (seg == VCPU_SREG_TR
3911                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3912                         return;
3913                 var->base = vmx_read_guest_seg_base(vmx, seg);
3914                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3915                 return;
3916         }
3917         var->base = vmx_read_guest_seg_base(vmx, seg);
3918         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3919         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3920         ar = vmx_read_guest_seg_ar(vmx, seg);
3921         var->unusable = (ar >> 16) & 1;
3922         var->type = ar & 15;
3923         var->s = (ar >> 4) & 1;
3924         var->dpl = (ar >> 5) & 3;
3925         /*
3926          * Some userspaces do not preserve unusable property. Since usable
3927          * segment has to be present according to VMX spec we can use present
3928          * property to amend userspace bug by making unusable segment always
3929          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3930          * segment as unusable.
3931          */
3932         var->present = !var->unusable;
3933         var->avl = (ar >> 12) & 1;
3934         var->l = (ar >> 13) & 1;
3935         var->db = (ar >> 14) & 1;
3936         var->g = (ar >> 15) & 1;
3937 }
3938
3939 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3940 {
3941         struct kvm_segment s;
3942
3943         if (to_vmx(vcpu)->rmode.vm86_active) {
3944                 vmx_get_segment(vcpu, &s, seg);
3945                 return s.base;
3946         }
3947         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3948 }
3949
3950 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3951 {
3952         struct vcpu_vmx *vmx = to_vmx(vcpu);
3953
3954         if (unlikely(vmx->rmode.vm86_active))
3955                 return 0;
3956         else {
3957                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3958                 return VMX_AR_DPL(ar);
3959         }
3960 }
3961
3962 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3963 {
3964         u32 ar;
3965
3966         if (var->unusable || !var->present)
3967                 ar = 1 << 16;
3968         else {
3969                 ar = var->type & 15;
3970                 ar |= (var->s & 1) << 4;
3971                 ar |= (var->dpl & 3) << 5;
3972                 ar |= (var->present & 1) << 7;
3973                 ar |= (var->avl & 1) << 12;
3974                 ar |= (var->l & 1) << 13;
3975                 ar |= (var->db & 1) << 14;
3976                 ar |= (var->g & 1) << 15;
3977         }
3978
3979         return ar;
3980 }
3981
3982 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3983                             struct kvm_segment *var, int seg)
3984 {
3985         struct vcpu_vmx *vmx = to_vmx(vcpu);
3986         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3987
3988         vmx_segment_cache_clear(vmx);
3989
3990         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3991                 vmx->rmode.segs[seg] = *var;
3992                 if (seg == VCPU_SREG_TR)
3993                         vmcs_write16(sf->selector, var->selector);
3994                 else if (var->s)
3995                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3996                 goto out;
3997         }
3998
3999         vmcs_writel(sf->base, var->base);
4000         vmcs_write32(sf->limit, var->limit);
4001         vmcs_write16(sf->selector, var->selector);
4002
4003         /*
4004          *   Fix the "Accessed" bit in AR field of segment registers for older
4005          * qemu binaries.
4006          *   IA32 arch specifies that at the time of processor reset the
4007          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4008          * is setting it to 0 in the userland code. This causes invalid guest
4009          * state vmexit when "unrestricted guest" mode is turned on.
4010          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4011          * tree. Newer qemu binaries with that qemu fix would not need this
4012          * kvm hack.
4013          */
4014         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4015                 var->type |= 0x1; /* Accessed */
4016
4017         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4018
4019 out:
4020         vmx->emulation_required = emulation_required(vcpu);
4021 }
4022
4023 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4024 {
4025         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4026
4027         *db = (ar >> 14) & 1;
4028         *l = (ar >> 13) & 1;
4029 }
4030
4031 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4032 {
4033         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4034         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4035 }
4036
4037 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4038 {
4039         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4040         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4041 }
4042
4043 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4044 {
4045         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4046         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4047 }
4048
4049 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4050 {
4051         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4052         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4053 }
4054
4055 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4056 {
4057         struct kvm_segment var;
4058         u32 ar;
4059
4060         vmx_get_segment(vcpu, &var, seg);
4061         var.dpl = 0x3;
4062         if (seg == VCPU_SREG_CS)
4063                 var.type = 0x3;
4064         ar = vmx_segment_access_rights(&var);
4065
4066         if (var.base != (var.selector << 4))
4067                 return false;
4068         if (var.limit != 0xffff)
4069                 return false;
4070         if (ar != 0xf3)
4071                 return false;
4072
4073         return true;
4074 }
4075
4076 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4077 {
4078         struct kvm_segment cs;
4079         unsigned int cs_rpl;
4080
4081         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4082         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4083
4084         if (cs.unusable)
4085                 return false;
4086         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4087                 return false;
4088         if (!cs.s)
4089                 return false;
4090         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4091                 if (cs.dpl > cs_rpl)
4092                         return false;
4093         } else {
4094                 if (cs.dpl != cs_rpl)
4095                         return false;
4096         }
4097         if (!cs.present)
4098                 return false;
4099
4100         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4101         return true;
4102 }
4103
4104 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4105 {
4106         struct kvm_segment ss;
4107         unsigned int ss_rpl;
4108
4109         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4110         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4111
4112         if (ss.unusable)
4113                 return true;
4114         if (ss.type != 3 && ss.type != 7)
4115                 return false;
4116         if (!ss.s)
4117                 return false;
4118         if (ss.dpl != ss_rpl) /* DPL != RPL */
4119                 return false;
4120         if (!ss.present)
4121                 return false;
4122
4123         return true;
4124 }
4125
4126 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4127 {
4128         struct kvm_segment var;
4129         unsigned int rpl;
4130
4131         vmx_get_segment(vcpu, &var, seg);
4132         rpl = var.selector & SEGMENT_RPL_MASK;
4133
4134         if (var.unusable)
4135                 return true;
4136         if (!var.s)
4137                 return false;
4138         if (!var.present)
4139                 return false;
4140         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4141                 if (var.dpl < rpl) /* DPL < RPL */
4142                         return false;
4143         }
4144
4145         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4146          * rights flags
4147          */
4148         return true;
4149 }
4150
4151 static bool tr_valid(struct kvm_vcpu *vcpu)
4152 {
4153         struct kvm_segment tr;
4154
4155         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4156
4157         if (tr.unusable)
4158                 return false;
4159         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4160                 return false;
4161         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4162                 return false;
4163         if (!tr.present)
4164                 return false;
4165
4166         return true;
4167 }
4168
4169 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4170 {
4171         struct kvm_segment ldtr;
4172
4173         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4174
4175         if (ldtr.unusable)
4176                 return true;
4177         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4178                 return false;
4179         if (ldtr.type != 2)
4180                 return false;
4181         if (!ldtr.present)
4182                 return false;
4183
4184         return true;
4185 }
4186
4187 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4188 {
4189         struct kvm_segment cs, ss;
4190
4191         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4192         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4193
4194         return ((cs.selector & SEGMENT_RPL_MASK) ==
4195                  (ss.selector & SEGMENT_RPL_MASK));
4196 }
4197
4198 /*
4199  * Check if guest state is valid. Returns true if valid, false if
4200  * not.
4201  * We assume that registers are always usable
4202  */
4203 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4204 {
4205         if (enable_unrestricted_guest)
4206                 return true;
4207
4208         /* real mode guest state checks */
4209         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4210                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4211                         return false;
4212                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4213                         return false;
4214                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4215                         return false;
4216                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4217                         return false;
4218                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4219                         return false;
4220                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4221                         return false;
4222         } else {
4223         /* protected mode guest state checks */
4224                 if (!cs_ss_rpl_check(vcpu))
4225                         return false;
4226                 if (!code_segment_valid(vcpu))
4227                         return false;
4228                 if (!stack_segment_valid(vcpu))
4229                         return false;
4230                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4231                         return false;
4232                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4233                         return false;
4234                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4235                         return false;
4236                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4237                         return false;
4238                 if (!tr_valid(vcpu))
4239                         return false;
4240                 if (!ldtr_valid(vcpu))
4241                         return false;
4242         }
4243         /* TODO:
4244          * - Add checks on RIP
4245          * - Add checks on RFLAGS
4246          */
4247
4248         return true;
4249 }
4250
4251 static int init_rmode_tss(struct kvm *kvm)
4252 {
4253         gfn_t fn;
4254         u16 data = 0;
4255         int idx, r;
4256
4257         idx = srcu_read_lock(&kvm->srcu);
4258         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4259         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4260         if (r < 0)
4261                 goto out;
4262         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4263         r = kvm_write_guest_page(kvm, fn++, &data,
4264                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4265         if (r < 0)
4266                 goto out;
4267         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4268         if (r < 0)
4269                 goto out;
4270         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4271         if (r < 0)
4272                 goto out;
4273         data = ~0;
4274         r = kvm_write_guest_page(kvm, fn, &data,
4275                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4276                                  sizeof(u8));
4277 out:
4278         srcu_read_unlock(&kvm->srcu, idx);
4279         return r;
4280 }
4281
4282 static int init_rmode_identity_map(struct kvm *kvm)
4283 {
4284         int i, idx, r = 0;
4285         kvm_pfn_t identity_map_pfn;
4286         u32 tmp;
4287
4288         if (!enable_ept)
4289                 return 0;
4290
4291         /* Protect kvm->arch.ept_identity_pagetable_done. */
4292         mutex_lock(&kvm->slots_lock);
4293
4294         if (likely(kvm->arch.ept_identity_pagetable_done))
4295                 goto out2;
4296
4297         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4298
4299         r = alloc_identity_pagetable(kvm);
4300         if (r < 0)
4301                 goto out2;
4302
4303         idx = srcu_read_lock(&kvm->srcu);
4304         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4305         if (r < 0)
4306                 goto out;
4307         /* Set up identity-mapping pagetable for EPT in real mode */
4308         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4309                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4310                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4311                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4312                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4313                 if (r < 0)
4314                         goto out;
4315         }
4316         kvm->arch.ept_identity_pagetable_done = true;
4317
4318 out:
4319         srcu_read_unlock(&kvm->srcu, idx);
4320
4321 out2:
4322         mutex_unlock(&kvm->slots_lock);
4323         return r;
4324 }
4325
4326 static void seg_setup(int seg)
4327 {
4328         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4329         unsigned int ar;
4330
4331         vmcs_write16(sf->selector, 0);
4332         vmcs_writel(sf->base, 0);
4333         vmcs_write32(sf->limit, 0xffff);
4334         ar = 0x93;
4335         if (seg == VCPU_SREG_CS)
4336                 ar |= 0x08; /* code segment */
4337
4338         vmcs_write32(sf->ar_bytes, ar);
4339 }
4340
4341 static int alloc_apic_access_page(struct kvm *kvm)
4342 {
4343         struct page *page;
4344         int r = 0;
4345
4346         mutex_lock(&kvm->slots_lock);
4347         if (kvm->arch.apic_access_page_done)
4348                 goto out;
4349         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4350                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4351         if (r)
4352                 goto out;
4353
4354         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4355         if (is_error_page(page)) {
4356                 r = -EFAULT;
4357                 goto out;
4358         }
4359
4360         /*
4361          * Do not pin the page in memory, so that memory hot-unplug
4362          * is able to migrate it.
4363          */
4364         put_page(page);
4365         kvm->arch.apic_access_page_done = true;
4366 out:
4367         mutex_unlock(&kvm->slots_lock);
4368         return r;
4369 }
4370
4371 static int alloc_identity_pagetable(struct kvm *kvm)
4372 {
4373         /* Called with kvm->slots_lock held. */
4374
4375         int r = 0;
4376
4377         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4378
4379         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4380                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4381
4382         return r;
4383 }
4384
4385 static int allocate_vpid(void)
4386 {
4387         int vpid;
4388
4389         if (!enable_vpid)
4390                 return 0;
4391         spin_lock(&vmx_vpid_lock);
4392         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4393         if (vpid < VMX_NR_VPIDS)
4394                 __set_bit(vpid, vmx_vpid_bitmap);
4395         else
4396                 vpid = 0;
4397         spin_unlock(&vmx_vpid_lock);
4398         return vpid;
4399 }
4400
4401 static void free_vpid(int vpid)
4402 {
4403         if (!enable_vpid || vpid == 0)
4404                 return;
4405         spin_lock(&vmx_vpid_lock);
4406         __clear_bit(vpid, vmx_vpid_bitmap);
4407         spin_unlock(&vmx_vpid_lock);
4408 }
4409
4410 #define MSR_TYPE_R      1
4411 #define MSR_TYPE_W      2
4412 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4413                                                 u32 msr, int type)
4414 {
4415         int f = sizeof(unsigned long);
4416
4417         if (!cpu_has_vmx_msr_bitmap())
4418                 return;
4419
4420         /*
4421          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4422          * have the write-low and read-high bitmap offsets the wrong way round.
4423          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4424          */
4425         if (msr <= 0x1fff) {
4426                 if (type & MSR_TYPE_R)
4427                         /* read-low */
4428                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4429
4430                 if (type & MSR_TYPE_W)
4431                         /* write-low */
4432                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4433
4434         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4435                 msr &= 0x1fff;
4436                 if (type & MSR_TYPE_R)
4437                         /* read-high */
4438                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4439
4440                 if (type & MSR_TYPE_W)
4441                         /* write-high */
4442                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4443
4444         }
4445 }
4446
4447 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4448                                                 u32 msr, int type)
4449 {
4450         int f = sizeof(unsigned long);
4451
4452         if (!cpu_has_vmx_msr_bitmap())
4453                 return;
4454
4455         /*
4456          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4457          * have the write-low and read-high bitmap offsets the wrong way round.
4458          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4459          */
4460         if (msr <= 0x1fff) {
4461                 if (type & MSR_TYPE_R)
4462                         /* read-low */
4463                         __set_bit(msr, msr_bitmap + 0x000 / f);
4464
4465                 if (type & MSR_TYPE_W)
4466                         /* write-low */
4467                         __set_bit(msr, msr_bitmap + 0x800 / f);
4468
4469         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4470                 msr &= 0x1fff;
4471                 if (type & MSR_TYPE_R)
4472                         /* read-high */
4473                         __set_bit(msr, msr_bitmap + 0x400 / f);
4474
4475                 if (type & MSR_TYPE_W)
4476                         /* write-high */
4477                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4478
4479         }
4480 }
4481
4482 /*
4483  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4484  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4485  */
4486 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4487                                                unsigned long *msr_bitmap_nested,
4488                                                u32 msr, int type)
4489 {
4490         int f = sizeof(unsigned long);
4491
4492         if (!cpu_has_vmx_msr_bitmap()) {
4493                 WARN_ON(1);
4494                 return;
4495         }
4496
4497         /*
4498          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4499          * have the write-low and read-high bitmap offsets the wrong way round.
4500          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4501          */
4502         if (msr <= 0x1fff) {
4503                 if (type & MSR_TYPE_R &&
4504                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4505                         /* read-low */
4506                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4507
4508                 if (type & MSR_TYPE_W &&
4509                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4510                         /* write-low */
4511                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4512
4513         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4514                 msr &= 0x1fff;
4515                 if (type & MSR_TYPE_R &&
4516                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4517                         /* read-high */
4518                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4519
4520                 if (type & MSR_TYPE_W &&
4521                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4522                         /* write-high */
4523                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4524
4525         }
4526 }
4527
4528 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4529 {
4530         if (!longmode_only)
4531                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4532                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4533         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4534                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4535 }
4536
4537 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4538 {
4539         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4540                         msr, MSR_TYPE_R);
4541         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4542                         msr, MSR_TYPE_R);
4543 }
4544
4545 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4546 {
4547         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4548                         msr, MSR_TYPE_R);
4549         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4550                         msr, MSR_TYPE_R);
4551 }
4552
4553 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4554 {
4555         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4556                         msr, MSR_TYPE_W);
4557         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4558                         msr, MSR_TYPE_W);
4559 }
4560
4561 static bool vmx_get_enable_apicv(void)
4562 {
4563         return enable_apicv;
4564 }
4565
4566 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4567 {
4568         struct vcpu_vmx *vmx = to_vmx(vcpu);
4569         int max_irr;
4570         void *vapic_page;
4571         u16 status;
4572
4573         if (vmx->nested.pi_desc &&
4574             vmx->nested.pi_pending) {
4575                 vmx->nested.pi_pending = false;
4576                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4577                         return 0;
4578
4579                 max_irr = find_last_bit(
4580                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4581
4582                 if (max_irr == 256)
4583                         return 0;
4584
4585                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4586                 if (!vapic_page) {
4587                         WARN_ON(1);
4588                         return -ENOMEM;
4589                 }
4590                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4591                 kunmap(vmx->nested.virtual_apic_page);
4592
4593                 status = vmcs_read16(GUEST_INTR_STATUS);
4594                 if ((u8)max_irr > ((u8)status & 0xff)) {
4595                         status &= ~0xff;
4596                         status |= (u8)max_irr;
4597                         vmcs_write16(GUEST_INTR_STATUS, status);
4598                 }
4599         }
4600         return 0;
4601 }
4602
4603 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4604 {
4605 #ifdef CONFIG_SMP
4606         if (vcpu->mode == IN_GUEST_MODE) {
4607                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4608
4609                 /*
4610                  * Currently, we don't support urgent interrupt,
4611                  * all interrupts are recognized as non-urgent
4612                  * interrupt, so we cannot post interrupts when
4613                  * 'SN' is set.
4614                  *
4615                  * If the vcpu is in guest mode, it means it is
4616                  * running instead of being scheduled out and
4617                  * waiting in the run queue, and that's the only
4618                  * case when 'SN' is set currently, warning if
4619                  * 'SN' is set.
4620                  */
4621                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4622
4623                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4624                                 POSTED_INTR_VECTOR);
4625                 return true;
4626         }
4627 #endif
4628         return false;
4629 }
4630
4631 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4632                                                 int vector)
4633 {
4634         struct vcpu_vmx *vmx = to_vmx(vcpu);
4635
4636         if (is_guest_mode(vcpu) &&
4637             vector == vmx->nested.posted_intr_nv) {
4638                 /* the PIR and ON have been set by L1. */
4639                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4640                 /*
4641                  * If a posted intr is not recognized by hardware,
4642                  * we will accomplish it in the next vmentry.
4643                  */
4644                 vmx->nested.pi_pending = true;
4645                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4646                 return 0;
4647         }
4648         return -1;
4649 }
4650 /*
4651  * Send interrupt to vcpu via posted interrupt way.
4652  * 1. If target vcpu is running(non-root mode), send posted interrupt
4653  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4654  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4655  * interrupt from PIR in next vmentry.
4656  */
4657 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4658 {
4659         struct vcpu_vmx *vmx = to_vmx(vcpu);
4660         int r;
4661
4662         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4663         if (!r)
4664                 return;
4665
4666         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4667                 return;
4668
4669         r = pi_test_and_set_on(&vmx->pi_desc);
4670         kvm_make_request(KVM_REQ_EVENT, vcpu);
4671         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4672                 kvm_vcpu_kick(vcpu);
4673 }
4674
4675 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4676 {
4677         struct vcpu_vmx *vmx = to_vmx(vcpu);
4678
4679         if (!pi_test_and_clear_on(&vmx->pi_desc))
4680                 return;
4681
4682         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4683 }
4684
4685 /*
4686  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4687  * will not change in the lifetime of the guest.
4688  * Note that host-state that does change is set elsewhere. E.g., host-state
4689  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4690  */
4691 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4692 {
4693         u32 low32, high32;
4694         unsigned long tmpl;
4695         struct desc_ptr dt;
4696         unsigned long cr4;
4697
4698         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4699         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4700
4701         /* Save the most likely value for this task's CR4 in the VMCS. */
4702         cr4 = cr4_read_shadow();
4703         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4704         vmx->host_state.vmcs_host_cr4 = cr4;
4705
4706         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4707 #ifdef CONFIG_X86_64
4708         /*
4709          * Load null selectors, so we can avoid reloading them in
4710          * __vmx_load_host_state(), in case userspace uses the null selectors
4711          * too (the expected case).
4712          */
4713         vmcs_write16(HOST_DS_SELECTOR, 0);
4714         vmcs_write16(HOST_ES_SELECTOR, 0);
4715 #else
4716         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4717         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4718 #endif
4719         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4720         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4721
4722         native_store_idt(&dt);
4723         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4724         vmx->host_idt_base = dt.address;
4725
4726         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4727
4728         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4729         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4730         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4731         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4732
4733         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4734                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4735                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4736         }
4737 }
4738
4739 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4740 {
4741         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4742         if (enable_ept)
4743                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4744         if (is_guest_mode(&vmx->vcpu))
4745                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4746                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4747         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4748 }
4749
4750 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4751 {
4752         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4753
4754         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4755                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4756         return pin_based_exec_ctrl;
4757 }
4758
4759 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4760 {
4761         struct vcpu_vmx *vmx = to_vmx(vcpu);
4762
4763         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4764 }
4765
4766 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4767 {
4768         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4769
4770         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4771                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4772
4773         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4774                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4775 #ifdef CONFIG_X86_64
4776                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4777                                 CPU_BASED_CR8_LOAD_EXITING;
4778 #endif
4779         }
4780         if (!enable_ept)
4781                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4782                                 CPU_BASED_CR3_LOAD_EXITING  |
4783                                 CPU_BASED_INVLPG_EXITING;
4784         return exec_control;
4785 }
4786
4787 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4788 {
4789         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4790         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4791                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4792         if (vmx->vpid == 0)
4793                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4794         if (!enable_ept) {
4795                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4796                 enable_unrestricted_guest = 0;
4797                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4798                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4799         }
4800         if (!enable_unrestricted_guest)
4801                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4802         if (!ple_gap)
4803                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4804         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4805                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4806                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4807         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4808         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4809            (handle_vmptrld).
4810            We can NOT enable shadow_vmcs here because we don't have yet
4811            a current VMCS12
4812         */
4813         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4814
4815         if (!enable_pml)
4816                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4817
4818         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4819         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4820
4821         return exec_control;
4822 }
4823
4824 static void ept_set_mmio_spte_mask(void)
4825 {
4826         /*
4827          * EPT Misconfigurations can be generated if the value of bits 2:0
4828          * of an EPT paging-structure entry is 110b (write/execute).
4829          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4830          * spte.
4831          */
4832         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4833 }
4834
4835 #define VMX_XSS_EXIT_BITMAP 0
4836 /*
4837  * Sets up the vmcs for emulated real mode.
4838  */
4839 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4840 {
4841 #ifdef CONFIG_X86_64
4842         unsigned long a;
4843 #endif
4844         int i;
4845
4846         /* I/O */
4847         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4848         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4849
4850         if (enable_shadow_vmcs) {
4851                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4852                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4853         }
4854         if (cpu_has_vmx_msr_bitmap())
4855                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4856
4857         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4858
4859         /* Control */
4860         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4861
4862         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4863
4864         if (cpu_has_secondary_exec_ctrls())
4865                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4866                                 vmx_secondary_exec_control(vmx));
4867
4868         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4869                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4870                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4871                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4872                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4873
4874                 vmcs_write16(GUEST_INTR_STATUS, 0);
4875
4876                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4877                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4878         }
4879
4880         if (ple_gap) {
4881                 vmcs_write32(PLE_GAP, ple_gap);
4882                 vmx->ple_window = ple_window;
4883                 vmx->ple_window_dirty = true;
4884         }
4885
4886         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4887         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4888         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4889
4890         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4891         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4892         vmx_set_constant_host_state(vmx);
4893 #ifdef CONFIG_X86_64
4894         rdmsrl(MSR_FS_BASE, a);
4895         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4896         rdmsrl(MSR_GS_BASE, a);
4897         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4898 #else
4899         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4900         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4901 #endif
4902
4903         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4904         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4905         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4906         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4907         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4908
4909         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4910                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4911
4912         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4913                 u32 index = vmx_msr_index[i];
4914                 u32 data_low, data_high;
4915                 int j = vmx->nmsrs;
4916
4917                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4918                         continue;
4919                 if (wrmsr_safe(index, data_low, data_high) < 0)
4920                         continue;
4921                 vmx->guest_msrs[j].index = i;
4922                 vmx->guest_msrs[j].data = 0;
4923                 vmx->guest_msrs[j].mask = -1ull;
4924                 ++vmx->nmsrs;
4925         }
4926
4927
4928         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4929
4930         /* 22.2.1, 20.8.1 */
4931         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4932
4933         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4934         set_cr4_guest_host_mask(vmx);
4935
4936         if (vmx_xsaves_supported())
4937                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4938
4939         return 0;
4940 }
4941
4942 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4943 {
4944         struct vcpu_vmx *vmx = to_vmx(vcpu);
4945         struct msr_data apic_base_msr;
4946         u64 cr0;
4947
4948         vmx->rmode.vm86_active = 0;
4949
4950         vmx->soft_vnmi_blocked = 0;
4951
4952         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4953         kvm_set_cr8(vcpu, 0);
4954
4955         if (!init_event) {
4956                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4957                                      MSR_IA32_APICBASE_ENABLE;
4958                 if (kvm_vcpu_is_reset_bsp(vcpu))
4959                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4960                 apic_base_msr.host_initiated = true;
4961                 kvm_set_apic_base(vcpu, &apic_base_msr);
4962         }
4963
4964         vmx_segment_cache_clear(vmx);
4965
4966         seg_setup(VCPU_SREG_CS);
4967         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4968         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4969
4970         seg_setup(VCPU_SREG_DS);
4971         seg_setup(VCPU_SREG_ES);
4972         seg_setup(VCPU_SREG_FS);
4973         seg_setup(VCPU_SREG_GS);
4974         seg_setup(VCPU_SREG_SS);
4975
4976         vmcs_write16(GUEST_TR_SELECTOR, 0);
4977         vmcs_writel(GUEST_TR_BASE, 0);
4978         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4979         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4980
4981         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4982         vmcs_writel(GUEST_LDTR_BASE, 0);
4983         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4984         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4985
4986         if (!init_event) {
4987                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4988                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4989                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4990                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4991         }
4992
4993         vmcs_writel(GUEST_RFLAGS, 0x02);
4994         kvm_rip_write(vcpu, 0xfff0);
4995
4996         vmcs_writel(GUEST_GDTR_BASE, 0);
4997         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4998
4999         vmcs_writel(GUEST_IDTR_BASE, 0);
5000         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5001
5002         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5003         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5004         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5005
5006         setup_msrs(vmx);
5007
5008         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5009
5010         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5011                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5012                 if (cpu_need_tpr_shadow(vcpu))
5013                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5014                                      __pa(vcpu->arch.apic->regs));
5015                 vmcs_write32(TPR_THRESHOLD, 0);
5016         }
5017
5018         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5019
5020         if (kvm_vcpu_apicv_active(vcpu))
5021                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5022
5023         if (vmx->vpid != 0)
5024                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5025
5026         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5027         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5028         vmx->vcpu.arch.cr0 = cr0;
5029         vmx_set_cr4(vcpu, 0);
5030         vmx_set_efer(vcpu, 0);
5031         vmx_fpu_activate(vcpu);
5032         update_exception_bitmap(vcpu);
5033
5034         vpid_sync_context(vmx->vpid);
5035 }
5036
5037 /*
5038  * In nested virtualization, check if L1 asked to exit on external interrupts.
5039  * For most existing hypervisors, this will always return true.
5040  */
5041 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5042 {
5043         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5044                 PIN_BASED_EXT_INTR_MASK;
5045 }
5046
5047 /*
5048  * In nested virtualization, check if L1 has set
5049  * VM_EXIT_ACK_INTR_ON_EXIT
5050  */
5051 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5052 {
5053         return get_vmcs12(vcpu)->vm_exit_controls &
5054                 VM_EXIT_ACK_INTR_ON_EXIT;
5055 }
5056
5057 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5058 {
5059         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5060                 PIN_BASED_NMI_EXITING;
5061 }
5062
5063 static void enable_irq_window(struct kvm_vcpu *vcpu)
5064 {
5065         u32 cpu_based_vm_exec_control;
5066
5067         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5068         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5069         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5070 }
5071
5072 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5073 {
5074         u32 cpu_based_vm_exec_control;
5075
5076         if (!cpu_has_virtual_nmis() ||
5077             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5078                 enable_irq_window(vcpu);
5079                 return;
5080         }
5081
5082         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5083         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5084         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5085 }
5086
5087 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5088 {
5089         struct vcpu_vmx *vmx = to_vmx(vcpu);
5090         uint32_t intr;
5091         int irq = vcpu->arch.interrupt.nr;
5092
5093         trace_kvm_inj_virq(irq);
5094
5095         ++vcpu->stat.irq_injections;
5096         if (vmx->rmode.vm86_active) {
5097                 int inc_eip = 0;
5098                 if (vcpu->arch.interrupt.soft)
5099                         inc_eip = vcpu->arch.event_exit_inst_len;
5100                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5101                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5102                 return;
5103         }
5104         intr = irq | INTR_INFO_VALID_MASK;
5105         if (vcpu->arch.interrupt.soft) {
5106                 intr |= INTR_TYPE_SOFT_INTR;
5107                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5108                              vmx->vcpu.arch.event_exit_inst_len);
5109         } else
5110                 intr |= INTR_TYPE_EXT_INTR;
5111         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5112 }
5113
5114 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5115 {
5116         struct vcpu_vmx *vmx = to_vmx(vcpu);
5117
5118         if (is_guest_mode(vcpu))
5119                 return;
5120
5121         if (!cpu_has_virtual_nmis()) {
5122                 /*
5123                  * Tracking the NMI-blocked state in software is built upon
5124                  * finding the next open IRQ window. This, in turn, depends on
5125                  * well-behaving guests: They have to keep IRQs disabled at
5126                  * least as long as the NMI handler runs. Otherwise we may
5127                  * cause NMI nesting, maybe breaking the guest. But as this is
5128                  * highly unlikely, we can live with the residual risk.
5129                  */
5130                 vmx->soft_vnmi_blocked = 1;
5131                 vmx->vnmi_blocked_time = 0;
5132         }
5133
5134         ++vcpu->stat.nmi_injections;
5135         vmx->nmi_known_unmasked = false;
5136         if (vmx->rmode.vm86_active) {
5137                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5138                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5139                 return;
5140         }
5141         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5142                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5143 }
5144
5145 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5146 {
5147         if (!cpu_has_virtual_nmis())
5148                 return to_vmx(vcpu)->soft_vnmi_blocked;
5149         if (to_vmx(vcpu)->nmi_known_unmasked)
5150                 return false;
5151         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5152 }
5153
5154 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5155 {
5156         struct vcpu_vmx *vmx = to_vmx(vcpu);
5157
5158         if (!cpu_has_virtual_nmis()) {
5159                 if (vmx->soft_vnmi_blocked != masked) {
5160                         vmx->soft_vnmi_blocked = masked;
5161                         vmx->vnmi_blocked_time = 0;
5162                 }
5163         } else {
5164                 vmx->nmi_known_unmasked = !masked;
5165                 if (masked)
5166                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5167                                       GUEST_INTR_STATE_NMI);
5168                 else
5169                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5170                                         GUEST_INTR_STATE_NMI);
5171         }
5172 }
5173
5174 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5175 {
5176         if (to_vmx(vcpu)->nested.nested_run_pending)
5177                 return 0;
5178
5179         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5180                 return 0;
5181
5182         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5183                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5184                    | GUEST_INTR_STATE_NMI));
5185 }
5186
5187 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5188 {
5189         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5190                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5191                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5192                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5193 }
5194
5195 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5196 {
5197         int ret;
5198
5199         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5200                                     PAGE_SIZE * 3);
5201         if (ret)
5202                 return ret;
5203         kvm->arch.tss_addr = addr;
5204         return init_rmode_tss(kvm);
5205 }
5206
5207 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5208 {
5209         switch (vec) {
5210         case BP_VECTOR:
5211                 /*
5212                  * Update instruction length as we may reinject the exception
5213                  * from user space while in guest debugging mode.
5214                  */
5215                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5216                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5217                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5218                         return false;
5219                 /* fall through */
5220         case DB_VECTOR:
5221                 if (vcpu->guest_debug &
5222                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5223                         return false;
5224                 /* fall through */
5225         case DE_VECTOR:
5226         case OF_VECTOR:
5227         case BR_VECTOR:
5228         case UD_VECTOR:
5229         case DF_VECTOR:
5230         case SS_VECTOR:
5231         case GP_VECTOR:
5232         case MF_VECTOR:
5233                 return true;
5234         break;
5235         }
5236         return false;
5237 }
5238
5239 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5240                                   int vec, u32 err_code)
5241 {
5242         /*
5243          * Instruction with address size override prefix opcode 0x67
5244          * Cause the #SS fault with 0 error code in VM86 mode.
5245          */
5246         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5247                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5248                         if (vcpu->arch.halt_request) {
5249                                 vcpu->arch.halt_request = 0;
5250                                 return kvm_vcpu_halt(vcpu);
5251                         }
5252                         return 1;
5253                 }
5254                 return 0;
5255         }
5256
5257         /*
5258          * Forward all other exceptions that are valid in real mode.
5259          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5260          *        the required debugging infrastructure rework.
5261          */
5262         kvm_queue_exception(vcpu, vec);
5263         return 1;
5264 }
5265
5266 /*
5267  * Trigger machine check on the host. We assume all the MSRs are already set up
5268  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5269  * We pass a fake environment to the machine check handler because we want
5270  * the guest to be always treated like user space, no matter what context
5271  * it used internally.
5272  */
5273 static void kvm_machine_check(void)
5274 {
5275 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5276         struct pt_regs regs = {
5277                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5278                 .flags = X86_EFLAGS_IF,
5279         };
5280
5281         do_machine_check(&regs, 0);
5282 #endif
5283 }
5284
5285 static int handle_machine_check(struct kvm_vcpu *vcpu)
5286 {
5287         /* already handled by vcpu_run */
5288         return 1;
5289 }
5290
5291 static int handle_exception(struct kvm_vcpu *vcpu)
5292 {
5293         struct vcpu_vmx *vmx = to_vmx(vcpu);
5294         struct kvm_run *kvm_run = vcpu->run;
5295         u32 intr_info, ex_no, error_code;
5296         unsigned long cr2, rip, dr6;
5297         u32 vect_info;
5298         enum emulation_result er;
5299
5300         vect_info = vmx->idt_vectoring_info;
5301         intr_info = vmx->exit_intr_info;
5302
5303         if (is_machine_check(intr_info))
5304                 return handle_machine_check(vcpu);
5305
5306         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5307                 return 1;  /* already handled by vmx_vcpu_run() */
5308
5309         if (is_no_device(intr_info)) {
5310                 vmx_fpu_activate(vcpu);
5311                 return 1;
5312         }
5313
5314         if (is_invalid_opcode(intr_info)) {
5315                 if (is_guest_mode(vcpu)) {
5316                         kvm_queue_exception(vcpu, UD_VECTOR);
5317                         return 1;
5318                 }
5319                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5320                 if (er != EMULATE_DONE)
5321                         kvm_queue_exception(vcpu, UD_VECTOR);
5322                 return 1;
5323         }
5324
5325         error_code = 0;
5326         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5327                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5328
5329         /*
5330          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5331          * MMIO, it is better to report an internal error.
5332          * See the comments in vmx_handle_exit.
5333          */
5334         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5335             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5336                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5337                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5338                 vcpu->run->internal.ndata = 3;
5339                 vcpu->run->internal.data[0] = vect_info;
5340                 vcpu->run->internal.data[1] = intr_info;
5341                 vcpu->run->internal.data[2] = error_code;
5342                 return 0;
5343         }
5344
5345         if (is_page_fault(intr_info)) {
5346                 /* EPT won't cause page fault directly */
5347                 BUG_ON(enable_ept);
5348                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5349                 trace_kvm_page_fault(cr2, error_code);
5350
5351                 if (kvm_event_needs_reinjection(vcpu))
5352                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5353                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5354         }
5355
5356         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5357
5358         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5359                 return handle_rmode_exception(vcpu, ex_no, error_code);
5360
5361         switch (ex_no) {
5362         case AC_VECTOR:
5363                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5364                 return 1;
5365         case DB_VECTOR:
5366                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5367                 if (!(vcpu->guest_debug &
5368                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5369                         vcpu->arch.dr6 &= ~15;
5370                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5371                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5372                                 skip_emulated_instruction(vcpu);
5373
5374                         kvm_queue_exception(vcpu, DB_VECTOR);
5375                         return 1;
5376                 }
5377                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5378                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5379                 /* fall through */
5380         case BP_VECTOR:
5381                 /*
5382                  * Update instruction length as we may reinject #BP from
5383                  * user space while in guest debugging mode. Reading it for
5384                  * #DB as well causes no harm, it is not used in that case.
5385                  */
5386                 vmx->vcpu.arch.event_exit_inst_len =
5387                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5388                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5389                 rip = kvm_rip_read(vcpu);
5390                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5391                 kvm_run->debug.arch.exception = ex_no;
5392                 break;
5393         default:
5394                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5395                 kvm_run->ex.exception = ex_no;
5396                 kvm_run->ex.error_code = error_code;
5397                 break;
5398         }
5399         return 0;
5400 }
5401
5402 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5403 {
5404         ++vcpu->stat.irq_exits;
5405         return 1;
5406 }
5407
5408 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5409 {
5410         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5411         return 0;
5412 }
5413
5414 static int handle_io(struct kvm_vcpu *vcpu)
5415 {
5416         unsigned long exit_qualification;
5417         int size, in, string;
5418         unsigned port;
5419
5420         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5421         string = (exit_qualification & 16) != 0;
5422         in = (exit_qualification & 8) != 0;
5423
5424         ++vcpu->stat.io_exits;
5425
5426         if (string || in)
5427                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5428
5429         port = exit_qualification >> 16;
5430         size = (exit_qualification & 7) + 1;
5431         skip_emulated_instruction(vcpu);
5432
5433         return kvm_fast_pio_out(vcpu, size, port);
5434 }
5435
5436 static void
5437 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5438 {
5439         /*
5440          * Patch in the VMCALL instruction:
5441          */
5442         hypercall[0] = 0x0f;
5443         hypercall[1] = 0x01;
5444         hypercall[2] = 0xc1;
5445 }
5446
5447 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5448 {
5449         unsigned long always_on = VMXON_CR0_ALWAYSON;
5450         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5451
5452         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5453                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5454             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5455                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5456         return (val & always_on) == always_on;
5457 }
5458
5459 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5460 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5461 {
5462         if (is_guest_mode(vcpu)) {
5463                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5464                 unsigned long orig_val = val;
5465
5466                 /*
5467                  * We get here when L2 changed cr0 in a way that did not change
5468                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5469                  * but did change L0 shadowed bits. So we first calculate the
5470                  * effective cr0 value that L1 would like to write into the
5471                  * hardware. It consists of the L2-owned bits from the new
5472                  * value combined with the L1-owned bits from L1's guest_cr0.
5473                  */
5474                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5475                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5476
5477                 if (!nested_cr0_valid(vcpu, val))
5478                         return 1;
5479
5480                 if (kvm_set_cr0(vcpu, val))
5481                         return 1;
5482                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5483                 return 0;
5484         } else {
5485                 if (to_vmx(vcpu)->nested.vmxon &&
5486                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5487                         return 1;
5488                 return kvm_set_cr0(vcpu, val);
5489         }
5490 }
5491
5492 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5493 {
5494         if (is_guest_mode(vcpu)) {
5495                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5496                 unsigned long orig_val = val;
5497
5498                 /* analogously to handle_set_cr0 */
5499                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5500                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5501                 if (kvm_set_cr4(vcpu, val))
5502                         return 1;
5503                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5504                 return 0;
5505         } else
5506                 return kvm_set_cr4(vcpu, val);
5507 }
5508
5509 /* called to set cr0 as approriate for clts instruction exit. */
5510 static void handle_clts(struct kvm_vcpu *vcpu)
5511 {
5512         if (is_guest_mode(vcpu)) {
5513                 /*
5514                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5515                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5516                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5517                  */
5518                 vmcs_writel(CR0_READ_SHADOW,
5519                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5520                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5521         } else
5522                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5523 }
5524
5525 static int handle_cr(struct kvm_vcpu *vcpu)
5526 {
5527         unsigned long exit_qualification, val;
5528         int cr;
5529         int reg;
5530         int err;
5531
5532         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5533         cr = exit_qualification & 15;
5534         reg = (exit_qualification >> 8) & 15;
5535         switch ((exit_qualification >> 4) & 3) {
5536         case 0: /* mov to cr */
5537                 val = kvm_register_readl(vcpu, reg);
5538                 trace_kvm_cr_write(cr, val);
5539                 switch (cr) {
5540                 case 0:
5541                         err = handle_set_cr0(vcpu, val);
5542                         kvm_complete_insn_gp(vcpu, err);
5543                         return 1;
5544                 case 3:
5545                         err = kvm_set_cr3(vcpu, val);
5546                         kvm_complete_insn_gp(vcpu, err);
5547                         return 1;
5548                 case 4:
5549                         err = handle_set_cr4(vcpu, val);
5550                         kvm_complete_insn_gp(vcpu, err);
5551                         return 1;
5552                 case 8: {
5553                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5554                                 u8 cr8 = (u8)val;
5555                                 err = kvm_set_cr8(vcpu, cr8);
5556                                 kvm_complete_insn_gp(vcpu, err);
5557                                 if (lapic_in_kernel(vcpu))
5558                                         return 1;
5559                                 if (cr8_prev <= cr8)
5560                                         return 1;
5561                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5562                                 return 0;
5563                         }
5564                 }
5565                 break;
5566         case 2: /* clts */
5567                 handle_clts(vcpu);
5568                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5569                 skip_emulated_instruction(vcpu);
5570                 vmx_fpu_activate(vcpu);
5571                 return 1;
5572         case 1: /*mov from cr*/
5573                 switch (cr) {
5574                 case 3:
5575                         val = kvm_read_cr3(vcpu);
5576                         kvm_register_write(vcpu, reg, val);
5577                         trace_kvm_cr_read(cr, val);
5578                         skip_emulated_instruction(vcpu);
5579                         return 1;
5580                 case 8:
5581                         val = kvm_get_cr8(vcpu);
5582                         kvm_register_write(vcpu, reg, val);
5583                         trace_kvm_cr_read(cr, val);
5584                         skip_emulated_instruction(vcpu);
5585                         return 1;
5586                 }
5587                 break;
5588         case 3: /* lmsw */
5589                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5590                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5591                 kvm_lmsw(vcpu, val);
5592
5593                 skip_emulated_instruction(vcpu);
5594                 return 1;
5595         default:
5596                 break;
5597         }
5598         vcpu->run->exit_reason = 0;
5599         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5600                (int)(exit_qualification >> 4) & 3, cr);
5601         return 0;
5602 }
5603
5604 static int handle_dr(struct kvm_vcpu *vcpu)
5605 {
5606         unsigned long exit_qualification;
5607         int dr, dr7, reg;
5608
5609         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5610         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5611
5612         /* First, if DR does not exist, trigger UD */
5613         if (!kvm_require_dr(vcpu, dr))
5614                 return 1;
5615
5616         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5617         if (!kvm_require_cpl(vcpu, 0))
5618                 return 1;
5619         dr7 = vmcs_readl(GUEST_DR7);
5620         if (dr7 & DR7_GD) {
5621                 /*
5622                  * As the vm-exit takes precedence over the debug trap, we
5623                  * need to emulate the latter, either for the host or the
5624                  * guest debugging itself.
5625                  */
5626                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5627                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5628                         vcpu->run->debug.arch.dr7 = dr7;
5629                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5630                         vcpu->run->debug.arch.exception = DB_VECTOR;
5631                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5632                         return 0;
5633                 } else {
5634                         vcpu->arch.dr6 &= ~15;
5635                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5636                         kvm_queue_exception(vcpu, DB_VECTOR);
5637                         return 1;
5638                 }
5639         }
5640
5641         if (vcpu->guest_debug == 0) {
5642                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5643                                 CPU_BASED_MOV_DR_EXITING);
5644
5645                 /*
5646                  * No more DR vmexits; force a reload of the debug registers
5647                  * and reenter on this instruction.  The next vmexit will
5648                  * retrieve the full state of the debug registers.
5649                  */
5650                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5651                 return 1;
5652         }
5653
5654         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5655         if (exit_qualification & TYPE_MOV_FROM_DR) {
5656                 unsigned long val;
5657
5658                 if (kvm_get_dr(vcpu, dr, &val))
5659                         return 1;
5660                 kvm_register_write(vcpu, reg, val);
5661         } else
5662                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5663                         return 1;
5664
5665         skip_emulated_instruction(vcpu);
5666         return 1;
5667 }
5668
5669 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5670 {
5671         return vcpu->arch.dr6;
5672 }
5673
5674 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5675 {
5676 }
5677
5678 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5679 {
5680         get_debugreg(vcpu->arch.db[0], 0);
5681         get_debugreg(vcpu->arch.db[1], 1);
5682         get_debugreg(vcpu->arch.db[2], 2);
5683         get_debugreg(vcpu->arch.db[3], 3);
5684         get_debugreg(vcpu->arch.dr6, 6);
5685         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5686
5687         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5688         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5689 }
5690
5691 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5692 {
5693         vmcs_writel(GUEST_DR7, val);
5694 }
5695
5696 static int handle_cpuid(struct kvm_vcpu *vcpu)
5697 {
5698         kvm_emulate_cpuid(vcpu);
5699         return 1;
5700 }
5701
5702 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5703 {
5704         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5705         struct msr_data msr_info;
5706
5707         msr_info.index = ecx;
5708         msr_info.host_initiated = false;
5709         if (vmx_get_msr(vcpu, &msr_info)) {
5710                 trace_kvm_msr_read_ex(ecx);
5711                 kvm_inject_gp(vcpu, 0);
5712                 return 1;
5713         }
5714
5715         trace_kvm_msr_read(ecx, msr_info.data);
5716
5717         /* FIXME: handling of bits 32:63 of rax, rdx */
5718         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5719         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5720         skip_emulated_instruction(vcpu);
5721         return 1;
5722 }
5723
5724 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5725 {
5726         struct msr_data msr;
5727         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5728         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5729                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5730
5731         msr.data = data;
5732         msr.index = ecx;
5733         msr.host_initiated = false;
5734         if (kvm_set_msr(vcpu, &msr) != 0) {
5735                 trace_kvm_msr_write_ex(ecx, data);
5736                 kvm_inject_gp(vcpu, 0);
5737                 return 1;
5738         }
5739
5740         trace_kvm_msr_write(ecx, data);
5741         skip_emulated_instruction(vcpu);
5742         return 1;
5743 }
5744
5745 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5746 {
5747         kvm_make_request(KVM_REQ_EVENT, vcpu);
5748         return 1;
5749 }
5750
5751 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5752 {
5753         u32 cpu_based_vm_exec_control;
5754
5755         /* clear pending irq */
5756         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5757         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5758         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5759
5760         kvm_make_request(KVM_REQ_EVENT, vcpu);
5761
5762         ++vcpu->stat.irq_window_exits;
5763         return 1;
5764 }
5765
5766 static int handle_halt(struct kvm_vcpu *vcpu)
5767 {
5768         return kvm_emulate_halt(vcpu);
5769 }
5770
5771 static int handle_vmcall(struct kvm_vcpu *vcpu)
5772 {
5773         return kvm_emulate_hypercall(vcpu);
5774 }
5775
5776 static int handle_invd(struct kvm_vcpu *vcpu)
5777 {
5778         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5779 }
5780
5781 static int handle_invlpg(struct kvm_vcpu *vcpu)
5782 {
5783         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5784
5785         kvm_mmu_invlpg(vcpu, exit_qualification);
5786         skip_emulated_instruction(vcpu);
5787         return 1;
5788 }
5789
5790 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5791 {
5792         int err;
5793
5794         err = kvm_rdpmc(vcpu);
5795         kvm_complete_insn_gp(vcpu, err);
5796
5797         return 1;
5798 }
5799
5800 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5801 {
5802         kvm_emulate_wbinvd(vcpu);
5803         return 1;
5804 }
5805
5806 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5807 {
5808         u64 new_bv = kvm_read_edx_eax(vcpu);
5809         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5810
5811         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5812                 skip_emulated_instruction(vcpu);
5813         return 1;
5814 }
5815
5816 static int handle_xsaves(struct kvm_vcpu *vcpu)
5817 {
5818         skip_emulated_instruction(vcpu);
5819         WARN(1, "this should never happen\n");
5820         return 1;
5821 }
5822
5823 static int handle_xrstors(struct kvm_vcpu *vcpu)
5824 {
5825         skip_emulated_instruction(vcpu);
5826         WARN(1, "this should never happen\n");
5827         return 1;
5828 }
5829
5830 static int handle_apic_access(struct kvm_vcpu *vcpu)
5831 {
5832         if (likely(fasteoi)) {
5833                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5834                 int access_type, offset;
5835
5836                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5837                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5838                 /*
5839                  * Sane guest uses MOV to write EOI, with written value
5840                  * not cared. So make a short-circuit here by avoiding
5841                  * heavy instruction emulation.
5842                  */
5843                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5844                     (offset == APIC_EOI)) {
5845                         kvm_lapic_set_eoi(vcpu);
5846                         skip_emulated_instruction(vcpu);
5847                         return 1;
5848                 }
5849         }
5850         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5851 }
5852
5853 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5854 {
5855         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5856         int vector = exit_qualification & 0xff;
5857
5858         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5859         kvm_apic_set_eoi_accelerated(vcpu, vector);
5860         return 1;
5861 }
5862
5863 static int handle_apic_write(struct kvm_vcpu *vcpu)
5864 {
5865         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5866         u32 offset = exit_qualification & 0xfff;
5867
5868         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5869         kvm_apic_write_nodecode(vcpu, offset);
5870         return 1;
5871 }
5872
5873 static int handle_task_switch(struct kvm_vcpu *vcpu)
5874 {
5875         struct vcpu_vmx *vmx = to_vmx(vcpu);
5876         unsigned long exit_qualification;
5877         bool has_error_code = false;
5878         u32 error_code = 0;
5879         u16 tss_selector;
5880         int reason, type, idt_v, idt_index;
5881
5882         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5883         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5884         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5885
5886         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5887
5888         reason = (u32)exit_qualification >> 30;
5889         if (reason == TASK_SWITCH_GATE && idt_v) {
5890                 switch (type) {
5891                 case INTR_TYPE_NMI_INTR:
5892                         vcpu->arch.nmi_injected = false;
5893                         vmx_set_nmi_mask(vcpu, true);
5894                         break;
5895                 case INTR_TYPE_EXT_INTR:
5896                 case INTR_TYPE_SOFT_INTR:
5897                         kvm_clear_interrupt_queue(vcpu);
5898                         break;
5899                 case INTR_TYPE_HARD_EXCEPTION:
5900                         if (vmx->idt_vectoring_info &
5901                             VECTORING_INFO_DELIVER_CODE_MASK) {
5902                                 has_error_code = true;
5903                                 error_code =
5904                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5905                         }
5906                         /* fall through */
5907                 case INTR_TYPE_SOFT_EXCEPTION:
5908                         kvm_clear_exception_queue(vcpu);
5909                         break;
5910                 default:
5911                         break;
5912                 }
5913         }
5914         tss_selector = exit_qualification;
5915
5916         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5917                        type != INTR_TYPE_EXT_INTR &&
5918                        type != INTR_TYPE_NMI_INTR))
5919                 skip_emulated_instruction(vcpu);
5920
5921         if (kvm_task_switch(vcpu, tss_selector,
5922                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5923                             has_error_code, error_code) == EMULATE_FAIL) {
5924                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5925                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5926                 vcpu->run->internal.ndata = 0;
5927                 return 0;
5928         }
5929
5930         /*
5931          * TODO: What about debug traps on tss switch?
5932          *       Are we supposed to inject them and update dr6?
5933          */
5934
5935         return 1;
5936 }
5937
5938 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5939 {
5940         unsigned long exit_qualification;
5941         gpa_t gpa;
5942         u32 error_code;
5943         int gla_validity;
5944
5945         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5946
5947         gla_validity = (exit_qualification >> 7) & 0x3;
5948         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5949                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5950                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5951                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5952                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5953                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5954                         (long unsigned int)exit_qualification);
5955                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5956                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5957                 return 0;
5958         }
5959
5960         /*
5961          * EPT violation happened while executing iret from NMI,
5962          * "blocked by NMI" bit has to be set before next VM entry.
5963          * There are errata that may cause this bit to not be set:
5964          * AAK134, BY25.
5965          */
5966         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5967                         cpu_has_virtual_nmis() &&
5968                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5969                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5970
5971         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5972         trace_kvm_page_fault(gpa, exit_qualification);
5973
5974         /* It is a write fault? */
5975         error_code = exit_qualification & PFERR_WRITE_MASK;
5976         /* It is a fetch fault? */
5977         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5978         /* ept page table is present? */
5979         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5980
5981         vcpu->arch.exit_qualification = exit_qualification;
5982
5983         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5984 }
5985
5986 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5987 {
5988         int ret;
5989         gpa_t gpa;
5990
5991         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5992         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5993                 skip_emulated_instruction(vcpu);
5994                 trace_kvm_fast_mmio(gpa);
5995                 return 1;
5996         }
5997
5998         ret = handle_mmio_page_fault(vcpu, gpa, true);
5999         if (likely(ret == RET_MMIO_PF_EMULATE))
6000                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6001                                               EMULATE_DONE;
6002
6003         if (unlikely(ret == RET_MMIO_PF_INVALID))
6004                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6005
6006         if (unlikely(ret == RET_MMIO_PF_RETRY))
6007                 return 1;
6008
6009         /* It is the real ept misconfig */
6010         WARN_ON(1);
6011
6012         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6013         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6014
6015         return 0;
6016 }
6017
6018 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6019 {
6020         u32 cpu_based_vm_exec_control;
6021
6022         /* clear pending NMI */
6023         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6024         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6025         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6026         ++vcpu->stat.nmi_window_exits;
6027         kvm_make_request(KVM_REQ_EVENT, vcpu);
6028
6029         return 1;
6030 }
6031
6032 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6033 {
6034         struct vcpu_vmx *vmx = to_vmx(vcpu);
6035         enum emulation_result err = EMULATE_DONE;
6036         int ret = 1;
6037         u32 cpu_exec_ctrl;
6038         bool intr_window_requested;
6039         unsigned count = 130;
6040
6041         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6042         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6043
6044         while (vmx->emulation_required && count-- != 0) {
6045                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6046                         return handle_interrupt_window(&vmx->vcpu);
6047
6048                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6049                         return 1;
6050
6051                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6052
6053                 if (err == EMULATE_USER_EXIT) {
6054                         ++vcpu->stat.mmio_exits;
6055                         ret = 0;
6056                         goto out;
6057                 }
6058
6059                 if (err != EMULATE_DONE) {
6060                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6061                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6062                         vcpu->run->internal.ndata = 0;
6063                         return 0;
6064                 }
6065
6066                 if (vcpu->arch.halt_request) {
6067                         vcpu->arch.halt_request = 0;
6068                         ret = kvm_vcpu_halt(vcpu);
6069                         goto out;
6070                 }
6071
6072                 if (signal_pending(current))
6073                         goto out;
6074                 if (need_resched())
6075                         schedule();
6076         }
6077
6078 out:
6079         return ret;
6080 }
6081
6082 static int __grow_ple_window(int val)
6083 {
6084         if (ple_window_grow < 1)
6085                 return ple_window;
6086
6087         val = min(val, ple_window_actual_max);
6088
6089         if (ple_window_grow < ple_window)
6090                 val *= ple_window_grow;
6091         else
6092                 val += ple_window_grow;
6093
6094         return val;
6095 }
6096
6097 static int __shrink_ple_window(int val, int modifier, int minimum)
6098 {
6099         if (modifier < 1)
6100                 return ple_window;
6101
6102         if (modifier < ple_window)
6103                 val /= modifier;
6104         else
6105                 val -= modifier;
6106
6107         return max(val, minimum);
6108 }
6109
6110 static void grow_ple_window(struct kvm_vcpu *vcpu)
6111 {
6112         struct vcpu_vmx *vmx = to_vmx(vcpu);
6113         int old = vmx->ple_window;
6114
6115         vmx->ple_window = __grow_ple_window(old);
6116
6117         if (vmx->ple_window != old)
6118                 vmx->ple_window_dirty = true;
6119
6120         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6121 }
6122
6123 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6124 {
6125         struct vcpu_vmx *vmx = to_vmx(vcpu);
6126         int old = vmx->ple_window;
6127
6128         vmx->ple_window = __shrink_ple_window(old,
6129                                               ple_window_shrink, ple_window);
6130
6131         if (vmx->ple_window != old)
6132                 vmx->ple_window_dirty = true;
6133
6134         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6135 }
6136
6137 /*
6138  * ple_window_actual_max is computed to be one grow_ple_window() below
6139  * ple_window_max. (See __grow_ple_window for the reason.)
6140  * This prevents overflows, because ple_window_max is int.
6141  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6142  * this process.
6143  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6144  */
6145 static void update_ple_window_actual_max(void)
6146 {
6147         ple_window_actual_max =
6148                         __shrink_ple_window(max(ple_window_max, ple_window),
6149                                             ple_window_grow, INT_MIN);
6150 }
6151
6152 /*
6153  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6154  */
6155 static void wakeup_handler(void)
6156 {
6157         struct kvm_vcpu *vcpu;
6158         int cpu = smp_processor_id();
6159
6160         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6161         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6162                         blocked_vcpu_list) {
6163                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6164
6165                 if (pi_test_on(pi_desc) == 1)
6166                         kvm_vcpu_kick(vcpu);
6167         }
6168         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6169 }
6170
6171 static __init int hardware_setup(void)
6172 {
6173         int r = -ENOMEM, i, msr;
6174
6175         rdmsrl_safe(MSR_EFER, &host_efer);
6176
6177         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6178                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6179
6180         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6181         if (!vmx_io_bitmap_a)
6182                 return r;
6183
6184         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6185         if (!vmx_io_bitmap_b)
6186                 goto out;
6187
6188         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6189         if (!vmx_msr_bitmap_legacy)
6190                 goto out1;
6191
6192         vmx_msr_bitmap_legacy_x2apic =
6193                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6194         if (!vmx_msr_bitmap_legacy_x2apic)
6195                 goto out2;
6196
6197         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6198         if (!vmx_msr_bitmap_longmode)
6199                 goto out3;
6200
6201         vmx_msr_bitmap_longmode_x2apic =
6202                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6203         if (!vmx_msr_bitmap_longmode_x2apic)
6204                 goto out4;
6205
6206         if (nested) {
6207                 vmx_msr_bitmap_nested =
6208                         (unsigned long *)__get_free_page(GFP_KERNEL);
6209                 if (!vmx_msr_bitmap_nested)
6210                         goto out5;
6211         }
6212
6213         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6214         if (!vmx_vmread_bitmap)
6215                 goto out6;
6216
6217         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6218         if (!vmx_vmwrite_bitmap)
6219                 goto out7;
6220
6221         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6222         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6223
6224         /*
6225          * Allow direct access to the PC debug port (it is often used for I/O
6226          * delays, but the vmexits simply slow things down).
6227          */
6228         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6229         clear_bit(0x80, vmx_io_bitmap_a);
6230
6231         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6232
6233         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6234         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6235         if (nested)
6236                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6237
6238         if (setup_vmcs_config(&vmcs_config) < 0) {
6239                 r = -EIO;
6240                 goto out8;
6241         }
6242
6243         if (boot_cpu_has(X86_FEATURE_NX))
6244                 kvm_enable_efer_bits(EFER_NX);
6245
6246         if (!cpu_has_vmx_vpid())
6247                 enable_vpid = 0;
6248         if (!cpu_has_vmx_shadow_vmcs())
6249                 enable_shadow_vmcs = 0;
6250         if (enable_shadow_vmcs)
6251                 init_vmcs_shadow_fields();
6252
6253         if (!cpu_has_vmx_ept() ||
6254             !cpu_has_vmx_ept_4levels()) {
6255                 enable_ept = 0;
6256                 enable_unrestricted_guest = 0;
6257                 enable_ept_ad_bits = 0;
6258         }
6259
6260         if (!cpu_has_vmx_ept_ad_bits())
6261                 enable_ept_ad_bits = 0;
6262
6263         if (!cpu_has_vmx_unrestricted_guest())
6264                 enable_unrestricted_guest = 0;
6265
6266         if (!cpu_has_vmx_flexpriority())
6267                 flexpriority_enabled = 0;
6268
6269         /*
6270          * set_apic_access_page_addr() is used to reload apic access
6271          * page upon invalidation.  No need to do anything if not
6272          * using the APIC_ACCESS_ADDR VMCS field.
6273          */
6274         if (!flexpriority_enabled)
6275                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6276
6277         if (!cpu_has_vmx_tpr_shadow())
6278                 kvm_x86_ops->update_cr8_intercept = NULL;
6279
6280         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6281                 kvm_disable_largepages();
6282
6283         if (!cpu_has_vmx_ple())
6284                 ple_gap = 0;
6285
6286         if (!cpu_has_vmx_apicv())
6287                 enable_apicv = 0;
6288
6289         if (cpu_has_vmx_tsc_scaling()) {
6290                 kvm_has_tsc_control = true;
6291                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6292                 kvm_tsc_scaling_ratio_frac_bits = 48;
6293         }
6294
6295         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6296         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6297         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6298         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6299         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6300         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6301         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6302
6303         memcpy(vmx_msr_bitmap_legacy_x2apic,
6304                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6305         memcpy(vmx_msr_bitmap_longmode_x2apic,
6306                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6307
6308         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6309
6310         if (enable_apicv) {
6311                 for (msr = 0x800; msr <= 0x8ff; msr++)
6312                         vmx_disable_intercept_msr_read_x2apic(msr);
6313
6314                 /* According SDM, in x2apic mode, the whole id reg is used.
6315                  * But in KVM, it only use the highest eight bits. Need to
6316                  * intercept it */
6317                 vmx_enable_intercept_msr_read_x2apic(0x802);
6318                 /* TMCCT */
6319                 vmx_enable_intercept_msr_read_x2apic(0x839);
6320                 /* TPR */
6321                 vmx_disable_intercept_msr_write_x2apic(0x808);
6322                 /* EOI */
6323                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6324                 /* SELF-IPI */
6325                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6326         }
6327
6328         if (enable_ept) {
6329                 kvm_mmu_set_mask_ptes(0ull,
6330                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6331                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6332                         0ull, VMX_EPT_EXECUTABLE_MASK);
6333                 ept_set_mmio_spte_mask();
6334                 kvm_enable_tdp();
6335         } else
6336                 kvm_disable_tdp();
6337
6338         update_ple_window_actual_max();
6339
6340         /*
6341          * Only enable PML when hardware supports PML feature, and both EPT
6342          * and EPT A/D bit features are enabled -- PML depends on them to work.
6343          */
6344         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6345                 enable_pml = 0;
6346
6347         if (!enable_pml) {
6348                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6349                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6350                 kvm_x86_ops->flush_log_dirty = NULL;
6351                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6352         }
6353
6354         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6355
6356         return alloc_kvm_area();
6357
6358 out8:
6359         free_page((unsigned long)vmx_vmwrite_bitmap);
6360 out7:
6361         free_page((unsigned long)vmx_vmread_bitmap);
6362 out6:
6363         if (nested)
6364                 free_page((unsigned long)vmx_msr_bitmap_nested);
6365 out5:
6366         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6367 out4:
6368         free_page((unsigned long)vmx_msr_bitmap_longmode);
6369 out3:
6370         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6371 out2:
6372         free_page((unsigned long)vmx_msr_bitmap_legacy);
6373 out1:
6374         free_page((unsigned long)vmx_io_bitmap_b);
6375 out:
6376         free_page((unsigned long)vmx_io_bitmap_a);
6377
6378     return r;
6379 }
6380
6381 static __exit void hardware_unsetup(void)
6382 {
6383         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6384         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6385         free_page((unsigned long)vmx_msr_bitmap_legacy);
6386         free_page((unsigned long)vmx_msr_bitmap_longmode);
6387         free_page((unsigned long)vmx_io_bitmap_b);
6388         free_page((unsigned long)vmx_io_bitmap_a);
6389         free_page((unsigned long)vmx_vmwrite_bitmap);
6390         free_page((unsigned long)vmx_vmread_bitmap);
6391         if (nested)
6392                 free_page((unsigned long)vmx_msr_bitmap_nested);
6393
6394         free_kvm_area();
6395 }
6396
6397 /*
6398  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6399  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6400  */
6401 static int handle_pause(struct kvm_vcpu *vcpu)
6402 {
6403         if (ple_gap)
6404                 grow_ple_window(vcpu);
6405
6406         skip_emulated_instruction(vcpu);
6407         kvm_vcpu_on_spin(vcpu);
6408
6409         return 1;
6410 }
6411
6412 static int handle_nop(struct kvm_vcpu *vcpu)
6413 {
6414         skip_emulated_instruction(vcpu);
6415         return 1;
6416 }
6417
6418 static int handle_mwait(struct kvm_vcpu *vcpu)
6419 {
6420         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6421         return handle_nop(vcpu);
6422 }
6423
6424 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6425 {
6426         return 1;
6427 }
6428
6429 static int handle_monitor(struct kvm_vcpu *vcpu)
6430 {
6431         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6432         return handle_nop(vcpu);
6433 }
6434
6435 /*
6436  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6437  * We could reuse a single VMCS for all the L2 guests, but we also want the
6438  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6439  * allows keeping them loaded on the processor, and in the future will allow
6440  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6441  * every entry if they never change.
6442  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6443  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6444  *
6445  * The following functions allocate and free a vmcs02 in this pool.
6446  */
6447
6448 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6449 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6450 {
6451         struct vmcs02_list *item;
6452         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6453                 if (item->vmptr == vmx->nested.current_vmptr) {
6454                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6455                         return &item->vmcs02;
6456                 }
6457
6458         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6459                 /* Recycle the least recently used VMCS. */
6460                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6461                                        struct vmcs02_list, list);
6462                 item->vmptr = vmx->nested.current_vmptr;
6463                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6464                 return &item->vmcs02;
6465         }
6466
6467         /* Create a new VMCS */
6468         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6469         if (!item)
6470                 return NULL;
6471         item->vmcs02.vmcs = alloc_vmcs();
6472         if (!item->vmcs02.vmcs) {
6473                 kfree(item);
6474                 return NULL;
6475         }
6476         loaded_vmcs_init(&item->vmcs02);
6477         item->vmptr = vmx->nested.current_vmptr;
6478         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6479         vmx->nested.vmcs02_num++;
6480         return &item->vmcs02;
6481 }
6482
6483 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6484 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6485 {
6486         struct vmcs02_list *item;
6487         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6488                 if (item->vmptr == vmptr) {
6489                         free_loaded_vmcs(&item->vmcs02);
6490                         list_del(&item->list);
6491                         kfree(item);
6492                         vmx->nested.vmcs02_num--;
6493                         return;
6494                 }
6495 }
6496
6497 /*
6498  * Free all VMCSs saved for this vcpu, except the one pointed by
6499  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6500  * must be &vmx->vmcs01.
6501  */
6502 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6503 {
6504         struct vmcs02_list *item, *n;
6505
6506         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6507         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6508                 /*
6509                  * Something will leak if the above WARN triggers.  Better than
6510                  * a use-after-free.
6511                  */
6512                 if (vmx->loaded_vmcs == &item->vmcs02)
6513                         continue;
6514
6515                 free_loaded_vmcs(&item->vmcs02);
6516                 list_del(&item->list);
6517                 kfree(item);
6518                 vmx->nested.vmcs02_num--;
6519         }
6520 }
6521
6522 /*
6523  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6524  * set the success or error code of an emulated VMX instruction, as specified
6525  * by Vol 2B, VMX Instruction Reference, "Conventions".
6526  */
6527 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6528 {
6529         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6530                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6531                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6532 }
6533
6534 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6535 {
6536         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6537                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6538                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6539                         | X86_EFLAGS_CF);
6540 }
6541
6542 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6543                                         u32 vm_instruction_error)
6544 {
6545         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6546                 /*
6547                  * failValid writes the error number to the current VMCS, which
6548                  * can't be done there isn't a current VMCS.
6549                  */
6550                 nested_vmx_failInvalid(vcpu);
6551                 return;
6552         }
6553         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6554                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6555                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6556                         | X86_EFLAGS_ZF);
6557         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6558         /*
6559          * We don't need to force a shadow sync because
6560          * VM_INSTRUCTION_ERROR is not shadowed
6561          */
6562 }
6563
6564 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6565 {
6566         /* TODO: not to reset guest simply here. */
6567         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6568         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6569 }
6570
6571 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6572 {
6573         struct vcpu_vmx *vmx =
6574                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6575
6576         vmx->nested.preemption_timer_expired = true;
6577         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6578         kvm_vcpu_kick(&vmx->vcpu);
6579
6580         return HRTIMER_NORESTART;
6581 }
6582
6583 /*
6584  * Decode the memory-address operand of a vmx instruction, as recorded on an
6585  * exit caused by such an instruction (run by a guest hypervisor).
6586  * On success, returns 0. When the operand is invalid, returns 1 and throws
6587  * #UD or #GP.
6588  */
6589 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6590                                  unsigned long exit_qualification,
6591                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6592 {
6593         gva_t off;
6594         bool exn;
6595         struct kvm_segment s;
6596
6597         /*
6598          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6599          * Execution", on an exit, vmx_instruction_info holds most of the
6600          * addressing components of the operand. Only the displacement part
6601          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6602          * For how an actual address is calculated from all these components,
6603          * refer to Vol. 1, "Operand Addressing".
6604          */
6605         int  scaling = vmx_instruction_info & 3;
6606         int  addr_size = (vmx_instruction_info >> 7) & 7;
6607         bool is_reg = vmx_instruction_info & (1u << 10);
6608         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6609         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6610         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6611         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6612         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6613
6614         if (is_reg) {
6615                 kvm_queue_exception(vcpu, UD_VECTOR);
6616                 return 1;
6617         }
6618
6619         /* Addr = segment_base + offset */
6620         /* offset = base + [index * scale] + displacement */
6621         off = exit_qualification; /* holds the displacement */
6622         if (base_is_valid)
6623                 off += kvm_register_read(vcpu, base_reg);
6624         if (index_is_valid)
6625                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6626         vmx_get_segment(vcpu, &s, seg_reg);
6627         *ret = s.base + off;
6628
6629         if (addr_size == 1) /* 32 bit */
6630                 *ret &= 0xffffffff;
6631
6632         /* Checks for #GP/#SS exceptions. */
6633         exn = false;
6634         if (is_protmode(vcpu)) {
6635                 /* Protected mode: apply checks for segment validity in the
6636                  * following order:
6637                  * - segment type check (#GP(0) may be thrown)
6638                  * - usability check (#GP(0)/#SS(0))
6639                  * - limit check (#GP(0)/#SS(0))
6640                  */
6641                 if (wr)
6642                         /* #GP(0) if the destination operand is located in a
6643                          * read-only data segment or any code segment.
6644                          */
6645                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6646                 else
6647                         /* #GP(0) if the source operand is located in an
6648                          * execute-only code segment
6649                          */
6650                         exn = ((s.type & 0xa) == 8);
6651         }
6652         if (exn) {
6653                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6654                 return 1;
6655         }
6656         if (is_long_mode(vcpu)) {
6657                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6658                  * non-canonical form. This is an only check for long mode.
6659                  */
6660                 exn = is_noncanonical_address(*ret);
6661         } else if (is_protmode(vcpu)) {
6662                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6663                  */
6664                 exn = (s.unusable != 0);
6665                 /* Protected mode: #GP(0)/#SS(0) if the memory
6666                  * operand is outside the segment limit.
6667                  */
6668                 exn = exn || (off + sizeof(u64) > s.limit);
6669         }
6670         if (exn) {
6671                 kvm_queue_exception_e(vcpu,
6672                                       seg_reg == VCPU_SREG_SS ?
6673                                                 SS_VECTOR : GP_VECTOR,
6674                                       0);
6675                 return 1;
6676         }
6677
6678         return 0;
6679 }
6680
6681 /*
6682  * This function performs the various checks including
6683  * - if it's 4KB aligned
6684  * - No bits beyond the physical address width are set
6685  * - Returns 0 on success or else 1
6686  * (Intel SDM Section 30.3)
6687  */
6688 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6689                                   gpa_t *vmpointer)
6690 {
6691         gva_t gva;
6692         gpa_t vmptr;
6693         struct x86_exception e;
6694         struct page *page;
6695         struct vcpu_vmx *vmx = to_vmx(vcpu);
6696         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6697
6698         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6699                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6700                 return 1;
6701
6702         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6703                                 sizeof(vmptr), &e)) {
6704                 kvm_inject_page_fault(vcpu, &e);
6705                 return 1;
6706         }
6707
6708         switch (exit_reason) {
6709         case EXIT_REASON_VMON:
6710                 /*
6711                  * SDM 3: 24.11.5
6712                  * The first 4 bytes of VMXON region contain the supported
6713                  * VMCS revision identifier
6714                  *
6715                  * Note - IA32_VMX_BASIC[48] will never be 1
6716                  * for the nested case;
6717                  * which replaces physical address width with 32
6718                  *
6719                  */
6720                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6721                         nested_vmx_failInvalid(vcpu);
6722                         skip_emulated_instruction(vcpu);
6723                         return 1;
6724                 }
6725
6726                 page = nested_get_page(vcpu, vmptr);
6727                 if (page == NULL ||
6728                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6729                         nested_vmx_failInvalid(vcpu);
6730                         kunmap(page);
6731                         skip_emulated_instruction(vcpu);
6732                         return 1;
6733                 }
6734                 kunmap(page);
6735                 vmx->nested.vmxon_ptr = vmptr;
6736                 break;
6737         case EXIT_REASON_VMCLEAR:
6738                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6739                         nested_vmx_failValid(vcpu,
6740                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6741                         skip_emulated_instruction(vcpu);
6742                         return 1;
6743                 }
6744
6745                 if (vmptr == vmx->nested.vmxon_ptr) {
6746                         nested_vmx_failValid(vcpu,
6747                                              VMXERR_VMCLEAR_VMXON_POINTER);
6748                         skip_emulated_instruction(vcpu);
6749                         return 1;
6750                 }
6751                 break;
6752         case EXIT_REASON_VMPTRLD:
6753                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6754                         nested_vmx_failValid(vcpu,
6755                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6756                         skip_emulated_instruction(vcpu);
6757                         return 1;
6758                 }
6759
6760                 if (vmptr == vmx->nested.vmxon_ptr) {
6761                         nested_vmx_failValid(vcpu,
6762                                              VMXERR_VMCLEAR_VMXON_POINTER);
6763                         skip_emulated_instruction(vcpu);
6764                         return 1;
6765                 }
6766                 break;
6767         default:
6768                 return 1; /* shouldn't happen */
6769         }
6770
6771         if (vmpointer)
6772                 *vmpointer = vmptr;
6773         return 0;
6774 }
6775
6776 /*
6777  * Emulate the VMXON instruction.
6778  * Currently, we just remember that VMX is active, and do not save or even
6779  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6780  * do not currently need to store anything in that guest-allocated memory
6781  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6782  * argument is different from the VMXON pointer (which the spec says they do).
6783  */
6784 static int handle_vmon(struct kvm_vcpu *vcpu)
6785 {
6786         struct kvm_segment cs;
6787         struct vcpu_vmx *vmx = to_vmx(vcpu);
6788         struct vmcs *shadow_vmcs;
6789         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6790                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6791
6792         /* The Intel VMX Instruction Reference lists a bunch of bits that
6793          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6794          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6795          * Otherwise, we should fail with #UD. We test these now:
6796          */
6797         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6798             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6799             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6800                 kvm_queue_exception(vcpu, UD_VECTOR);
6801                 return 1;
6802         }
6803
6804         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6805         if (is_long_mode(vcpu) && !cs.l) {
6806                 kvm_queue_exception(vcpu, UD_VECTOR);
6807                 return 1;
6808         }
6809
6810         if (vmx_get_cpl(vcpu)) {
6811                 kvm_inject_gp(vcpu, 0);
6812                 return 1;
6813         }
6814
6815         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6816                 return 1;
6817
6818         if (vmx->nested.vmxon) {
6819                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6820                 skip_emulated_instruction(vcpu);
6821                 return 1;
6822         }
6823
6824         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6825                         != VMXON_NEEDED_FEATURES) {
6826                 kvm_inject_gp(vcpu, 0);
6827                 return 1;
6828         }
6829
6830         if (enable_shadow_vmcs) {
6831                 shadow_vmcs = alloc_vmcs();
6832                 if (!shadow_vmcs)
6833                         return -ENOMEM;
6834                 /* mark vmcs as shadow */
6835                 shadow_vmcs->revision_id |= (1u << 31);
6836                 /* init shadow vmcs */
6837                 vmcs_clear(shadow_vmcs);
6838                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6839         }
6840
6841         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6842         vmx->nested.vmcs02_num = 0;
6843
6844         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6845                      HRTIMER_MODE_REL);
6846         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6847
6848         vmx->nested.vmxon = true;
6849
6850         skip_emulated_instruction(vcpu);
6851         nested_vmx_succeed(vcpu);
6852         return 1;
6853 }
6854
6855 /*
6856  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6857  * for running VMX instructions (except VMXON, whose prerequisites are
6858  * slightly different). It also specifies what exception to inject otherwise.
6859  */
6860 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6861 {
6862         struct kvm_segment cs;
6863         struct vcpu_vmx *vmx = to_vmx(vcpu);
6864
6865         if (!vmx->nested.vmxon) {
6866                 kvm_queue_exception(vcpu, UD_VECTOR);
6867                 return 0;
6868         }
6869
6870         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6871         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6872             (is_long_mode(vcpu) && !cs.l)) {
6873                 kvm_queue_exception(vcpu, UD_VECTOR);
6874                 return 0;
6875         }
6876
6877         if (vmx_get_cpl(vcpu)) {
6878                 kvm_inject_gp(vcpu, 0);
6879                 return 0;
6880         }
6881
6882         return 1;
6883 }
6884
6885 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6886 {
6887         if (vmx->nested.current_vmptr == -1ull)
6888                 return;
6889
6890         /* current_vmptr and current_vmcs12 are always set/reset together */
6891         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6892                 return;
6893
6894         if (enable_shadow_vmcs) {
6895                 /* copy to memory all shadowed fields in case
6896                    they were modified */
6897                 copy_shadow_to_vmcs12(vmx);
6898                 vmx->nested.sync_shadow_vmcs = false;
6899                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6900                                 SECONDARY_EXEC_SHADOW_VMCS);
6901                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6902         }
6903         vmx->nested.posted_intr_nv = -1;
6904         kunmap(vmx->nested.current_vmcs12_page);
6905         nested_release_page(vmx->nested.current_vmcs12_page);
6906         vmx->nested.current_vmptr = -1ull;
6907         vmx->nested.current_vmcs12 = NULL;
6908 }
6909
6910 /*
6911  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6912  * just stops using VMX.
6913  */
6914 static void free_nested(struct vcpu_vmx *vmx)
6915 {
6916         if (!vmx->nested.vmxon)
6917                 return;
6918
6919         vmx->nested.vmxon = false;
6920         free_vpid(vmx->nested.vpid02);
6921         nested_release_vmcs12(vmx);
6922         if (enable_shadow_vmcs)
6923                 free_vmcs(vmx->nested.current_shadow_vmcs);
6924         /* Unpin physical memory we referred to in current vmcs02 */
6925         if (vmx->nested.apic_access_page) {
6926                 nested_release_page(vmx->nested.apic_access_page);
6927                 vmx->nested.apic_access_page = NULL;
6928         }
6929         if (vmx->nested.virtual_apic_page) {
6930                 nested_release_page(vmx->nested.virtual_apic_page);
6931                 vmx->nested.virtual_apic_page = NULL;
6932         }
6933         if (vmx->nested.pi_desc_page) {
6934                 kunmap(vmx->nested.pi_desc_page);
6935                 nested_release_page(vmx->nested.pi_desc_page);
6936                 vmx->nested.pi_desc_page = NULL;
6937                 vmx->nested.pi_desc = NULL;
6938         }
6939
6940         nested_free_all_saved_vmcss(vmx);
6941 }
6942
6943 /* Emulate the VMXOFF instruction */
6944 static int handle_vmoff(struct kvm_vcpu *vcpu)
6945 {
6946         if (!nested_vmx_check_permission(vcpu))
6947                 return 1;
6948         free_nested(to_vmx(vcpu));
6949         skip_emulated_instruction(vcpu);
6950         nested_vmx_succeed(vcpu);
6951         return 1;
6952 }
6953
6954 /* Emulate the VMCLEAR instruction */
6955 static int handle_vmclear(struct kvm_vcpu *vcpu)
6956 {
6957         struct vcpu_vmx *vmx = to_vmx(vcpu);
6958         gpa_t vmptr;
6959         struct vmcs12 *vmcs12;
6960         struct page *page;
6961
6962         if (!nested_vmx_check_permission(vcpu))
6963                 return 1;
6964
6965         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6966                 return 1;
6967
6968         if (vmptr == vmx->nested.current_vmptr)
6969                 nested_release_vmcs12(vmx);
6970
6971         page = nested_get_page(vcpu, vmptr);
6972         if (page == NULL) {
6973                 /*
6974                  * For accurate processor emulation, VMCLEAR beyond available
6975                  * physical memory should do nothing at all. However, it is
6976                  * possible that a nested vmx bug, not a guest hypervisor bug,
6977                  * resulted in this case, so let's shut down before doing any
6978                  * more damage:
6979                  */
6980                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6981                 return 1;
6982         }
6983         vmcs12 = kmap(page);
6984         vmcs12->launch_state = 0;
6985         kunmap(page);
6986         nested_release_page(page);
6987
6988         nested_free_vmcs02(vmx, vmptr);
6989
6990         skip_emulated_instruction(vcpu);
6991         nested_vmx_succeed(vcpu);
6992         return 1;
6993 }
6994
6995 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6996
6997 /* Emulate the VMLAUNCH instruction */
6998 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6999 {
7000         return nested_vmx_run(vcpu, true);
7001 }
7002
7003 /* Emulate the VMRESUME instruction */
7004 static int handle_vmresume(struct kvm_vcpu *vcpu)
7005 {
7006
7007         return nested_vmx_run(vcpu, false);
7008 }
7009
7010 enum vmcs_field_type {
7011         VMCS_FIELD_TYPE_U16 = 0,
7012         VMCS_FIELD_TYPE_U64 = 1,
7013         VMCS_FIELD_TYPE_U32 = 2,
7014         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7015 };
7016
7017 static inline int vmcs_field_type(unsigned long field)
7018 {
7019         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7020                 return VMCS_FIELD_TYPE_U32;
7021         return (field >> 13) & 0x3 ;
7022 }
7023
7024 static inline int vmcs_field_readonly(unsigned long field)
7025 {
7026         return (((field >> 10) & 0x3) == 1);
7027 }
7028
7029 /*
7030  * Read a vmcs12 field. Since these can have varying lengths and we return
7031  * one type, we chose the biggest type (u64) and zero-extend the return value
7032  * to that size. Note that the caller, handle_vmread, might need to use only
7033  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7034  * 64-bit fields are to be returned).
7035  */
7036 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7037                                   unsigned long field, u64 *ret)
7038 {
7039         short offset = vmcs_field_to_offset(field);
7040         char *p;
7041
7042         if (offset < 0)
7043                 return offset;
7044
7045         p = ((char *)(get_vmcs12(vcpu))) + offset;
7046
7047         switch (vmcs_field_type(field)) {
7048         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7049                 *ret = *((natural_width *)p);
7050                 return 0;
7051         case VMCS_FIELD_TYPE_U16:
7052                 *ret = *((u16 *)p);
7053                 return 0;
7054         case VMCS_FIELD_TYPE_U32:
7055                 *ret = *((u32 *)p);
7056                 return 0;
7057         case VMCS_FIELD_TYPE_U64:
7058                 *ret = *((u64 *)p);
7059                 return 0;
7060         default:
7061                 WARN_ON(1);
7062                 return -ENOENT;
7063         }
7064 }
7065
7066
7067 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7068                                    unsigned long field, u64 field_value){
7069         short offset = vmcs_field_to_offset(field);
7070         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7071         if (offset < 0)
7072                 return offset;
7073
7074         switch (vmcs_field_type(field)) {
7075         case VMCS_FIELD_TYPE_U16:
7076                 *(u16 *)p = field_value;
7077                 return 0;
7078         case VMCS_FIELD_TYPE_U32:
7079                 *(u32 *)p = field_value;
7080                 return 0;
7081         case VMCS_FIELD_TYPE_U64:
7082                 *(u64 *)p = field_value;
7083                 return 0;
7084         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7085                 *(natural_width *)p = field_value;
7086                 return 0;
7087         default:
7088                 WARN_ON(1);
7089                 return -ENOENT;
7090         }
7091
7092 }
7093
7094 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7095 {
7096         int i;
7097         unsigned long field;
7098         u64 field_value;
7099         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7100         const unsigned long *fields = shadow_read_write_fields;
7101         const int num_fields = max_shadow_read_write_fields;
7102
7103         preempt_disable();
7104
7105         vmcs_load(shadow_vmcs);
7106
7107         for (i = 0; i < num_fields; i++) {
7108                 field = fields[i];
7109                 switch (vmcs_field_type(field)) {
7110                 case VMCS_FIELD_TYPE_U16:
7111                         field_value = vmcs_read16(field);
7112                         break;
7113                 case VMCS_FIELD_TYPE_U32:
7114                         field_value = vmcs_read32(field);
7115                         break;
7116                 case VMCS_FIELD_TYPE_U64:
7117                         field_value = vmcs_read64(field);
7118                         break;
7119                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7120                         field_value = vmcs_readl(field);
7121                         break;
7122                 default:
7123                         WARN_ON(1);
7124                         continue;
7125                 }
7126                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7127         }
7128
7129         vmcs_clear(shadow_vmcs);
7130         vmcs_load(vmx->loaded_vmcs->vmcs);
7131
7132         preempt_enable();
7133 }
7134
7135 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7136 {
7137         const unsigned long *fields[] = {
7138                 shadow_read_write_fields,
7139                 shadow_read_only_fields
7140         };
7141         const int max_fields[] = {
7142                 max_shadow_read_write_fields,
7143                 max_shadow_read_only_fields
7144         };
7145         int i, q;
7146         unsigned long field;
7147         u64 field_value = 0;
7148         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7149
7150         vmcs_load(shadow_vmcs);
7151
7152         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7153                 for (i = 0; i < max_fields[q]; i++) {
7154                         field = fields[q][i];
7155                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7156
7157                         switch (vmcs_field_type(field)) {
7158                         case VMCS_FIELD_TYPE_U16:
7159                                 vmcs_write16(field, (u16)field_value);
7160                                 break;
7161                         case VMCS_FIELD_TYPE_U32:
7162                                 vmcs_write32(field, (u32)field_value);
7163                                 break;
7164                         case VMCS_FIELD_TYPE_U64:
7165                                 vmcs_write64(field, (u64)field_value);
7166                                 break;
7167                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7168                                 vmcs_writel(field, (long)field_value);
7169                                 break;
7170                         default:
7171                                 WARN_ON(1);
7172                                 break;
7173                         }
7174                 }
7175         }
7176
7177         vmcs_clear(shadow_vmcs);
7178         vmcs_load(vmx->loaded_vmcs->vmcs);
7179 }
7180
7181 /*
7182  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7183  * used before) all generate the same failure when it is missing.
7184  */
7185 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7186 {
7187         struct vcpu_vmx *vmx = to_vmx(vcpu);
7188         if (vmx->nested.current_vmptr == -1ull) {
7189                 nested_vmx_failInvalid(vcpu);
7190                 skip_emulated_instruction(vcpu);
7191                 return 0;
7192         }
7193         return 1;
7194 }
7195
7196 static int handle_vmread(struct kvm_vcpu *vcpu)
7197 {
7198         unsigned long field;
7199         u64 field_value;
7200         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7201         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7202         gva_t gva = 0;
7203
7204         if (!nested_vmx_check_permission(vcpu) ||
7205             !nested_vmx_check_vmcs12(vcpu))
7206                 return 1;
7207
7208         /* Decode instruction info and find the field to read */
7209         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7210         /* Read the field, zero-extended to a u64 field_value */
7211         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7212                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7213                 skip_emulated_instruction(vcpu);
7214                 return 1;
7215         }
7216         /*
7217          * Now copy part of this value to register or memory, as requested.
7218          * Note that the number of bits actually copied is 32 or 64 depending
7219          * on the guest's mode (32 or 64 bit), not on the given field's length.
7220          */
7221         if (vmx_instruction_info & (1u << 10)) {
7222                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7223                         field_value);
7224         } else {
7225                 if (get_vmx_mem_address(vcpu, exit_qualification,
7226                                 vmx_instruction_info, true, &gva))
7227                         return 1;
7228                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7229                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7230                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7231         }
7232
7233         nested_vmx_succeed(vcpu);
7234         skip_emulated_instruction(vcpu);
7235         return 1;
7236 }
7237
7238
7239 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7240 {
7241         unsigned long field;
7242         gva_t gva;
7243         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7244         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7245         /* The value to write might be 32 or 64 bits, depending on L1's long
7246          * mode, and eventually we need to write that into a field of several
7247          * possible lengths. The code below first zero-extends the value to 64
7248          * bit (field_value), and then copies only the approriate number of
7249          * bits into the vmcs12 field.
7250          */
7251         u64 field_value = 0;
7252         struct x86_exception e;
7253
7254         if (!nested_vmx_check_permission(vcpu) ||
7255             !nested_vmx_check_vmcs12(vcpu))
7256                 return 1;
7257
7258         if (vmx_instruction_info & (1u << 10))
7259                 field_value = kvm_register_readl(vcpu,
7260                         (((vmx_instruction_info) >> 3) & 0xf));
7261         else {
7262                 if (get_vmx_mem_address(vcpu, exit_qualification,
7263                                 vmx_instruction_info, false, &gva))
7264                         return 1;
7265                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7266                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7267                         kvm_inject_page_fault(vcpu, &e);
7268                         return 1;
7269                 }
7270         }
7271
7272
7273         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7274         if (vmcs_field_readonly(field)) {
7275                 nested_vmx_failValid(vcpu,
7276                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7277                 skip_emulated_instruction(vcpu);
7278                 return 1;
7279         }
7280
7281         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7282                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7283                 skip_emulated_instruction(vcpu);
7284                 return 1;
7285         }
7286
7287         nested_vmx_succeed(vcpu);
7288         skip_emulated_instruction(vcpu);
7289         return 1;
7290 }
7291
7292 /* Emulate the VMPTRLD instruction */
7293 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7294 {
7295         struct vcpu_vmx *vmx = to_vmx(vcpu);
7296         gpa_t vmptr;
7297
7298         if (!nested_vmx_check_permission(vcpu))
7299                 return 1;
7300
7301         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7302                 return 1;
7303
7304         if (vmx->nested.current_vmptr != vmptr) {
7305                 struct vmcs12 *new_vmcs12;
7306                 struct page *page;
7307                 page = nested_get_page(vcpu, vmptr);
7308                 if (page == NULL) {
7309                         nested_vmx_failInvalid(vcpu);
7310                         skip_emulated_instruction(vcpu);
7311                         return 1;
7312                 }
7313                 new_vmcs12 = kmap(page);
7314                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7315                         kunmap(page);
7316                         nested_release_page_clean(page);
7317                         nested_vmx_failValid(vcpu,
7318                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7319                         skip_emulated_instruction(vcpu);
7320                         return 1;
7321                 }
7322
7323                 nested_release_vmcs12(vmx);
7324                 vmx->nested.current_vmptr = vmptr;
7325                 vmx->nested.current_vmcs12 = new_vmcs12;
7326                 vmx->nested.current_vmcs12_page = page;
7327                 if (enable_shadow_vmcs) {
7328                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7329                                       SECONDARY_EXEC_SHADOW_VMCS);
7330                         vmcs_write64(VMCS_LINK_POINTER,
7331                                      __pa(vmx->nested.current_shadow_vmcs));
7332                         vmx->nested.sync_shadow_vmcs = true;
7333                 }
7334         }
7335
7336         nested_vmx_succeed(vcpu);
7337         skip_emulated_instruction(vcpu);
7338         return 1;
7339 }
7340
7341 /* Emulate the VMPTRST instruction */
7342 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7343 {
7344         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7345         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7346         gva_t vmcs_gva;
7347         struct x86_exception e;
7348
7349         if (!nested_vmx_check_permission(vcpu))
7350                 return 1;
7351
7352         if (get_vmx_mem_address(vcpu, exit_qualification,
7353                         vmx_instruction_info, true, &vmcs_gva))
7354                 return 1;
7355         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7356         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7357                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7358                                  sizeof(u64), &e)) {
7359                 kvm_inject_page_fault(vcpu, &e);
7360                 return 1;
7361         }
7362         nested_vmx_succeed(vcpu);
7363         skip_emulated_instruction(vcpu);
7364         return 1;
7365 }
7366
7367 /* Emulate the INVEPT instruction */
7368 static int handle_invept(struct kvm_vcpu *vcpu)
7369 {
7370         struct vcpu_vmx *vmx = to_vmx(vcpu);
7371         u32 vmx_instruction_info, types;
7372         unsigned long type;
7373         gva_t gva;
7374         struct x86_exception e;
7375         struct {
7376                 u64 eptp, gpa;
7377         } operand;
7378
7379         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7380               SECONDARY_EXEC_ENABLE_EPT) ||
7381             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7382                 kvm_queue_exception(vcpu, UD_VECTOR);
7383                 return 1;
7384         }
7385
7386         if (!nested_vmx_check_permission(vcpu))
7387                 return 1;
7388
7389         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7390                 kvm_queue_exception(vcpu, UD_VECTOR);
7391                 return 1;
7392         }
7393
7394         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7395         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7396
7397         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7398
7399         if (!(types & (1UL << type))) {
7400                 nested_vmx_failValid(vcpu,
7401                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7402                 skip_emulated_instruction(vcpu);
7403                 return 1;
7404         }
7405
7406         /* According to the Intel VMX instruction reference, the memory
7407          * operand is read even if it isn't needed (e.g., for type==global)
7408          */
7409         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7410                         vmx_instruction_info, false, &gva))
7411                 return 1;
7412         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7413                                 sizeof(operand), &e)) {
7414                 kvm_inject_page_fault(vcpu, &e);
7415                 return 1;
7416         }
7417
7418         switch (type) {
7419         case VMX_EPT_EXTENT_GLOBAL:
7420                 kvm_mmu_sync_roots(vcpu);
7421                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7422                 nested_vmx_succeed(vcpu);
7423                 break;
7424         default:
7425                 /* Trap single context invalidation invept calls */
7426                 BUG_ON(1);
7427                 break;
7428         }
7429
7430         skip_emulated_instruction(vcpu);
7431         return 1;
7432 }
7433
7434 static int handle_invvpid(struct kvm_vcpu *vcpu)
7435 {
7436         struct vcpu_vmx *vmx = to_vmx(vcpu);
7437         u32 vmx_instruction_info;
7438         unsigned long type, types;
7439         gva_t gva;
7440         struct x86_exception e;
7441         int vpid;
7442
7443         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7444               SECONDARY_EXEC_ENABLE_VPID) ||
7445                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7446                 kvm_queue_exception(vcpu, UD_VECTOR);
7447                 return 1;
7448         }
7449
7450         if (!nested_vmx_check_permission(vcpu))
7451                 return 1;
7452
7453         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7454         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7455
7456         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7457
7458         if (!(types & (1UL << type))) {
7459                 nested_vmx_failValid(vcpu,
7460                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7461                 return 1;
7462         }
7463
7464         /* according to the intel vmx instruction reference, the memory
7465          * operand is read even if it isn't needed (e.g., for type==global)
7466          */
7467         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7468                         vmx_instruction_info, false, &gva))
7469                 return 1;
7470         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7471                                 sizeof(u32), &e)) {
7472                 kvm_inject_page_fault(vcpu, &e);
7473                 return 1;
7474         }
7475
7476         switch (type) {
7477         case VMX_VPID_EXTENT_ALL_CONTEXT:
7478                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7479                 nested_vmx_succeed(vcpu);
7480                 break;
7481         default:
7482                 /* Trap single context invalidation invvpid calls */
7483                 BUG_ON(1);
7484                 break;
7485         }
7486
7487         skip_emulated_instruction(vcpu);
7488         return 1;
7489 }
7490
7491 static int handle_pml_full(struct kvm_vcpu *vcpu)
7492 {
7493         unsigned long exit_qualification;
7494
7495         trace_kvm_pml_full(vcpu->vcpu_id);
7496
7497         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7498
7499         /*
7500          * PML buffer FULL happened while executing iret from NMI,
7501          * "blocked by NMI" bit has to be set before next VM entry.
7502          */
7503         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7504                         cpu_has_virtual_nmis() &&
7505                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7506                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7507                                 GUEST_INTR_STATE_NMI);
7508
7509         /*
7510          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7511          * here.., and there's no userspace involvement needed for PML.
7512          */
7513         return 1;
7514 }
7515
7516 static int handle_pcommit(struct kvm_vcpu *vcpu)
7517 {
7518         /* we never catch pcommit instruct for L1 guest. */
7519         WARN_ON(1);
7520         return 1;
7521 }
7522
7523 /*
7524  * The exit handlers return 1 if the exit was handled fully and guest execution
7525  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7526  * to be done to userspace and return 0.
7527  */
7528 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7529         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7530         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7531         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7532         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7533         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7534         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7535         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7536         [EXIT_REASON_CPUID]                   = handle_cpuid,
7537         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7538         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7539         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7540         [EXIT_REASON_HLT]                     = handle_halt,
7541         [EXIT_REASON_INVD]                    = handle_invd,
7542         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7543         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7544         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7545         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7546         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7547         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7548         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7549         [EXIT_REASON_VMREAD]                  = handle_vmread,
7550         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7551         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7552         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7553         [EXIT_REASON_VMON]                    = handle_vmon,
7554         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7555         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7556         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7557         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7558         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7559         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7560         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7561         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7562         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7563         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7564         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7565         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7566         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7567         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7568         [EXIT_REASON_INVEPT]                  = handle_invept,
7569         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7570         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7571         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7572         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7573         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7574 };
7575
7576 static const int kvm_vmx_max_exit_handlers =
7577         ARRAY_SIZE(kvm_vmx_exit_handlers);
7578
7579 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7580                                        struct vmcs12 *vmcs12)
7581 {
7582         unsigned long exit_qualification;
7583         gpa_t bitmap, last_bitmap;
7584         unsigned int port;
7585         int size;
7586         u8 b;
7587
7588         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7589                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7590
7591         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7592
7593         port = exit_qualification >> 16;
7594         size = (exit_qualification & 7) + 1;
7595
7596         last_bitmap = (gpa_t)-1;
7597         b = -1;
7598
7599         while (size > 0) {
7600                 if (port < 0x8000)
7601                         bitmap = vmcs12->io_bitmap_a;
7602                 else if (port < 0x10000)
7603                         bitmap = vmcs12->io_bitmap_b;
7604                 else
7605                         return true;
7606                 bitmap += (port & 0x7fff) / 8;
7607
7608                 if (last_bitmap != bitmap)
7609                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7610                                 return true;
7611                 if (b & (1 << (port & 7)))
7612                         return true;
7613
7614                 port++;
7615                 size--;
7616                 last_bitmap = bitmap;
7617         }
7618
7619         return false;
7620 }
7621
7622 /*
7623  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7624  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7625  * disinterest in the current event (read or write a specific MSR) by using an
7626  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7627  */
7628 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7629         struct vmcs12 *vmcs12, u32 exit_reason)
7630 {
7631         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7632         gpa_t bitmap;
7633
7634         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7635                 return true;
7636
7637         /*
7638          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7639          * for the four combinations of read/write and low/high MSR numbers.
7640          * First we need to figure out which of the four to use:
7641          */
7642         bitmap = vmcs12->msr_bitmap;
7643         if (exit_reason == EXIT_REASON_MSR_WRITE)
7644                 bitmap += 2048;
7645         if (msr_index >= 0xc0000000) {
7646                 msr_index -= 0xc0000000;
7647                 bitmap += 1024;
7648         }
7649
7650         /* Then read the msr_index'th bit from this bitmap: */
7651         if (msr_index < 1024*8) {
7652                 unsigned char b;
7653                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7654                         return true;
7655                 return 1 & (b >> (msr_index & 7));
7656         } else
7657                 return true; /* let L1 handle the wrong parameter */
7658 }
7659
7660 /*
7661  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7662  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7663  * intercept (via guest_host_mask etc.) the current event.
7664  */
7665 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7666         struct vmcs12 *vmcs12)
7667 {
7668         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7669         int cr = exit_qualification & 15;
7670         int reg = (exit_qualification >> 8) & 15;
7671         unsigned long val = kvm_register_readl(vcpu, reg);
7672
7673         switch ((exit_qualification >> 4) & 3) {
7674         case 0: /* mov to cr */
7675                 switch (cr) {
7676                 case 0:
7677                         if (vmcs12->cr0_guest_host_mask &
7678                             (val ^ vmcs12->cr0_read_shadow))
7679                                 return true;
7680                         break;
7681                 case 3:
7682                         if ((vmcs12->cr3_target_count >= 1 &&
7683                                         vmcs12->cr3_target_value0 == val) ||
7684                                 (vmcs12->cr3_target_count >= 2 &&
7685                                         vmcs12->cr3_target_value1 == val) ||
7686                                 (vmcs12->cr3_target_count >= 3 &&
7687                                         vmcs12->cr3_target_value2 == val) ||
7688                                 (vmcs12->cr3_target_count >= 4 &&
7689                                         vmcs12->cr3_target_value3 == val))
7690                                 return false;
7691                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7692                                 return true;
7693                         break;
7694                 case 4:
7695                         if (vmcs12->cr4_guest_host_mask &
7696                             (vmcs12->cr4_read_shadow ^ val))
7697                                 return true;
7698                         break;
7699                 case 8:
7700                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7701                                 return true;
7702                         break;
7703                 }
7704                 break;
7705         case 2: /* clts */
7706                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7707                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7708                         return true;
7709                 break;
7710         case 1: /* mov from cr */
7711                 switch (cr) {
7712                 case 3:
7713                         if (vmcs12->cpu_based_vm_exec_control &
7714                             CPU_BASED_CR3_STORE_EXITING)
7715                                 return true;
7716                         break;
7717                 case 8:
7718                         if (vmcs12->cpu_based_vm_exec_control &
7719                             CPU_BASED_CR8_STORE_EXITING)
7720                                 return true;
7721                         break;
7722                 }
7723                 break;
7724         case 3: /* lmsw */
7725                 /*
7726                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7727                  * cr0. Other attempted changes are ignored, with no exit.
7728                  */
7729                 if (vmcs12->cr0_guest_host_mask & 0xe &
7730                     (val ^ vmcs12->cr0_read_shadow))
7731                         return true;
7732                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7733                     !(vmcs12->cr0_read_shadow & 0x1) &&
7734                     (val & 0x1))
7735                         return true;
7736                 break;
7737         }
7738         return false;
7739 }
7740
7741 /*
7742  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7743  * should handle it ourselves in L0 (and then continue L2). Only call this
7744  * when in is_guest_mode (L2).
7745  */
7746 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7747 {
7748         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7749         struct vcpu_vmx *vmx = to_vmx(vcpu);
7750         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7751         u32 exit_reason = vmx->exit_reason;
7752
7753         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7754                                 vmcs_readl(EXIT_QUALIFICATION),
7755                                 vmx->idt_vectoring_info,
7756                                 intr_info,
7757                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7758                                 KVM_ISA_VMX);
7759
7760         if (vmx->nested.nested_run_pending)
7761                 return false;
7762
7763         if (unlikely(vmx->fail)) {
7764                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7765                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7766                 return true;
7767         }
7768
7769         switch (exit_reason) {
7770         case EXIT_REASON_EXCEPTION_NMI:
7771                 if (!is_exception(intr_info))
7772                         return false;
7773                 else if (is_page_fault(intr_info))
7774                         return enable_ept;
7775                 else if (is_no_device(intr_info) &&
7776                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7777                         return false;
7778                 else if (is_debug(intr_info) &&
7779                          vcpu->guest_debug &
7780                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7781                         return false;
7782                 else if (is_breakpoint(intr_info) &&
7783                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7784                         return false;
7785                 return vmcs12->exception_bitmap &
7786                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7787         case EXIT_REASON_EXTERNAL_INTERRUPT:
7788                 return false;
7789         case EXIT_REASON_TRIPLE_FAULT:
7790                 return true;
7791         case EXIT_REASON_PENDING_INTERRUPT:
7792                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7793         case EXIT_REASON_NMI_WINDOW:
7794                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7795         case EXIT_REASON_TASK_SWITCH:
7796                 return true;
7797         case EXIT_REASON_CPUID:
7798                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7799                         return false;
7800                 return true;
7801         case EXIT_REASON_HLT:
7802                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7803         case EXIT_REASON_INVD:
7804                 return true;
7805         case EXIT_REASON_INVLPG:
7806                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7807         case EXIT_REASON_RDPMC:
7808                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7809         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7810                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7811         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7812         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7813         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7814         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7815         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7816         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7817                 /*
7818                  * VMX instructions trap unconditionally. This allows L1 to
7819                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7820                  */
7821                 return true;
7822         case EXIT_REASON_CR_ACCESS:
7823                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7824         case EXIT_REASON_DR_ACCESS:
7825                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7826         case EXIT_REASON_IO_INSTRUCTION:
7827                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7828         case EXIT_REASON_MSR_READ:
7829         case EXIT_REASON_MSR_WRITE:
7830                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7831         case EXIT_REASON_INVALID_STATE:
7832                 return true;
7833         case EXIT_REASON_MWAIT_INSTRUCTION:
7834                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7835         case EXIT_REASON_MONITOR_TRAP_FLAG:
7836                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7837         case EXIT_REASON_MONITOR_INSTRUCTION:
7838                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7839         case EXIT_REASON_PAUSE_INSTRUCTION:
7840                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7841                         nested_cpu_has2(vmcs12,
7842                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7843         case EXIT_REASON_MCE_DURING_VMENTRY:
7844                 return false;
7845         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7846                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7847         case EXIT_REASON_APIC_ACCESS:
7848                 return nested_cpu_has2(vmcs12,
7849                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7850         case EXIT_REASON_APIC_WRITE:
7851         case EXIT_REASON_EOI_INDUCED:
7852                 /* apic_write and eoi_induced should exit unconditionally. */
7853                 return true;
7854         case EXIT_REASON_EPT_VIOLATION:
7855                 /*
7856                  * L0 always deals with the EPT violation. If nested EPT is
7857                  * used, and the nested mmu code discovers that the address is
7858                  * missing in the guest EPT table (EPT12), the EPT violation
7859                  * will be injected with nested_ept_inject_page_fault()
7860                  */
7861                 return false;
7862         case EXIT_REASON_EPT_MISCONFIG:
7863                 /*
7864                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7865                  * table (shadow on EPT) or a merged EPT table that L0 built
7866                  * (EPT on EPT). So any problems with the structure of the
7867                  * table is L0's fault.
7868                  */
7869                 return false;
7870         case EXIT_REASON_WBINVD:
7871                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7872         case EXIT_REASON_XSETBV:
7873                 return true;
7874         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7875                 /*
7876                  * This should never happen, since it is not possible to
7877                  * set XSS to a non-zero value---neither in L1 nor in L2.
7878                  * If if it were, XSS would have to be checked against
7879                  * the XSS exit bitmap in vmcs12.
7880                  */
7881                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7882         case EXIT_REASON_PCOMMIT:
7883                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7884         default:
7885                 return true;
7886         }
7887 }
7888
7889 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7890 {
7891         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7892         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7893 }
7894
7895 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7896 {
7897         struct page *pml_pg;
7898
7899         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7900         if (!pml_pg)
7901                 return -ENOMEM;
7902
7903         vmx->pml_pg = pml_pg;
7904
7905         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7906         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7907
7908         return 0;
7909 }
7910
7911 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7912 {
7913         if (vmx->pml_pg) {
7914                 __free_page(vmx->pml_pg);
7915                 vmx->pml_pg = NULL;
7916         }
7917 }
7918
7919 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7920 {
7921         struct vcpu_vmx *vmx = to_vmx(vcpu);
7922         u64 *pml_buf;
7923         u16 pml_idx;
7924
7925         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7926
7927         /* Do nothing if PML buffer is empty */
7928         if (pml_idx == (PML_ENTITY_NUM - 1))
7929                 return;
7930
7931         /* PML index always points to next available PML buffer entity */
7932         if (pml_idx >= PML_ENTITY_NUM)
7933                 pml_idx = 0;
7934         else
7935                 pml_idx++;
7936
7937         pml_buf = page_address(vmx->pml_pg);
7938         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7939                 u64 gpa;
7940
7941                 gpa = pml_buf[pml_idx];
7942                 WARN_ON(gpa & (PAGE_SIZE - 1));
7943                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7944         }
7945
7946         /* reset PML index */
7947         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7948 }
7949
7950 /*
7951  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7952  * Called before reporting dirty_bitmap to userspace.
7953  */
7954 static void kvm_flush_pml_buffers(struct kvm *kvm)
7955 {
7956         int i;
7957         struct kvm_vcpu *vcpu;
7958         /*
7959          * We only need to kick vcpu out of guest mode here, as PML buffer
7960          * is flushed at beginning of all VMEXITs, and it's obvious that only
7961          * vcpus running in guest are possible to have unflushed GPAs in PML
7962          * buffer.
7963          */
7964         kvm_for_each_vcpu(i, vcpu, kvm)
7965                 kvm_vcpu_kick(vcpu);
7966 }
7967
7968 static void vmx_dump_sel(char *name, uint32_t sel)
7969 {
7970         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7971                name, vmcs_read32(sel),
7972                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7973                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7974                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7975 }
7976
7977 static void vmx_dump_dtsel(char *name, uint32_t limit)
7978 {
7979         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7980                name, vmcs_read32(limit),
7981                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7982 }
7983
7984 static void dump_vmcs(void)
7985 {
7986         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7987         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7988         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7989         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7990         u32 secondary_exec_control = 0;
7991         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7992         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7993         int i, n;
7994
7995         if (cpu_has_secondary_exec_ctrls())
7996                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7997
7998         pr_err("*** Guest State ***\n");
7999         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8000                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8001                vmcs_readl(CR0_GUEST_HOST_MASK));
8002         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8003                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8004         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8005         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8006             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8007         {
8008                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8009                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8010                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8011                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8012         }
8013         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8014                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8015         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8016                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8017         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8018                vmcs_readl(GUEST_SYSENTER_ESP),
8019                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8020         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8021         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8022         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8023         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8024         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8025         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8026         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8027         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8028         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8029         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8030         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8031             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8032                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8033                        efer, vmcs_read64(GUEST_IA32_PAT));
8034         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8035                vmcs_read64(GUEST_IA32_DEBUGCTL),
8036                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8037         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8038                 pr_err("PerfGlobCtl = 0x%016llx\n",
8039                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8040         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8041                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8042         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8043                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8044                vmcs_read32(GUEST_ACTIVITY_STATE));
8045         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8046                 pr_err("InterruptStatus = %04x\n",
8047                        vmcs_read16(GUEST_INTR_STATUS));
8048
8049         pr_err("*** Host State ***\n");
8050         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8051                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8052         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8053                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8054                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8055                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8056                vmcs_read16(HOST_TR_SELECTOR));
8057         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8058                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8059                vmcs_readl(HOST_TR_BASE));
8060         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8061                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8062         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8063                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8064                vmcs_readl(HOST_CR4));
8065         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8066                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8067                vmcs_read32(HOST_IA32_SYSENTER_CS),
8068                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8069         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8070                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8071                        vmcs_read64(HOST_IA32_EFER),
8072                        vmcs_read64(HOST_IA32_PAT));
8073         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8074                 pr_err("PerfGlobCtl = 0x%016llx\n",
8075                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8076
8077         pr_err("*** Control State ***\n");
8078         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8079                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8080         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8081         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8082                vmcs_read32(EXCEPTION_BITMAP),
8083                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8084                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8085         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8086                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8087                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8088                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8089         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8090                vmcs_read32(VM_EXIT_INTR_INFO),
8091                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8092                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8093         pr_err("        reason=%08x qualification=%016lx\n",
8094                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8095         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8096                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8097                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8098         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8099         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8100                 pr_err("TSC Multiplier = 0x%016llx\n",
8101                        vmcs_read64(TSC_MULTIPLIER));
8102         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8103                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8104         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8105                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8106         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8107                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8108         n = vmcs_read32(CR3_TARGET_COUNT);
8109         for (i = 0; i + 1 < n; i += 4)
8110                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8111                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8112                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8113         if (i < n)
8114                 pr_err("CR3 target%u=%016lx\n",
8115                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8116         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8117                 pr_err("PLE Gap=%08x Window=%08x\n",
8118                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8119         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8120                 pr_err("Virtual processor ID = 0x%04x\n",
8121                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8122 }
8123
8124 /*
8125  * The guest has exited.  See if we can fix it or if we need userspace
8126  * assistance.
8127  */
8128 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8129 {
8130         struct vcpu_vmx *vmx = to_vmx(vcpu);
8131         u32 exit_reason = vmx->exit_reason;
8132         u32 vectoring_info = vmx->idt_vectoring_info;
8133
8134         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8135
8136         /*
8137          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8138          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8139          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8140          * mode as if vcpus is in root mode, the PML buffer must has been
8141          * flushed already.
8142          */
8143         if (enable_pml)
8144                 vmx_flush_pml_buffer(vcpu);
8145
8146         /* If guest state is invalid, start emulating */
8147         if (vmx->emulation_required)
8148                 return handle_invalid_guest_state(vcpu);
8149
8150         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8151                 nested_vmx_vmexit(vcpu, exit_reason,
8152                                   vmcs_read32(VM_EXIT_INTR_INFO),
8153                                   vmcs_readl(EXIT_QUALIFICATION));
8154                 return 1;
8155         }
8156
8157         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8158                 dump_vmcs();
8159                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8160                 vcpu->run->fail_entry.hardware_entry_failure_reason
8161                         = exit_reason;
8162                 return 0;
8163         }
8164
8165         if (unlikely(vmx->fail)) {
8166                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8167                 vcpu->run->fail_entry.hardware_entry_failure_reason
8168                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8169                 return 0;
8170         }
8171
8172         /*
8173          * Note:
8174          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8175          * delivery event since it indicates guest is accessing MMIO.
8176          * The vm-exit can be triggered again after return to guest that
8177          * will cause infinite loop.
8178          */
8179         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8180                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8181                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8182                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8183                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8184                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8185                 vcpu->run->internal.ndata = 2;
8186                 vcpu->run->internal.data[0] = vectoring_info;
8187                 vcpu->run->internal.data[1] = exit_reason;
8188                 return 0;
8189         }
8190
8191         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8192             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8193                                         get_vmcs12(vcpu))))) {
8194                 if (vmx_interrupt_allowed(vcpu)) {
8195                         vmx->soft_vnmi_blocked = 0;
8196                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8197                            vcpu->arch.nmi_pending) {
8198                         /*
8199                          * This CPU don't support us in finding the end of an
8200                          * NMI-blocked window if the guest runs with IRQs
8201                          * disabled. So we pull the trigger after 1 s of
8202                          * futile waiting, but inform the user about this.
8203                          */
8204                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8205                                "state on VCPU %d after 1 s timeout\n",
8206                                __func__, vcpu->vcpu_id);
8207                         vmx->soft_vnmi_blocked = 0;
8208                 }
8209         }
8210
8211         if (exit_reason < kvm_vmx_max_exit_handlers
8212             && kvm_vmx_exit_handlers[exit_reason])
8213                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8214         else {
8215                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8216                 kvm_queue_exception(vcpu, UD_VECTOR);
8217                 return 1;
8218         }
8219 }
8220
8221 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8222 {
8223         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8224
8225         if (is_guest_mode(vcpu) &&
8226                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8227                 return;
8228
8229         if (irr == -1 || tpr < irr) {
8230                 vmcs_write32(TPR_THRESHOLD, 0);
8231                 return;
8232         }
8233
8234         vmcs_write32(TPR_THRESHOLD, irr);
8235 }
8236
8237 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8238 {
8239         u32 sec_exec_control;
8240
8241         /*
8242          * There is not point to enable virtualize x2apic without enable
8243          * apicv
8244          */
8245         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8246                                 !kvm_vcpu_apicv_active(vcpu))
8247                 return;
8248
8249         if (!cpu_need_tpr_shadow(vcpu))
8250                 return;
8251
8252         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8253
8254         if (set) {
8255                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8256                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8257         } else {
8258                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8259                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8260         }
8261         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8262
8263         vmx_set_msr_bitmap(vcpu);
8264 }
8265
8266 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8267 {
8268         struct vcpu_vmx *vmx = to_vmx(vcpu);
8269
8270         /*
8271          * Currently we do not handle the nested case where L2 has an
8272          * APIC access page of its own; that page is still pinned.
8273          * Hence, we skip the case where the VCPU is in guest mode _and_
8274          * L1 prepared an APIC access page for L2.
8275          *
8276          * For the case where L1 and L2 share the same APIC access page
8277          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8278          * in the vmcs12), this function will only update either the vmcs01
8279          * or the vmcs02.  If the former, the vmcs02 will be updated by
8280          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8281          * the next L2->L1 exit.
8282          */
8283         if (!is_guest_mode(vcpu) ||
8284             !nested_cpu_has2(vmx->nested.current_vmcs12,
8285                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8286                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8287 }
8288
8289 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8290 {
8291         u16 status;
8292         u8 old;
8293
8294         if (isr == -1)
8295                 isr = 0;
8296
8297         status = vmcs_read16(GUEST_INTR_STATUS);
8298         old = status >> 8;
8299         if (isr != old) {
8300                 status &= 0xff;
8301                 status |= isr << 8;
8302                 vmcs_write16(GUEST_INTR_STATUS, status);
8303         }
8304 }
8305
8306 static void vmx_set_rvi(int vector)
8307 {
8308         u16 status;
8309         u8 old;
8310
8311         if (vector == -1)
8312                 vector = 0;
8313
8314         status = vmcs_read16(GUEST_INTR_STATUS);
8315         old = (u8)status & 0xff;
8316         if ((u8)vector != old) {
8317                 status &= ~0xff;
8318                 status |= (u8)vector;
8319                 vmcs_write16(GUEST_INTR_STATUS, status);
8320         }
8321 }
8322
8323 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8324 {
8325         if (!is_guest_mode(vcpu)) {
8326                 vmx_set_rvi(max_irr);
8327                 return;
8328         }
8329
8330         if (max_irr == -1)
8331                 return;
8332
8333         /*
8334          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8335          * handles it.
8336          */
8337         if (nested_exit_on_intr(vcpu))
8338                 return;
8339
8340         /*
8341          * Else, fall back to pre-APICv interrupt injection since L2
8342          * is run without virtual interrupt delivery.
8343          */
8344         if (!kvm_event_needs_reinjection(vcpu) &&
8345             vmx_interrupt_allowed(vcpu)) {
8346                 kvm_queue_interrupt(vcpu, max_irr, false);
8347                 vmx_inject_irq(vcpu);
8348         }
8349 }
8350
8351 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8352 {
8353         if (!kvm_vcpu_apicv_active(vcpu))
8354                 return;
8355
8356         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8357         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8358         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8359         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8360 }
8361
8362 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8363 {
8364         u32 exit_intr_info;
8365
8366         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8367               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8368                 return;
8369
8370         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8371         exit_intr_info = vmx->exit_intr_info;
8372
8373         /* Handle machine checks before interrupts are enabled */
8374         if (is_machine_check(exit_intr_info))
8375                 kvm_machine_check();
8376
8377         /* We need to handle NMIs before interrupts are enabled */
8378         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8379             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8380                 kvm_before_handle_nmi(&vmx->vcpu);
8381                 asm("int $2");
8382                 kvm_after_handle_nmi(&vmx->vcpu);
8383         }
8384 }
8385
8386 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8387 {
8388         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8389         register void *__sp asm(_ASM_SP);
8390
8391         /*
8392          * If external interrupt exists, IF bit is set in rflags/eflags on the
8393          * interrupt stack frame, and interrupt will be enabled on a return
8394          * from interrupt handler.
8395          */
8396         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8397                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8398                 unsigned int vector;
8399                 unsigned long entry;
8400                 gate_desc *desc;
8401                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8402 #ifdef CONFIG_X86_64
8403                 unsigned long tmp;
8404 #endif
8405
8406                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8407                 desc = (gate_desc *)vmx->host_idt_base + vector;
8408                 entry = gate_offset(*desc);
8409                 asm volatile(
8410 #ifdef CONFIG_X86_64
8411                         "mov %%" _ASM_SP ", %[sp]\n\t"
8412                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8413                         "push $%c[ss]\n\t"
8414                         "push %[sp]\n\t"
8415 #endif
8416                         "pushf\n\t"
8417                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8418                         __ASM_SIZE(push) " $%c[cs]\n\t"
8419                         "call *%[entry]\n\t"
8420                         :
8421 #ifdef CONFIG_X86_64
8422                         [sp]"=&r"(tmp),
8423 #endif
8424                         "+r"(__sp)
8425                         :
8426                         [entry]"r"(entry),
8427                         [ss]"i"(__KERNEL_DS),
8428                         [cs]"i"(__KERNEL_CS)
8429                         );
8430         } else
8431                 local_irq_enable();
8432 }
8433
8434 static bool vmx_has_high_real_mode_segbase(void)
8435 {
8436         return enable_unrestricted_guest || emulate_invalid_guest_state;
8437 }
8438
8439 static bool vmx_mpx_supported(void)
8440 {
8441         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8442                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8443 }
8444
8445 static bool vmx_xsaves_supported(void)
8446 {
8447         return vmcs_config.cpu_based_2nd_exec_ctrl &
8448                 SECONDARY_EXEC_XSAVES;
8449 }
8450
8451 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8452 {
8453         u32 exit_intr_info;
8454         bool unblock_nmi;
8455         u8 vector;
8456         bool idtv_info_valid;
8457
8458         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8459
8460         if (cpu_has_virtual_nmis()) {
8461                 if (vmx->nmi_known_unmasked)
8462                         return;
8463                 /*
8464                  * Can't use vmx->exit_intr_info since we're not sure what
8465                  * the exit reason is.
8466                  */
8467                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8468                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8469                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8470                 /*
8471                  * SDM 3: 27.7.1.2 (September 2008)
8472                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8473                  * a guest IRET fault.
8474                  * SDM 3: 23.2.2 (September 2008)
8475                  * Bit 12 is undefined in any of the following cases:
8476                  *  If the VM exit sets the valid bit in the IDT-vectoring
8477                  *   information field.
8478                  *  If the VM exit is due to a double fault.
8479                  */
8480                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8481                     vector != DF_VECTOR && !idtv_info_valid)
8482                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8483                                       GUEST_INTR_STATE_NMI);
8484                 else
8485                         vmx->nmi_known_unmasked =
8486                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8487                                   & GUEST_INTR_STATE_NMI);
8488         } else if (unlikely(vmx->soft_vnmi_blocked))
8489                 vmx->vnmi_blocked_time +=
8490                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8491 }
8492
8493 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8494                                       u32 idt_vectoring_info,
8495                                       int instr_len_field,
8496                                       int error_code_field)
8497 {
8498         u8 vector;
8499         int type;
8500         bool idtv_info_valid;
8501
8502         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8503
8504         vcpu->arch.nmi_injected = false;
8505         kvm_clear_exception_queue(vcpu);
8506         kvm_clear_interrupt_queue(vcpu);
8507
8508         if (!idtv_info_valid)
8509                 return;
8510
8511         kvm_make_request(KVM_REQ_EVENT, vcpu);
8512
8513         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8514         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8515
8516         switch (type) {
8517         case INTR_TYPE_NMI_INTR:
8518                 vcpu->arch.nmi_injected = true;
8519                 /*
8520                  * SDM 3: 27.7.1.2 (September 2008)
8521                  * Clear bit "block by NMI" before VM entry if a NMI
8522                  * delivery faulted.
8523                  */
8524                 vmx_set_nmi_mask(vcpu, false);
8525                 break;
8526         case INTR_TYPE_SOFT_EXCEPTION:
8527                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8528                 /* fall through */
8529         case INTR_TYPE_HARD_EXCEPTION:
8530                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8531                         u32 err = vmcs_read32(error_code_field);
8532                         kvm_requeue_exception_e(vcpu, vector, err);
8533                 } else
8534                         kvm_requeue_exception(vcpu, vector);
8535                 break;
8536         case INTR_TYPE_SOFT_INTR:
8537                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8538                 /* fall through */
8539         case INTR_TYPE_EXT_INTR:
8540                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8541                 break;
8542         default:
8543                 break;
8544         }
8545 }
8546
8547 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8548 {
8549         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8550                                   VM_EXIT_INSTRUCTION_LEN,
8551                                   IDT_VECTORING_ERROR_CODE);
8552 }
8553
8554 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8555 {
8556         __vmx_complete_interrupts(vcpu,
8557                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8558                                   VM_ENTRY_INSTRUCTION_LEN,
8559                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8560
8561         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8562 }
8563
8564 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8565 {
8566         int i, nr_msrs;
8567         struct perf_guest_switch_msr *msrs;
8568
8569         msrs = perf_guest_get_msrs(&nr_msrs);
8570
8571         if (!msrs)
8572                 return;
8573
8574         for (i = 0; i < nr_msrs; i++)
8575                 if (msrs[i].host == msrs[i].guest)
8576                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8577                 else
8578                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8579                                         msrs[i].host);
8580 }
8581
8582 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8583 {
8584         struct vcpu_vmx *vmx = to_vmx(vcpu);
8585         unsigned long debugctlmsr, cr4;
8586
8587         /* Record the guest's net vcpu time for enforced NMI injections. */
8588         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8589                 vmx->entry_time = ktime_get();
8590
8591         /* Don't enter VMX if guest state is invalid, let the exit handler
8592            start emulation until we arrive back to a valid state */
8593         if (vmx->emulation_required)
8594                 return;
8595
8596         if (vmx->ple_window_dirty) {
8597                 vmx->ple_window_dirty = false;
8598                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8599         }
8600
8601         if (vmx->nested.sync_shadow_vmcs) {
8602                 copy_vmcs12_to_shadow(vmx);
8603                 vmx->nested.sync_shadow_vmcs = false;
8604         }
8605
8606         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8607                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8608         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8609                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8610
8611         cr4 = cr4_read_shadow();
8612         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8613                 vmcs_writel(HOST_CR4, cr4);
8614                 vmx->host_state.vmcs_host_cr4 = cr4;
8615         }
8616
8617         /* When single-stepping over STI and MOV SS, we must clear the
8618          * corresponding interruptibility bits in the guest state. Otherwise
8619          * vmentry fails as it then expects bit 14 (BS) in pending debug
8620          * exceptions being set, but that's not correct for the guest debugging
8621          * case. */
8622         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8623                 vmx_set_interrupt_shadow(vcpu, 0);
8624
8625         atomic_switch_perf_msrs(vmx);
8626         debugctlmsr = get_debugctlmsr();
8627
8628         vmx->__launched = vmx->loaded_vmcs->launched;
8629         asm(
8630                 /* Store host registers */
8631                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8632                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8633                 "push %%" _ASM_CX " \n\t"
8634                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8635                 "je 1f \n\t"
8636                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8637                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8638                 "1: \n\t"
8639                 /* Reload cr2 if changed */
8640                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8641                 "mov %%cr2, %%" _ASM_DX " \n\t"
8642                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8643                 "je 2f \n\t"
8644                 "mov %%" _ASM_AX", %%cr2 \n\t"
8645                 "2: \n\t"
8646                 /* Check if vmlaunch of vmresume is needed */
8647                 "cmpl $0, %c[launched](%0) \n\t"
8648                 /* Load guest registers.  Don't clobber flags. */
8649                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8650                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8651                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8652                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8653                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8654                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8655 #ifdef CONFIG_X86_64
8656                 "mov %c[r8](%0),  %%r8  \n\t"
8657                 "mov %c[r9](%0),  %%r9  \n\t"
8658                 "mov %c[r10](%0), %%r10 \n\t"
8659                 "mov %c[r11](%0), %%r11 \n\t"
8660                 "mov %c[r12](%0), %%r12 \n\t"
8661                 "mov %c[r13](%0), %%r13 \n\t"
8662                 "mov %c[r14](%0), %%r14 \n\t"
8663                 "mov %c[r15](%0), %%r15 \n\t"
8664 #endif
8665                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8666
8667                 /* Enter guest mode */
8668                 "jne 1f \n\t"
8669                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8670                 "jmp 2f \n\t"
8671                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8672                 "2: "
8673                 /* Save guest registers, load host registers, keep flags */
8674                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8675                 "pop %0 \n\t"
8676                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8677                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8678                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8679                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8680                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8681                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8682                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8683 #ifdef CONFIG_X86_64
8684                 "mov %%r8,  %c[r8](%0) \n\t"
8685                 "mov %%r9,  %c[r9](%0) \n\t"
8686                 "mov %%r10, %c[r10](%0) \n\t"
8687                 "mov %%r11, %c[r11](%0) \n\t"
8688                 "mov %%r12, %c[r12](%0) \n\t"
8689                 "mov %%r13, %c[r13](%0) \n\t"
8690                 "mov %%r14, %c[r14](%0) \n\t"
8691                 "mov %%r15, %c[r15](%0) \n\t"
8692 #endif
8693                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8694                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8695
8696                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8697                 "setbe %c[fail](%0) \n\t"
8698                 ".pushsection .rodata \n\t"
8699                 ".global vmx_return \n\t"
8700                 "vmx_return: " _ASM_PTR " 2b \n\t"
8701                 ".popsection"
8702               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8703                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8704                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8705                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8706                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8707                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8708                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8709                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8710                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8711                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8712                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8713 #ifdef CONFIG_X86_64
8714                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8715                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8716                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8717                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8718                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8719                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8720                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8721                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8722 #endif
8723                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8724                 [wordsize]"i"(sizeof(ulong))
8725               : "cc", "memory"
8726 #ifdef CONFIG_X86_64
8727                 , "rax", "rbx", "rdi", "rsi"
8728                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8729 #else
8730                 , "eax", "ebx", "edi", "esi"
8731 #endif
8732               );
8733
8734         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8735         if (debugctlmsr)
8736                 update_debugctlmsr(debugctlmsr);
8737
8738 #ifndef CONFIG_X86_64
8739         /*
8740          * The sysexit path does not restore ds/es, so we must set them to
8741          * a reasonable value ourselves.
8742          *
8743          * We can't defer this to vmx_load_host_state() since that function
8744          * may be executed in interrupt context, which saves and restore segments
8745          * around it, nullifying its effect.
8746          */
8747         loadsegment(ds, __USER_DS);
8748         loadsegment(es, __USER_DS);
8749 #endif
8750
8751         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8752                                   | (1 << VCPU_EXREG_RFLAGS)
8753                                   | (1 << VCPU_EXREG_PDPTR)
8754                                   | (1 << VCPU_EXREG_SEGMENTS)
8755                                   | (1 << VCPU_EXREG_CR3));
8756         vcpu->arch.regs_dirty = 0;
8757
8758         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8759
8760         vmx->loaded_vmcs->launched = 1;
8761
8762         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8763
8764         /*
8765          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8766          * we did not inject a still-pending event to L1 now because of
8767          * nested_run_pending, we need to re-enable this bit.
8768          */
8769         if (vmx->nested.nested_run_pending)
8770                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8771
8772         vmx->nested.nested_run_pending = 0;
8773
8774         vmx_complete_atomic_exit(vmx);
8775         vmx_recover_nmi_blocking(vmx);
8776         vmx_complete_interrupts(vmx);
8777 }
8778
8779 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8780 {
8781         struct vcpu_vmx *vmx = to_vmx(vcpu);
8782         int cpu;
8783
8784         if (vmx->loaded_vmcs == &vmx->vmcs01)
8785                 return;
8786
8787         cpu = get_cpu();
8788         vmx->loaded_vmcs = &vmx->vmcs01;
8789         vmx_vcpu_put(vcpu);
8790         vmx_vcpu_load(vcpu, cpu);
8791         vcpu->cpu = cpu;
8792         put_cpu();
8793 }
8794
8795 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8796 {
8797         struct vcpu_vmx *vmx = to_vmx(vcpu);
8798
8799         if (enable_pml)
8800                 vmx_destroy_pml_buffer(vmx);
8801         free_vpid(vmx->vpid);
8802         leave_guest_mode(vcpu);
8803         vmx_load_vmcs01(vcpu);
8804         free_nested(vmx);
8805         free_loaded_vmcs(vmx->loaded_vmcs);
8806         kfree(vmx->guest_msrs);
8807         kvm_vcpu_uninit(vcpu);
8808         kmem_cache_free(kvm_vcpu_cache, vmx);
8809 }
8810
8811 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8812 {
8813         int err;
8814         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8815         int cpu;
8816
8817         if (!vmx)
8818                 return ERR_PTR(-ENOMEM);
8819
8820         vmx->vpid = allocate_vpid();
8821
8822         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8823         if (err)
8824                 goto free_vcpu;
8825
8826         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8827         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8828                      > PAGE_SIZE);
8829
8830         err = -ENOMEM;
8831         if (!vmx->guest_msrs) {
8832                 goto uninit_vcpu;
8833         }
8834
8835         vmx->loaded_vmcs = &vmx->vmcs01;
8836         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8837         if (!vmx->loaded_vmcs->vmcs)
8838                 goto free_msrs;
8839         if (!vmm_exclusive)
8840                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8841         loaded_vmcs_init(vmx->loaded_vmcs);
8842         if (!vmm_exclusive)
8843                 kvm_cpu_vmxoff();
8844
8845         cpu = get_cpu();
8846         vmx_vcpu_load(&vmx->vcpu, cpu);
8847         vmx->vcpu.cpu = cpu;
8848         err = vmx_vcpu_setup(vmx);
8849         vmx_vcpu_put(&vmx->vcpu);
8850         put_cpu();
8851         if (err)
8852                 goto free_vmcs;
8853         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8854                 err = alloc_apic_access_page(kvm);
8855                 if (err)
8856                         goto free_vmcs;
8857         }
8858
8859         if (enable_ept) {
8860                 if (!kvm->arch.ept_identity_map_addr)
8861                         kvm->arch.ept_identity_map_addr =
8862                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8863                 err = init_rmode_identity_map(kvm);
8864                 if (err)
8865                         goto free_vmcs;
8866         }
8867
8868         if (nested) {
8869                 nested_vmx_setup_ctls_msrs(vmx);
8870                 vmx->nested.vpid02 = allocate_vpid();
8871         }
8872
8873         vmx->nested.posted_intr_nv = -1;
8874         vmx->nested.current_vmptr = -1ull;
8875         vmx->nested.current_vmcs12 = NULL;
8876
8877         /*
8878          * If PML is turned on, failure on enabling PML just results in failure
8879          * of creating the vcpu, therefore we can simplify PML logic (by
8880          * avoiding dealing with cases, such as enabling PML partially on vcpus
8881          * for the guest, etc.
8882          */
8883         if (enable_pml) {
8884                 err = vmx_create_pml_buffer(vmx);
8885                 if (err)
8886                         goto free_vmcs;
8887         }
8888
8889         return &vmx->vcpu;
8890
8891 free_vmcs:
8892         free_vpid(vmx->nested.vpid02);
8893         free_loaded_vmcs(vmx->loaded_vmcs);
8894 free_msrs:
8895         kfree(vmx->guest_msrs);
8896 uninit_vcpu:
8897         kvm_vcpu_uninit(&vmx->vcpu);
8898 free_vcpu:
8899         free_vpid(vmx->vpid);
8900         kmem_cache_free(kvm_vcpu_cache, vmx);
8901         return ERR_PTR(err);
8902 }
8903
8904 static void __init vmx_check_processor_compat(void *rtn)
8905 {
8906         struct vmcs_config vmcs_conf;
8907
8908         *(int *)rtn = 0;
8909         if (setup_vmcs_config(&vmcs_conf) < 0)
8910                 *(int *)rtn = -EIO;
8911         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8912                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8913                                 smp_processor_id());
8914                 *(int *)rtn = -EIO;
8915         }
8916 }
8917
8918 static int get_ept_level(void)
8919 {
8920         return VMX_EPT_DEFAULT_GAW + 1;
8921 }
8922
8923 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8924 {
8925         u8 cache;
8926         u64 ipat = 0;
8927
8928         /* For VT-d and EPT combination
8929          * 1. MMIO: always map as UC
8930          * 2. EPT with VT-d:
8931          *   a. VT-d without snooping control feature: can't guarantee the
8932          *      result, try to trust guest.
8933          *   b. VT-d with snooping control feature: snooping control feature of
8934          *      VT-d engine can guarantee the cache correctness. Just set it
8935          *      to WB to keep consistent with host. So the same as item 3.
8936          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8937          *    consistent with host MTRR
8938          */
8939         if (is_mmio) {
8940                 cache = MTRR_TYPE_UNCACHABLE;
8941                 goto exit;
8942         }
8943
8944         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8945                 ipat = VMX_EPT_IPAT_BIT;
8946                 cache = MTRR_TYPE_WRBACK;
8947                 goto exit;
8948         }
8949
8950         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8951                 ipat = VMX_EPT_IPAT_BIT;
8952                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8953                         cache = MTRR_TYPE_WRBACK;
8954                 else
8955                         cache = MTRR_TYPE_UNCACHABLE;
8956                 goto exit;
8957         }
8958
8959         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8960
8961 exit:
8962         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8963 }
8964
8965 static int vmx_get_lpage_level(void)
8966 {
8967         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8968                 return PT_DIRECTORY_LEVEL;
8969         else
8970                 /* For shadow and EPT supported 1GB page */
8971                 return PT_PDPE_LEVEL;
8972 }
8973
8974 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8975 {
8976         /*
8977          * These bits in the secondary execution controls field
8978          * are dynamic, the others are mostly based on the hypervisor
8979          * architecture and the guest's CPUID.  Do not touch the
8980          * dynamic bits.
8981          */
8982         u32 mask =
8983                 SECONDARY_EXEC_SHADOW_VMCS |
8984                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8985                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8986
8987         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8988
8989         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8990                      (new_ctl & ~mask) | (cur_ctl & mask));
8991 }
8992
8993 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8994 {
8995         struct kvm_cpuid_entry2 *best;
8996         struct vcpu_vmx *vmx = to_vmx(vcpu);
8997         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8998
8999         if (vmx_rdtscp_supported()) {
9000                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9001                 if (!rdtscp_enabled)
9002                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9003
9004                 if (nested) {
9005                         if (rdtscp_enabled)
9006                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9007                                         SECONDARY_EXEC_RDTSCP;
9008                         else
9009                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9010                                         ~SECONDARY_EXEC_RDTSCP;
9011                 }
9012         }
9013
9014         /* Exposing INVPCID only when PCID is exposed */
9015         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9016         if (vmx_invpcid_supported() &&
9017             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9018             !guest_cpuid_has_pcid(vcpu))) {
9019                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9020
9021                 if (best)
9022                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9023         }
9024
9025         if (cpu_has_secondary_exec_ctrls())
9026                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9027
9028         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9029                 if (guest_cpuid_has_pcommit(vcpu))
9030                         vmx->nested.nested_vmx_secondary_ctls_high |=
9031                                 SECONDARY_EXEC_PCOMMIT;
9032                 else
9033                         vmx->nested.nested_vmx_secondary_ctls_high &=
9034                                 ~SECONDARY_EXEC_PCOMMIT;
9035         }
9036 }
9037
9038 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9039 {
9040         if (func == 1 && nested)
9041                 entry->ecx |= bit(X86_FEATURE_VMX);
9042 }
9043
9044 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9045                 struct x86_exception *fault)
9046 {
9047         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9048         u32 exit_reason;
9049
9050         if (fault->error_code & PFERR_RSVD_MASK)
9051                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9052         else
9053                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9054         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9055         vmcs12->guest_physical_address = fault->address;
9056 }
9057
9058 /* Callbacks for nested_ept_init_mmu_context: */
9059
9060 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9061 {
9062         /* return the page table to be shadowed - in our case, EPT12 */
9063         return get_vmcs12(vcpu)->ept_pointer;
9064 }
9065
9066 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9067 {
9068         WARN_ON(mmu_is_nested(vcpu));
9069         kvm_init_shadow_ept_mmu(vcpu,
9070                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9071                         VMX_EPT_EXECUTE_ONLY_BIT);
9072         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9073         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9074         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9075
9076         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9077 }
9078
9079 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9080 {
9081         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9082 }
9083
9084 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9085                                             u16 error_code)
9086 {
9087         bool inequality, bit;
9088
9089         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9090         inequality =
9091                 (error_code & vmcs12->page_fault_error_code_mask) !=
9092                  vmcs12->page_fault_error_code_match;
9093         return inequality ^ bit;
9094 }
9095
9096 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9097                 struct x86_exception *fault)
9098 {
9099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9100
9101         WARN_ON(!is_guest_mode(vcpu));
9102
9103         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9104                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9105                                   vmcs_read32(VM_EXIT_INTR_INFO),
9106                                   vmcs_readl(EXIT_QUALIFICATION));
9107         else
9108                 kvm_inject_page_fault(vcpu, fault);
9109 }
9110
9111 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9112                                         struct vmcs12 *vmcs12)
9113 {
9114         struct vcpu_vmx *vmx = to_vmx(vcpu);
9115         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9116
9117         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9118                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9119                     vmcs12->apic_access_addr >> maxphyaddr)
9120                         return false;
9121
9122                 /*
9123                  * Translate L1 physical address to host physical
9124                  * address for vmcs02. Keep the page pinned, so this
9125                  * physical address remains valid. We keep a reference
9126                  * to it so we can release it later.
9127                  */
9128                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9129                         nested_release_page(vmx->nested.apic_access_page);
9130                 vmx->nested.apic_access_page =
9131                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9132         }
9133
9134         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9135                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9136                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9137                         return false;
9138
9139                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9140                         nested_release_page(vmx->nested.virtual_apic_page);
9141                 vmx->nested.virtual_apic_page =
9142                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9143
9144                 /*
9145                  * Failing the vm entry is _not_ what the processor does
9146                  * but it's basically the only possibility we have.
9147                  * We could still enter the guest if CR8 load exits are
9148                  * enabled, CR8 store exits are enabled, and virtualize APIC
9149                  * access is disabled; in this case the processor would never
9150                  * use the TPR shadow and we could simply clear the bit from
9151                  * the execution control.  But such a configuration is useless,
9152                  * so let's keep the code simple.
9153                  */
9154                 if (!vmx->nested.virtual_apic_page)
9155                         return false;
9156         }
9157
9158         if (nested_cpu_has_posted_intr(vmcs12)) {
9159                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9160                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9161                         return false;
9162
9163                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9164                         kunmap(vmx->nested.pi_desc_page);
9165                         nested_release_page(vmx->nested.pi_desc_page);
9166                 }
9167                 vmx->nested.pi_desc_page =
9168                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9169                 if (!vmx->nested.pi_desc_page)
9170                         return false;
9171
9172                 vmx->nested.pi_desc =
9173                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9174                 if (!vmx->nested.pi_desc) {
9175                         nested_release_page_clean(vmx->nested.pi_desc_page);
9176                         return false;
9177                 }
9178                 vmx->nested.pi_desc =
9179                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9180                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9181                         (PAGE_SIZE - 1)));
9182         }
9183
9184         return true;
9185 }
9186
9187 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9188 {
9189         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9190         struct vcpu_vmx *vmx = to_vmx(vcpu);
9191
9192         if (vcpu->arch.virtual_tsc_khz == 0)
9193                 return;
9194
9195         /* Make sure short timeouts reliably trigger an immediate vmexit.
9196          * hrtimer_start does not guarantee this. */
9197         if (preemption_timeout <= 1) {
9198                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9199                 return;
9200         }
9201
9202         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9203         preemption_timeout *= 1000000;
9204         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9205         hrtimer_start(&vmx->nested.preemption_timer,
9206                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9207 }
9208
9209 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9210                                                 struct vmcs12 *vmcs12)
9211 {
9212         int maxphyaddr;
9213         u64 addr;
9214
9215         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9216                 return 0;
9217
9218         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9219                 WARN_ON(1);
9220                 return -EINVAL;
9221         }
9222         maxphyaddr = cpuid_maxphyaddr(vcpu);
9223
9224         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9225            ((addr + PAGE_SIZE) >> maxphyaddr))
9226                 return -EINVAL;
9227
9228         return 0;
9229 }
9230
9231 /*
9232  * Merge L0's and L1's MSR bitmap, return false to indicate that
9233  * we do not use the hardware.
9234  */
9235 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9236                                                struct vmcs12 *vmcs12)
9237 {
9238         int msr;
9239         struct page *page;
9240         unsigned long *msr_bitmap;
9241
9242         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9243                 return false;
9244
9245         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9246         if (!page) {
9247                 WARN_ON(1);
9248                 return false;
9249         }
9250         msr_bitmap = (unsigned long *)kmap(page);
9251         if (!msr_bitmap) {
9252                 nested_release_page_clean(page);
9253                 WARN_ON(1);
9254                 return false;
9255         }
9256
9257         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9258                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9259                         for (msr = 0x800; msr <= 0x8ff; msr++)
9260                                 nested_vmx_disable_intercept_for_msr(
9261                                         msr_bitmap,
9262                                         vmx_msr_bitmap_nested,
9263                                         msr, MSR_TYPE_R);
9264                 /* TPR is allowed */
9265                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9266                                 vmx_msr_bitmap_nested,
9267                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9268                                 MSR_TYPE_R | MSR_TYPE_W);
9269                 if (nested_cpu_has_vid(vmcs12)) {
9270                         /* EOI and self-IPI are allowed */
9271                         nested_vmx_disable_intercept_for_msr(
9272                                 msr_bitmap,
9273                                 vmx_msr_bitmap_nested,
9274                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9275                                 MSR_TYPE_W);
9276                         nested_vmx_disable_intercept_for_msr(
9277                                 msr_bitmap,
9278                                 vmx_msr_bitmap_nested,
9279                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9280                                 MSR_TYPE_W);
9281                 }
9282         } else {
9283                 /*
9284                  * Enable reading intercept of all the x2apic
9285                  * MSRs. We should not rely on vmcs12 to do any
9286                  * optimizations here, it may have been modified
9287                  * by L1.
9288                  */
9289                 for (msr = 0x800; msr <= 0x8ff; msr++)
9290                         __vmx_enable_intercept_for_msr(
9291                                 vmx_msr_bitmap_nested,
9292                                 msr,
9293                                 MSR_TYPE_R);
9294
9295                 __vmx_enable_intercept_for_msr(
9296                                 vmx_msr_bitmap_nested,
9297                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9298                                 MSR_TYPE_W);
9299                 __vmx_enable_intercept_for_msr(
9300                                 vmx_msr_bitmap_nested,
9301                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9302                                 MSR_TYPE_W);
9303                 __vmx_enable_intercept_for_msr(
9304                                 vmx_msr_bitmap_nested,
9305                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9306                                 MSR_TYPE_W);
9307         }
9308         kunmap(page);
9309         nested_release_page_clean(page);
9310
9311         return true;
9312 }
9313
9314 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9315                                            struct vmcs12 *vmcs12)
9316 {
9317         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9318             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9319             !nested_cpu_has_vid(vmcs12) &&
9320             !nested_cpu_has_posted_intr(vmcs12))
9321                 return 0;
9322
9323         /*
9324          * If virtualize x2apic mode is enabled,
9325          * virtualize apic access must be disabled.
9326          */
9327         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9328             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9329                 return -EINVAL;
9330
9331         /*
9332          * If virtual interrupt delivery is enabled,
9333          * we must exit on external interrupts.
9334          */
9335         if (nested_cpu_has_vid(vmcs12) &&
9336            !nested_exit_on_intr(vcpu))
9337                 return -EINVAL;
9338
9339         /*
9340          * bits 15:8 should be zero in posted_intr_nv,
9341          * the descriptor address has been already checked
9342          * in nested_get_vmcs12_pages.
9343          */
9344         if (nested_cpu_has_posted_intr(vmcs12) &&
9345            (!nested_cpu_has_vid(vmcs12) ||
9346             !nested_exit_intr_ack_set(vcpu) ||
9347             vmcs12->posted_intr_nv & 0xff00))
9348                 return -EINVAL;
9349
9350         /* tpr shadow is needed by all apicv features. */
9351         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9352                 return -EINVAL;
9353
9354         return 0;
9355 }
9356
9357 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9358                                        unsigned long count_field,
9359                                        unsigned long addr_field)
9360 {
9361         int maxphyaddr;
9362         u64 count, addr;
9363
9364         if (vmcs12_read_any(vcpu, count_field, &count) ||
9365             vmcs12_read_any(vcpu, addr_field, &addr)) {
9366                 WARN_ON(1);
9367                 return -EINVAL;
9368         }
9369         if (count == 0)
9370                 return 0;
9371         maxphyaddr = cpuid_maxphyaddr(vcpu);
9372         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9373             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9374                 pr_warn_ratelimited(
9375                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9376                         addr_field, maxphyaddr, count, addr);
9377                 return -EINVAL;
9378         }
9379         return 0;
9380 }
9381
9382 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9383                                                 struct vmcs12 *vmcs12)
9384 {
9385         if (vmcs12->vm_exit_msr_load_count == 0 &&
9386             vmcs12->vm_exit_msr_store_count == 0 &&
9387             vmcs12->vm_entry_msr_load_count == 0)
9388                 return 0; /* Fast path */
9389         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9390                                         VM_EXIT_MSR_LOAD_ADDR) ||
9391             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9392                                         VM_EXIT_MSR_STORE_ADDR) ||
9393             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9394                                         VM_ENTRY_MSR_LOAD_ADDR))
9395                 return -EINVAL;
9396         return 0;
9397 }
9398
9399 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9400                                        struct vmx_msr_entry *e)
9401 {
9402         /* x2APIC MSR accesses are not allowed */
9403         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9404                 return -EINVAL;
9405         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9406             e->index == MSR_IA32_UCODE_REV)
9407                 return -EINVAL;
9408         if (e->reserved != 0)
9409                 return -EINVAL;
9410         return 0;
9411 }
9412
9413 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9414                                      struct vmx_msr_entry *e)
9415 {
9416         if (e->index == MSR_FS_BASE ||
9417             e->index == MSR_GS_BASE ||
9418             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9419             nested_vmx_msr_check_common(vcpu, e))
9420                 return -EINVAL;
9421         return 0;
9422 }
9423
9424 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9425                                       struct vmx_msr_entry *e)
9426 {
9427         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9428             nested_vmx_msr_check_common(vcpu, e))
9429                 return -EINVAL;
9430         return 0;
9431 }
9432
9433 /*
9434  * Load guest's/host's msr at nested entry/exit.
9435  * return 0 for success, entry index for failure.
9436  */
9437 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9438 {
9439         u32 i;
9440         struct vmx_msr_entry e;
9441         struct msr_data msr;
9442
9443         msr.host_initiated = false;
9444         for (i = 0; i < count; i++) {
9445                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9446                                         &e, sizeof(e))) {
9447                         pr_warn_ratelimited(
9448                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9449                                 __func__, i, gpa + i * sizeof(e));
9450                         goto fail;
9451                 }
9452                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9453                         pr_warn_ratelimited(
9454                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9455                                 __func__, i, e.index, e.reserved);
9456                         goto fail;
9457                 }
9458                 msr.index = e.index;
9459                 msr.data = e.value;
9460                 if (kvm_set_msr(vcpu, &msr)) {
9461                         pr_warn_ratelimited(
9462                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9463                                 __func__, i, e.index, e.value);
9464                         goto fail;
9465                 }
9466         }
9467         return 0;
9468 fail:
9469         return i + 1;
9470 }
9471
9472 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9473 {
9474         u32 i;
9475         struct vmx_msr_entry e;
9476
9477         for (i = 0; i < count; i++) {
9478                 struct msr_data msr_info;
9479                 if (kvm_vcpu_read_guest(vcpu,
9480                                         gpa + i * sizeof(e),
9481                                         &e, 2 * sizeof(u32))) {
9482                         pr_warn_ratelimited(
9483                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9484                                 __func__, i, gpa + i * sizeof(e));
9485                         return -EINVAL;
9486                 }
9487                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9488                         pr_warn_ratelimited(
9489                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9490                                 __func__, i, e.index, e.reserved);
9491                         return -EINVAL;
9492                 }
9493                 msr_info.host_initiated = false;
9494                 msr_info.index = e.index;
9495                 if (kvm_get_msr(vcpu, &msr_info)) {
9496                         pr_warn_ratelimited(
9497                                 "%s cannot read MSR (%u, 0x%x)\n",
9498                                 __func__, i, e.index);
9499                         return -EINVAL;
9500                 }
9501                 if (kvm_vcpu_write_guest(vcpu,
9502                                          gpa + i * sizeof(e) +
9503                                              offsetof(struct vmx_msr_entry, value),
9504                                          &msr_info.data, sizeof(msr_info.data))) {
9505                         pr_warn_ratelimited(
9506                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9507                                 __func__, i, e.index, msr_info.data);
9508                         return -EINVAL;
9509                 }
9510         }
9511         return 0;
9512 }
9513
9514 /*
9515  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9516  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9517  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9518  * guest in a way that will both be appropriate to L1's requests, and our
9519  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9520  * function also has additional necessary side-effects, like setting various
9521  * vcpu->arch fields.
9522  */
9523 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9524 {
9525         struct vcpu_vmx *vmx = to_vmx(vcpu);
9526         u32 exec_control;
9527
9528         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9529         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9530         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9531         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9532         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9533         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9534         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9535         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9536         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9537         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9538         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9539         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9540         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9541         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9542         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9543         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9544         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9545         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9546         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9547         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9548         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9549         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9550         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9551         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9552         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9553         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9554         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9555         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9556         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9557         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9558         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9559         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9560         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9561         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9562         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9563         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9564
9565         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9566                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9567                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9568         } else {
9569                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9570                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9571         }
9572         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9573                 vmcs12->vm_entry_intr_info_field);
9574         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9575                 vmcs12->vm_entry_exception_error_code);
9576         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9577                 vmcs12->vm_entry_instruction_len);
9578         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9579                 vmcs12->guest_interruptibility_info);
9580         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9581         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9582         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9583                 vmcs12->guest_pending_dbg_exceptions);
9584         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9585         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9586
9587         if (nested_cpu_has_xsaves(vmcs12))
9588                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9589         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9590
9591         exec_control = vmcs12->pin_based_vm_exec_control;
9592         exec_control |= vmcs_config.pin_based_exec_ctrl;
9593         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9594
9595         if (nested_cpu_has_posted_intr(vmcs12)) {
9596                 /*
9597                  * Note that we use L0's vector here and in
9598                  * vmx_deliver_nested_posted_interrupt.
9599                  */
9600                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9601                 vmx->nested.pi_pending = false;
9602                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9603                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9604                         page_to_phys(vmx->nested.pi_desc_page) +
9605                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9606                         (PAGE_SIZE - 1)));
9607         } else
9608                 exec_control &= ~PIN_BASED_POSTED_INTR;
9609
9610         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9611
9612         vmx->nested.preemption_timer_expired = false;
9613         if (nested_cpu_has_preemption_timer(vmcs12))
9614                 vmx_start_preemption_timer(vcpu);
9615
9616         /*
9617          * Whether page-faults are trapped is determined by a combination of
9618          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9619          * If enable_ept, L0 doesn't care about page faults and we should
9620          * set all of these to L1's desires. However, if !enable_ept, L0 does
9621          * care about (at least some) page faults, and because it is not easy
9622          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9623          * to exit on each and every L2 page fault. This is done by setting
9624          * MASK=MATCH=0 and (see below) EB.PF=1.
9625          * Note that below we don't need special code to set EB.PF beyond the
9626          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9627          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9628          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9629          *
9630          * A problem with this approach (when !enable_ept) is that L1 may be
9631          * injected with more page faults than it asked for. This could have
9632          * caused problems, but in practice existing hypervisors don't care.
9633          * To fix this, we will need to emulate the PFEC checking (on the L1
9634          * page tables), using walk_addr(), when injecting PFs to L1.
9635          */
9636         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9637                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9638         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9639                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9640
9641         if (cpu_has_secondary_exec_ctrls()) {
9642                 exec_control = vmx_secondary_exec_control(vmx);
9643
9644                 /* Take the following fields only from vmcs12 */
9645                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9646                                   SECONDARY_EXEC_RDTSCP |
9647                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9648                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9649                                   SECONDARY_EXEC_PCOMMIT);
9650                 if (nested_cpu_has(vmcs12,
9651                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9652                         exec_control |= vmcs12->secondary_vm_exec_control;
9653
9654                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9655                         /*
9656                          * If translation failed, no matter: This feature asks
9657                          * to exit when accessing the given address, and if it
9658                          * can never be accessed, this feature won't do
9659                          * anything anyway.
9660                          */
9661                         if (!vmx->nested.apic_access_page)
9662                                 exec_control &=
9663                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9664                         else
9665                                 vmcs_write64(APIC_ACCESS_ADDR,
9666                                   page_to_phys(vmx->nested.apic_access_page));
9667                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9668                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9669                         exec_control |=
9670                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9671                         kvm_vcpu_reload_apic_access_page(vcpu);
9672                 }
9673
9674                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9675                         vmcs_write64(EOI_EXIT_BITMAP0,
9676                                 vmcs12->eoi_exit_bitmap0);
9677                         vmcs_write64(EOI_EXIT_BITMAP1,
9678                                 vmcs12->eoi_exit_bitmap1);
9679                         vmcs_write64(EOI_EXIT_BITMAP2,
9680                                 vmcs12->eoi_exit_bitmap2);
9681                         vmcs_write64(EOI_EXIT_BITMAP3,
9682                                 vmcs12->eoi_exit_bitmap3);
9683                         vmcs_write16(GUEST_INTR_STATUS,
9684                                 vmcs12->guest_intr_status);
9685                 }
9686
9687                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9688         }
9689
9690
9691         /*
9692          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9693          * Some constant fields are set here by vmx_set_constant_host_state().
9694          * Other fields are different per CPU, and will be set later when
9695          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9696          */
9697         vmx_set_constant_host_state(vmx);
9698
9699         /*
9700          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9701          * entry, but only if the current (host) sp changed from the value
9702          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9703          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9704          * here we just force the write to happen on entry.
9705          */
9706         vmx->host_rsp = 0;
9707
9708         exec_control = vmx_exec_control(vmx); /* L0's desires */
9709         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9710         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9711         exec_control &= ~CPU_BASED_TPR_SHADOW;
9712         exec_control |= vmcs12->cpu_based_vm_exec_control;
9713
9714         if (exec_control & CPU_BASED_TPR_SHADOW) {
9715                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9716                                 page_to_phys(vmx->nested.virtual_apic_page));
9717                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9718         }
9719
9720         if (cpu_has_vmx_msr_bitmap() &&
9721             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9722                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9723                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9724         } else
9725                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9726
9727         /*
9728          * Merging of IO bitmap not currently supported.
9729          * Rather, exit every time.
9730          */
9731         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9732         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9733
9734         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9735
9736         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9737          * bitwise-or of what L1 wants to trap for L2, and what we want to
9738          * trap. Note that CR0.TS also needs updating - we do this later.
9739          */
9740         update_exception_bitmap(vcpu);
9741         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9742         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9743
9744         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9745          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9746          * bits are further modified by vmx_set_efer() below.
9747          */
9748         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9749
9750         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9751          * emulated by vmx_set_efer(), below.
9752          */
9753         vm_entry_controls_init(vmx,
9754                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9755                         ~VM_ENTRY_IA32E_MODE) |
9756                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9757
9758         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9759                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9760                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9761         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9762                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9763
9764
9765         set_cr4_guest_host_mask(vmx);
9766
9767         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9768                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9769
9770         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9771                 vmcs_write64(TSC_OFFSET,
9772                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9773         else
9774                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9775
9776         if (enable_vpid) {
9777                 /*
9778                  * There is no direct mapping between vpid02 and vpid12, the
9779                  * vpid02 is per-vCPU for L0 and reused while the value of
9780                  * vpid12 is changed w/ one invvpid during nested vmentry.
9781                  * The vpid12 is allocated by L1 for L2, so it will not
9782                  * influence global bitmap(for vpid01 and vpid02 allocation)
9783                  * even if spawn a lot of nested vCPUs.
9784                  */
9785                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9786                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9787                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9788                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9789                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9790                         }
9791                 } else {
9792                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9793                         vmx_flush_tlb(vcpu);
9794                 }
9795
9796         }
9797
9798         if (nested_cpu_has_ept(vmcs12)) {
9799                 kvm_mmu_unload(vcpu);
9800                 nested_ept_init_mmu_context(vcpu);
9801         }
9802
9803         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9804                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9805         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9806                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9807         else
9808                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9809         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9810         vmx_set_efer(vcpu, vcpu->arch.efer);
9811
9812         /*
9813          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9814          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9815          * The CR0_READ_SHADOW is what L2 should have expected to read given
9816          * the specifications by L1; It's not enough to take
9817          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9818          * have more bits than L1 expected.
9819          */
9820         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9821         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9822
9823         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9824         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9825
9826         /* shadow page tables on either EPT or shadow page tables */
9827         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9828         kvm_mmu_reset_context(vcpu);
9829
9830         if (!enable_ept)
9831                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9832
9833         /*
9834          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9835          */
9836         if (enable_ept) {
9837                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9838                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9839                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9840                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9841         }
9842
9843         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9844         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9845 }
9846
9847 /*
9848  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9849  * for running an L2 nested guest.
9850  */
9851 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9852 {
9853         struct vmcs12 *vmcs12;
9854         struct vcpu_vmx *vmx = to_vmx(vcpu);
9855         int cpu;
9856         struct loaded_vmcs *vmcs02;
9857         bool ia32e;
9858         u32 msr_entry_idx;
9859
9860         if (!nested_vmx_check_permission(vcpu) ||
9861             !nested_vmx_check_vmcs12(vcpu))
9862                 return 1;
9863
9864         skip_emulated_instruction(vcpu);
9865         vmcs12 = get_vmcs12(vcpu);
9866
9867         if (enable_shadow_vmcs)
9868                 copy_shadow_to_vmcs12(vmx);
9869
9870         /*
9871          * The nested entry process starts with enforcing various prerequisites
9872          * on vmcs12 as required by the Intel SDM, and act appropriately when
9873          * they fail: As the SDM explains, some conditions should cause the
9874          * instruction to fail, while others will cause the instruction to seem
9875          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9876          * To speed up the normal (success) code path, we should avoid checking
9877          * for misconfigurations which will anyway be caught by the processor
9878          * when using the merged vmcs02.
9879          */
9880         if (vmcs12->launch_state == launch) {
9881                 nested_vmx_failValid(vcpu,
9882                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9883                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9884                 return 1;
9885         }
9886
9887         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9888             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9889                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9890                 return 1;
9891         }
9892
9893         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9894                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9895                 return 1;
9896         }
9897
9898         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9899                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9900                 return 1;
9901         }
9902
9903         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9904                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9905                 return 1;
9906         }
9907
9908         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9909                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9910                 return 1;
9911         }
9912
9913         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9914                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9915                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9916             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9917                                 vmx->nested.nested_vmx_secondary_ctls_low,
9918                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9919             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9920                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9921                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9922             !vmx_control_verify(vmcs12->vm_exit_controls,
9923                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9924                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9925             !vmx_control_verify(vmcs12->vm_entry_controls,
9926                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9927                                 vmx->nested.nested_vmx_entry_ctls_high))
9928         {
9929                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9930                 return 1;
9931         }
9932
9933         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9934             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9935                 nested_vmx_failValid(vcpu,
9936                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9937                 return 1;
9938         }
9939
9940         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9941             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9942                 nested_vmx_entry_failure(vcpu, vmcs12,
9943                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9944                 return 1;
9945         }
9946         if (vmcs12->vmcs_link_pointer != -1ull) {
9947                 nested_vmx_entry_failure(vcpu, vmcs12,
9948                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9949                 return 1;
9950         }
9951
9952         /*
9953          * If the load IA32_EFER VM-entry control is 1, the following checks
9954          * are performed on the field for the IA32_EFER MSR:
9955          * - Bits reserved in the IA32_EFER MSR must be 0.
9956          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9957          *   the IA-32e mode guest VM-exit control. It must also be identical
9958          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9959          *   CR0.PG) is 1.
9960          */
9961         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9962                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9963                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9964                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9965                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9966                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9967                         nested_vmx_entry_failure(vcpu, vmcs12,
9968                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9969                         return 1;
9970                 }
9971         }
9972
9973         /*
9974          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9975          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9976          * the values of the LMA and LME bits in the field must each be that of
9977          * the host address-space size VM-exit control.
9978          */
9979         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9980                 ia32e = (vmcs12->vm_exit_controls &
9981                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9982                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9983                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9984                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9985                         nested_vmx_entry_failure(vcpu, vmcs12,
9986                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9987                         return 1;
9988                 }
9989         }
9990
9991         /*
9992          * We're finally done with prerequisite checking, and can start with
9993          * the nested entry.
9994          */
9995
9996         vmcs02 = nested_get_current_vmcs02(vmx);
9997         if (!vmcs02)
9998                 return -ENOMEM;
9999
10000         enter_guest_mode(vcpu);
10001
10002         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10003
10004         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10005                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10006
10007         cpu = get_cpu();
10008         vmx->loaded_vmcs = vmcs02;
10009         vmx_vcpu_put(vcpu);
10010         vmx_vcpu_load(vcpu, cpu);
10011         vcpu->cpu = cpu;
10012         put_cpu();
10013
10014         vmx_segment_cache_clear(vmx);
10015
10016         prepare_vmcs02(vcpu, vmcs12);
10017
10018         msr_entry_idx = nested_vmx_load_msr(vcpu,
10019                                             vmcs12->vm_entry_msr_load_addr,
10020                                             vmcs12->vm_entry_msr_load_count);
10021         if (msr_entry_idx) {
10022                 leave_guest_mode(vcpu);
10023                 vmx_load_vmcs01(vcpu);
10024                 nested_vmx_entry_failure(vcpu, vmcs12,
10025                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10026                 return 1;
10027         }
10028
10029         vmcs12->launch_state = 1;
10030
10031         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10032                 return kvm_vcpu_halt(vcpu);
10033
10034         vmx->nested.nested_run_pending = 1;
10035
10036         /*
10037          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10038          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10039          * returned as far as L1 is concerned. It will only return (and set
10040          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10041          */
10042         return 1;
10043 }
10044
10045 /*
10046  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10047  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10048  * This function returns the new value we should put in vmcs12.guest_cr0.
10049  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10050  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10051  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10052  *     didn't trap the bit, because if L1 did, so would L0).
10053  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10054  *     been modified by L2, and L1 knows it. So just leave the old value of
10055  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10056  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10057  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10058  *     changed these bits, and therefore they need to be updated, but L0
10059  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10060  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10061  */
10062 static inline unsigned long
10063 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10064 {
10065         return
10066         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10067         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10068         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10069                         vcpu->arch.cr0_guest_owned_bits));
10070 }
10071
10072 static inline unsigned long
10073 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10074 {
10075         return
10076         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10077         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10078         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10079                         vcpu->arch.cr4_guest_owned_bits));
10080 }
10081
10082 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10083                                        struct vmcs12 *vmcs12)
10084 {
10085         u32 idt_vectoring;
10086         unsigned int nr;
10087
10088         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10089                 nr = vcpu->arch.exception.nr;
10090                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10091
10092                 if (kvm_exception_is_soft(nr)) {
10093                         vmcs12->vm_exit_instruction_len =
10094                                 vcpu->arch.event_exit_inst_len;
10095                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10096                 } else
10097                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10098
10099                 if (vcpu->arch.exception.has_error_code) {
10100                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10101                         vmcs12->idt_vectoring_error_code =
10102                                 vcpu->arch.exception.error_code;
10103                 }
10104
10105                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10106         } else if (vcpu->arch.nmi_injected) {
10107                 vmcs12->idt_vectoring_info_field =
10108                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10109         } else if (vcpu->arch.interrupt.pending) {
10110                 nr = vcpu->arch.interrupt.nr;
10111                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10112
10113                 if (vcpu->arch.interrupt.soft) {
10114                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10115                         vmcs12->vm_entry_instruction_len =
10116                                 vcpu->arch.event_exit_inst_len;
10117                 } else
10118                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10119
10120                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10121         }
10122 }
10123
10124 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10125 {
10126         struct vcpu_vmx *vmx = to_vmx(vcpu);
10127
10128         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10129             vmx->nested.preemption_timer_expired) {
10130                 if (vmx->nested.nested_run_pending)
10131                         return -EBUSY;
10132                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10133                 return 0;
10134         }
10135
10136         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10137                 if (vmx->nested.nested_run_pending ||
10138                     vcpu->arch.interrupt.pending)
10139                         return -EBUSY;
10140                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10141                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10142                                   INTR_INFO_VALID_MASK, 0);
10143                 /*
10144                  * The NMI-triggered VM exit counts as injection:
10145                  * clear this one and block further NMIs.
10146                  */
10147                 vcpu->arch.nmi_pending = 0;
10148                 vmx_set_nmi_mask(vcpu, true);
10149                 return 0;
10150         }
10151
10152         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10153             nested_exit_on_intr(vcpu)) {
10154                 if (vmx->nested.nested_run_pending)
10155                         return -EBUSY;
10156                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10157                 return 0;
10158         }
10159
10160         return vmx_complete_nested_posted_interrupt(vcpu);
10161 }
10162
10163 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10164 {
10165         ktime_t remaining =
10166                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10167         u64 value;
10168
10169         if (ktime_to_ns(remaining) <= 0)
10170                 return 0;
10171
10172         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10173         do_div(value, 1000000);
10174         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10175 }
10176
10177 /*
10178  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10179  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10180  * and this function updates it to reflect the changes to the guest state while
10181  * L2 was running (and perhaps made some exits which were handled directly by L0
10182  * without going back to L1), and to reflect the exit reason.
10183  * Note that we do not have to copy here all VMCS fields, just those that
10184  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10185  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10186  * which already writes to vmcs12 directly.
10187  */
10188 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10189                            u32 exit_reason, u32 exit_intr_info,
10190                            unsigned long exit_qualification)
10191 {
10192         /* update guest state fields: */
10193         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10194         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10195
10196         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10197         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10198         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10199
10200         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10201         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10202         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10203         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10204         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10205         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10206         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10207         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10208         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10209         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10210         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10211         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10212         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10213         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10214         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10215         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10216         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10217         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10218         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10219         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10220         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10221         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10222         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10223         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10224         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10225         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10226         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10227         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10228         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10229         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10230         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10231         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10232         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10233         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10234         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10235         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10236
10237         vmcs12->guest_interruptibility_info =
10238                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10239         vmcs12->guest_pending_dbg_exceptions =
10240                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10241         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10242                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10243         else
10244                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10245
10246         if (nested_cpu_has_preemption_timer(vmcs12)) {
10247                 if (vmcs12->vm_exit_controls &
10248                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10249                         vmcs12->vmx_preemption_timer_value =
10250                                 vmx_get_preemption_timer_value(vcpu);
10251                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10252         }
10253
10254         /*
10255          * In some cases (usually, nested EPT), L2 is allowed to change its
10256          * own CR3 without exiting. If it has changed it, we must keep it.
10257          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10258          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10259          *
10260          * Additionally, restore L2's PDPTR to vmcs12.
10261          */
10262         if (enable_ept) {
10263                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10264                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10265                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10266                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10267                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10268         }
10269
10270         if (nested_cpu_has_vid(vmcs12))
10271                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10272
10273         vmcs12->vm_entry_controls =
10274                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10275                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10276
10277         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10278                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10279                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10280         }
10281
10282         /* TODO: These cannot have changed unless we have MSR bitmaps and
10283          * the relevant bit asks not to trap the change */
10284         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10285                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10286         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10287                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10288         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10289         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10290         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10291         if (kvm_mpx_supported())
10292                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10293         if (nested_cpu_has_xsaves(vmcs12))
10294                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10295
10296         /* update exit information fields: */
10297
10298         vmcs12->vm_exit_reason = exit_reason;
10299         vmcs12->exit_qualification = exit_qualification;
10300
10301         vmcs12->vm_exit_intr_info = exit_intr_info;
10302         if ((vmcs12->vm_exit_intr_info &
10303              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10304             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10305                 vmcs12->vm_exit_intr_error_code =
10306                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10307         vmcs12->idt_vectoring_info_field = 0;
10308         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10309         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10310
10311         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10312                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10313                  * instead of reading the real value. */
10314                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10315
10316                 /*
10317                  * Transfer the event that L0 or L1 may wanted to inject into
10318                  * L2 to IDT_VECTORING_INFO_FIELD.
10319                  */
10320                 vmcs12_save_pending_event(vcpu, vmcs12);
10321         }
10322
10323         /*
10324          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10325          * preserved above and would only end up incorrectly in L1.
10326          */
10327         vcpu->arch.nmi_injected = false;
10328         kvm_clear_exception_queue(vcpu);
10329         kvm_clear_interrupt_queue(vcpu);
10330 }
10331
10332 /*
10333  * A part of what we need to when the nested L2 guest exits and we want to
10334  * run its L1 parent, is to reset L1's guest state to the host state specified
10335  * in vmcs12.
10336  * This function is to be called not only on normal nested exit, but also on
10337  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10338  * Failures During or After Loading Guest State").
10339  * This function should be called when the active VMCS is L1's (vmcs01).
10340  */
10341 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10342                                    struct vmcs12 *vmcs12)
10343 {
10344         struct kvm_segment seg;
10345
10346         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10347                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10348         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10349                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10350         else
10351                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10352         vmx_set_efer(vcpu, vcpu->arch.efer);
10353
10354         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10355         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10356         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10357         /*
10358          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10359          * actually changed, because it depends on the current state of
10360          * fpu_active (which may have changed).
10361          * Note that vmx_set_cr0 refers to efer set above.
10362          */
10363         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10364         /*
10365          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10366          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10367          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10368          */
10369         update_exception_bitmap(vcpu);
10370         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10371         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10372
10373         /*
10374          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10375          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10376          */
10377         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10378         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10379
10380         nested_ept_uninit_mmu_context(vcpu);
10381
10382         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10383         kvm_mmu_reset_context(vcpu);
10384
10385         if (!enable_ept)
10386                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10387
10388         if (enable_vpid) {
10389                 /*
10390                  * Trivially support vpid by letting L2s share their parent
10391                  * L1's vpid. TODO: move to a more elaborate solution, giving
10392                  * each L2 its own vpid and exposing the vpid feature to L1.
10393                  */
10394                 vmx_flush_tlb(vcpu);
10395         }
10396
10397
10398         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10399         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10400         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10401         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10402         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10403
10404         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10405         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10406                 vmcs_write64(GUEST_BNDCFGS, 0);
10407
10408         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10409                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10410                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10411         }
10412         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10413                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10414                         vmcs12->host_ia32_perf_global_ctrl);
10415
10416         /* Set L1 segment info according to Intel SDM
10417             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10418         seg = (struct kvm_segment) {
10419                 .base = 0,
10420                 .limit = 0xFFFFFFFF,
10421                 .selector = vmcs12->host_cs_selector,
10422                 .type = 11,
10423                 .present = 1,
10424                 .s = 1,
10425                 .g = 1
10426         };
10427         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10428                 seg.l = 1;
10429         else
10430                 seg.db = 1;
10431         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10432         seg = (struct kvm_segment) {
10433                 .base = 0,
10434                 .limit = 0xFFFFFFFF,
10435                 .type = 3,
10436                 .present = 1,
10437                 .s = 1,
10438                 .db = 1,
10439                 .g = 1
10440         };
10441         seg.selector = vmcs12->host_ds_selector;
10442         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10443         seg.selector = vmcs12->host_es_selector;
10444         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10445         seg.selector = vmcs12->host_ss_selector;
10446         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10447         seg.selector = vmcs12->host_fs_selector;
10448         seg.base = vmcs12->host_fs_base;
10449         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10450         seg.selector = vmcs12->host_gs_selector;
10451         seg.base = vmcs12->host_gs_base;
10452         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10453         seg = (struct kvm_segment) {
10454                 .base = vmcs12->host_tr_base,
10455                 .limit = 0x67,
10456                 .selector = vmcs12->host_tr_selector,
10457                 .type = 11,
10458                 .present = 1
10459         };
10460         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10461
10462         kvm_set_dr(vcpu, 7, 0x400);
10463         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10464
10465         if (cpu_has_vmx_msr_bitmap())
10466                 vmx_set_msr_bitmap(vcpu);
10467
10468         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10469                                 vmcs12->vm_exit_msr_load_count))
10470                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10471 }
10472
10473 /*
10474  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10475  * and modify vmcs12 to make it see what it would expect to see there if
10476  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10477  */
10478 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10479                               u32 exit_intr_info,
10480                               unsigned long exit_qualification)
10481 {
10482         struct vcpu_vmx *vmx = to_vmx(vcpu);
10483         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10484
10485         /* trying to cancel vmlaunch/vmresume is a bug */
10486         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10487
10488         leave_guest_mode(vcpu);
10489         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10490                        exit_qualification);
10491
10492         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10493                                  vmcs12->vm_exit_msr_store_count))
10494                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10495
10496         vmx_load_vmcs01(vcpu);
10497
10498         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10499             && nested_exit_intr_ack_set(vcpu)) {
10500                 int irq = kvm_cpu_get_interrupt(vcpu);
10501                 WARN_ON(irq < 0);
10502                 vmcs12->vm_exit_intr_info = irq |
10503                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10504         }
10505
10506         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10507                                        vmcs12->exit_qualification,
10508                                        vmcs12->idt_vectoring_info_field,
10509                                        vmcs12->vm_exit_intr_info,
10510                                        vmcs12->vm_exit_intr_error_code,
10511                                        KVM_ISA_VMX);
10512
10513         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10514         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10515         vmx_segment_cache_clear(vmx);
10516
10517         /* if no vmcs02 cache requested, remove the one we used */
10518         if (VMCS02_POOL_SIZE == 0)
10519                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10520
10521         load_vmcs12_host_state(vcpu, vmcs12);
10522
10523         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10524         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10525
10526         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10527         vmx->host_rsp = 0;
10528
10529         /* Unpin physical memory we referred to in vmcs02 */
10530         if (vmx->nested.apic_access_page) {
10531                 nested_release_page(vmx->nested.apic_access_page);
10532                 vmx->nested.apic_access_page = NULL;
10533         }
10534         if (vmx->nested.virtual_apic_page) {
10535                 nested_release_page(vmx->nested.virtual_apic_page);
10536                 vmx->nested.virtual_apic_page = NULL;
10537         }
10538         if (vmx->nested.pi_desc_page) {
10539                 kunmap(vmx->nested.pi_desc_page);
10540                 nested_release_page(vmx->nested.pi_desc_page);
10541                 vmx->nested.pi_desc_page = NULL;
10542                 vmx->nested.pi_desc = NULL;
10543         }
10544
10545         /*
10546          * We are now running in L2, mmu_notifier will force to reload the
10547          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10548          */
10549         kvm_vcpu_reload_apic_access_page(vcpu);
10550
10551         /*
10552          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10553          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10554          * success or failure flag accordingly.
10555          */
10556         if (unlikely(vmx->fail)) {
10557                 vmx->fail = 0;
10558                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10559         } else
10560                 nested_vmx_succeed(vcpu);
10561         if (enable_shadow_vmcs)
10562                 vmx->nested.sync_shadow_vmcs = true;
10563
10564         /* in case we halted in L2 */
10565         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10566 }
10567
10568 /*
10569  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10570  */
10571 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10572 {
10573         if (is_guest_mode(vcpu))
10574                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10575         free_nested(to_vmx(vcpu));
10576 }
10577
10578 /*
10579  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10580  * 23.7 "VM-entry failures during or after loading guest state" (this also
10581  * lists the acceptable exit-reason and exit-qualification parameters).
10582  * It should only be called before L2 actually succeeded to run, and when
10583  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10584  */
10585 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10586                         struct vmcs12 *vmcs12,
10587                         u32 reason, unsigned long qualification)
10588 {
10589         load_vmcs12_host_state(vcpu, vmcs12);
10590         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10591         vmcs12->exit_qualification = qualification;
10592         nested_vmx_succeed(vcpu);
10593         if (enable_shadow_vmcs)
10594                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10595 }
10596
10597 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10598                                struct x86_instruction_info *info,
10599                                enum x86_intercept_stage stage)
10600 {
10601         return X86EMUL_CONTINUE;
10602 }
10603
10604 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10605 {
10606         if (ple_gap)
10607                 shrink_ple_window(vcpu);
10608 }
10609
10610 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10611                                      struct kvm_memory_slot *slot)
10612 {
10613         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10614         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10615 }
10616
10617 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10618                                        struct kvm_memory_slot *slot)
10619 {
10620         kvm_mmu_slot_set_dirty(kvm, slot);
10621 }
10622
10623 static void vmx_flush_log_dirty(struct kvm *kvm)
10624 {
10625         kvm_flush_pml_buffers(kvm);
10626 }
10627
10628 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10629                                            struct kvm_memory_slot *memslot,
10630                                            gfn_t offset, unsigned long mask)
10631 {
10632         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10633 }
10634
10635 /*
10636  * This routine does the following things for vCPU which is going
10637  * to be blocked if VT-d PI is enabled.
10638  * - Store the vCPU to the wakeup list, so when interrupts happen
10639  *   we can find the right vCPU to wake up.
10640  * - Change the Posted-interrupt descriptor as below:
10641  *      'NDST' <-- vcpu->pre_pcpu
10642  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10643  * - If 'ON' is set during this process, which means at least one
10644  *   interrupt is posted for this vCPU, we cannot block it, in
10645  *   this case, return 1, otherwise, return 0.
10646  *
10647  */
10648 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10649 {
10650         unsigned long flags;
10651         unsigned int dest;
10652         struct pi_desc old, new;
10653         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10654
10655         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10656                 !irq_remapping_cap(IRQ_POSTING_CAP))
10657                 return 0;
10658
10659         vcpu->pre_pcpu = vcpu->cpu;
10660         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10661                           vcpu->pre_pcpu), flags);
10662         list_add_tail(&vcpu->blocked_vcpu_list,
10663                       &per_cpu(blocked_vcpu_on_cpu,
10664                       vcpu->pre_pcpu));
10665         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10666                                vcpu->pre_pcpu), flags);
10667
10668         do {
10669                 old.control = new.control = pi_desc->control;
10670
10671                 /*
10672                  * We should not block the vCPU if
10673                  * an interrupt is posted for it.
10674                  */
10675                 if (pi_test_on(pi_desc) == 1) {
10676                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10677                                           vcpu->pre_pcpu), flags);
10678                         list_del(&vcpu->blocked_vcpu_list);
10679                         spin_unlock_irqrestore(
10680                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10681                                         vcpu->pre_pcpu), flags);
10682                         vcpu->pre_pcpu = -1;
10683
10684                         return 1;
10685                 }
10686
10687                 WARN((pi_desc->sn == 1),
10688                      "Warning: SN field of posted-interrupts "
10689                      "is set before blocking\n");
10690
10691                 /*
10692                  * Since vCPU can be preempted during this process,
10693                  * vcpu->cpu could be different with pre_pcpu, we
10694                  * need to set pre_pcpu as the destination of wakeup
10695                  * notification event, then we can find the right vCPU
10696                  * to wakeup in wakeup handler if interrupts happen
10697                  * when the vCPU is in blocked state.
10698                  */
10699                 dest = cpu_physical_id(vcpu->pre_pcpu);
10700
10701                 if (x2apic_enabled())
10702                         new.ndst = dest;
10703                 else
10704                         new.ndst = (dest << 8) & 0xFF00;
10705
10706                 /* set 'NV' to 'wakeup vector' */
10707                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10708         } while (cmpxchg(&pi_desc->control, old.control,
10709                         new.control) != old.control);
10710
10711         return 0;
10712 }
10713
10714 static void vmx_post_block(struct kvm_vcpu *vcpu)
10715 {
10716         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10717         struct pi_desc old, new;
10718         unsigned int dest;
10719         unsigned long flags;
10720
10721         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10722                 !irq_remapping_cap(IRQ_POSTING_CAP))
10723                 return;
10724
10725         do {
10726                 old.control = new.control = pi_desc->control;
10727
10728                 dest = cpu_physical_id(vcpu->cpu);
10729
10730                 if (x2apic_enabled())
10731                         new.ndst = dest;
10732                 else
10733                         new.ndst = (dest << 8) & 0xFF00;
10734
10735                 /* Allow posting non-urgent interrupts */
10736                 new.sn = 0;
10737
10738                 /* set 'NV' to 'notification vector' */
10739                 new.nv = POSTED_INTR_VECTOR;
10740         } while (cmpxchg(&pi_desc->control, old.control,
10741                         new.control) != old.control);
10742
10743         if(vcpu->pre_pcpu != -1) {
10744                 spin_lock_irqsave(
10745                         &per_cpu(blocked_vcpu_on_cpu_lock,
10746                         vcpu->pre_pcpu), flags);
10747                 list_del(&vcpu->blocked_vcpu_list);
10748                 spin_unlock_irqrestore(
10749                         &per_cpu(blocked_vcpu_on_cpu_lock,
10750                         vcpu->pre_pcpu), flags);
10751                 vcpu->pre_pcpu = -1;
10752         }
10753 }
10754
10755 /*
10756  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10757  *
10758  * @kvm: kvm
10759  * @host_irq: host irq of the interrupt
10760  * @guest_irq: gsi of the interrupt
10761  * @set: set or unset PI
10762  * returns 0 on success, < 0 on failure
10763  */
10764 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10765                               uint32_t guest_irq, bool set)
10766 {
10767         struct kvm_kernel_irq_routing_entry *e;
10768         struct kvm_irq_routing_table *irq_rt;
10769         struct kvm_lapic_irq irq;
10770         struct kvm_vcpu *vcpu;
10771         struct vcpu_data vcpu_info;
10772         int idx, ret = -EINVAL;
10773
10774         if (!kvm_arch_has_assigned_device(kvm) ||
10775                 !irq_remapping_cap(IRQ_POSTING_CAP))
10776                 return 0;
10777
10778         idx = srcu_read_lock(&kvm->irq_srcu);
10779         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10780         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10781
10782         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10783                 if (e->type != KVM_IRQ_ROUTING_MSI)
10784                         continue;
10785                 /*
10786                  * VT-d PI cannot support posting multicast/broadcast
10787                  * interrupts to a vCPU, we still use interrupt remapping
10788                  * for these kind of interrupts.
10789                  *
10790                  * For lowest-priority interrupts, we only support
10791                  * those with single CPU as the destination, e.g. user
10792                  * configures the interrupts via /proc/irq or uses
10793                  * irqbalance to make the interrupts single-CPU.
10794                  *
10795                  * We will support full lowest-priority interrupt later.
10796                  */
10797
10798                 kvm_set_msi_irq(e, &irq);
10799                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10800                         /*
10801                          * Make sure the IRTE is in remapped mode if
10802                          * we don't handle it in posted mode.
10803                          */
10804                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10805                         if (ret < 0) {
10806                                 printk(KERN_INFO
10807                                    "failed to back to remapped mode, irq: %u\n",
10808                                    host_irq);
10809                                 goto out;
10810                         }
10811
10812                         continue;
10813                 }
10814
10815                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10816                 vcpu_info.vector = irq.vector;
10817
10818                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10819                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10820
10821                 if (set)
10822                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10823                 else {
10824                         /* suppress notification event before unposting */
10825                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10826                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10827                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10828                 }
10829
10830                 if (ret < 0) {
10831                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10832                                         __func__);
10833                         goto out;
10834                 }
10835         }
10836
10837         ret = 0;
10838 out:
10839         srcu_read_unlock(&kvm->irq_srcu, idx);
10840         return ret;
10841 }
10842
10843 static struct kvm_x86_ops vmx_x86_ops = {
10844         .cpu_has_kvm_support = cpu_has_kvm_support,
10845         .disabled_by_bios = vmx_disabled_by_bios,
10846         .hardware_setup = hardware_setup,
10847         .hardware_unsetup = hardware_unsetup,
10848         .check_processor_compatibility = vmx_check_processor_compat,
10849         .hardware_enable = hardware_enable,
10850         .hardware_disable = hardware_disable,
10851         .cpu_has_accelerated_tpr = report_flexpriority,
10852         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10853
10854         .vcpu_create = vmx_create_vcpu,
10855         .vcpu_free = vmx_free_vcpu,
10856         .vcpu_reset = vmx_vcpu_reset,
10857
10858         .prepare_guest_switch = vmx_save_host_state,
10859         .vcpu_load = vmx_vcpu_load,
10860         .vcpu_put = vmx_vcpu_put,
10861
10862         .update_bp_intercept = update_exception_bitmap,
10863         .get_msr = vmx_get_msr,
10864         .set_msr = vmx_set_msr,
10865         .get_segment_base = vmx_get_segment_base,
10866         .get_segment = vmx_get_segment,
10867         .set_segment = vmx_set_segment,
10868         .get_cpl = vmx_get_cpl,
10869         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10870         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10871         .decache_cr3 = vmx_decache_cr3,
10872         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10873         .set_cr0 = vmx_set_cr0,
10874         .set_cr3 = vmx_set_cr3,
10875         .set_cr4 = vmx_set_cr4,
10876         .set_efer = vmx_set_efer,
10877         .get_idt = vmx_get_idt,
10878         .set_idt = vmx_set_idt,
10879         .get_gdt = vmx_get_gdt,
10880         .set_gdt = vmx_set_gdt,
10881         .get_dr6 = vmx_get_dr6,
10882         .set_dr6 = vmx_set_dr6,
10883         .set_dr7 = vmx_set_dr7,
10884         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10885         .cache_reg = vmx_cache_reg,
10886         .get_rflags = vmx_get_rflags,
10887         .set_rflags = vmx_set_rflags,
10888         .fpu_activate = vmx_fpu_activate,
10889         .fpu_deactivate = vmx_fpu_deactivate,
10890
10891         .tlb_flush = vmx_flush_tlb,
10892
10893         .run = vmx_vcpu_run,
10894         .handle_exit = vmx_handle_exit,
10895         .skip_emulated_instruction = skip_emulated_instruction,
10896         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10897         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10898         .patch_hypercall = vmx_patch_hypercall,
10899         .set_irq = vmx_inject_irq,
10900         .set_nmi = vmx_inject_nmi,
10901         .queue_exception = vmx_queue_exception,
10902         .cancel_injection = vmx_cancel_injection,
10903         .interrupt_allowed = vmx_interrupt_allowed,
10904         .nmi_allowed = vmx_nmi_allowed,
10905         .get_nmi_mask = vmx_get_nmi_mask,
10906         .set_nmi_mask = vmx_set_nmi_mask,
10907         .enable_nmi_window = enable_nmi_window,
10908         .enable_irq_window = enable_irq_window,
10909         .update_cr8_intercept = update_cr8_intercept,
10910         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10911         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10912         .get_enable_apicv = vmx_get_enable_apicv,
10913         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10914         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10915         .hwapic_irr_update = vmx_hwapic_irr_update,
10916         .hwapic_isr_update = vmx_hwapic_isr_update,
10917         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10918         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10919
10920         .set_tss_addr = vmx_set_tss_addr,
10921         .get_tdp_level = get_ept_level,
10922         .get_mt_mask = vmx_get_mt_mask,
10923
10924         .get_exit_info = vmx_get_exit_info,
10925
10926         .get_lpage_level = vmx_get_lpage_level,
10927
10928         .cpuid_update = vmx_cpuid_update,
10929
10930         .rdtscp_supported = vmx_rdtscp_supported,
10931         .invpcid_supported = vmx_invpcid_supported,
10932
10933         .set_supported_cpuid = vmx_set_supported_cpuid,
10934
10935         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10936
10937         .read_tsc_offset = vmx_read_tsc_offset,
10938         .write_tsc_offset = vmx_write_tsc_offset,
10939         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10940         .read_l1_tsc = vmx_read_l1_tsc,
10941
10942         .set_tdp_cr3 = vmx_set_cr3,
10943
10944         .check_intercept = vmx_check_intercept,
10945         .handle_external_intr = vmx_handle_external_intr,
10946         .mpx_supported = vmx_mpx_supported,
10947         .xsaves_supported = vmx_xsaves_supported,
10948
10949         .check_nested_events = vmx_check_nested_events,
10950
10951         .sched_in = vmx_sched_in,
10952
10953         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10954         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10955         .flush_log_dirty = vmx_flush_log_dirty,
10956         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10957
10958         .pre_block = vmx_pre_block,
10959         .post_block = vmx_post_block,
10960
10961         .pmu_ops = &intel_pmu_ops,
10962
10963         .update_pi_irte = vmx_update_pi_irte,
10964 };
10965
10966 static int __init vmx_init(void)
10967 {
10968         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10969                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10970         if (r)
10971                 return r;
10972
10973 #ifdef CONFIG_KEXEC_CORE
10974         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10975                            crash_vmclear_local_loaded_vmcss);
10976 #endif
10977
10978         return 0;
10979 }
10980
10981 static void __exit vmx_exit(void)
10982 {
10983 #ifdef CONFIG_KEXEC_CORE
10984         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10985         synchronize_rcu();
10986 #endif
10987
10988         kvm_exit();
10989 }
10990
10991 module_init(vmx_init)
10992 module_exit(vmx_exit)